JPH04329071A - Pedestal level detecting circuit - Google Patents

Abstract

PURPOSE:To more stably detect a pedestal level while the influence of the noise is minimized by determining the pedestal level from mean value data. CONSTITUTION:A pedestal level detecting circuit 50 includes data latches 51a-51c to latch Y signal data, R-Y signal and B-Y signal data inputted from each input terminal in response to clock signals CLKa-CLKc and the outputs of the data latches 51a-51c are commonly given to a multiplier 52. In this case, the multiplier 52 is to make input data into 1/n, and the output is given to the one side input of an adder 53. The output of the adder 53 is given to data latches 54a-54c to respond to the clock signals CLKa-CLKc and the outputs are commonly given to a multiplier 55. The multiplier 55 operates (1-1/n) and the output is given to other side input of the adder 53.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a pedestal level detection circuit, and in particular to a pedestal level detection circuit for use in high-definition monitors, for example.
The present invention relates to a pedestal level detection circuit used to determine a pedestal level and add a side panel signal when displaying an SC television signal.

0002

2. Description of the Related Art In order to display video signals of the current NTSC system on a high-definition monitor, an NTSC-HD converter 1 as shown in FIG. 5 is used to cope with differences in aspect ratio. This NTSC-HD converter 1
Then, the composite video signal is converted into digital data by the A/D converter 2, and the EDTV signal processing circuit 3 performs predetermined processing including double speed processing and three-dimensional Y/C separation. Thereafter, the video signal data from the EDTV signal processing circuit 3 is compressed in the horizontal direction by the horizontal time axis compression circuit 4, resulting in an image that can be displayed with an aspect ratio of 4:3 on a high-definition monitor with an aspect ratio of 16:9. Output signal data. At this time, in the margins formed on both sides of the high-definition monitor, side panel signal data set to, for example, the average level of the video signal is inserted in order to prevent unburned areas. The side panel signal data is added based on the pedestal level detected by the pedestal level detection circuit 5.

As shown in FIG. 6, the pedestal level detection circuit 5 converts video signal data such as Y signal data into
It is latched by the data latch 5b in response to a pulse from the monostable multivibrator 5a triggered by the trailing edge of the horizontal synchronization signal Hsync. That is, the data latch 5b samples the pedestal level following the horizontal synchronizing signal Hsync. This pedestal level data is given to an adder 6a included in the additional signal data generation circuit 6, and the adder 6a is further given side panel data, which is the average level of the Y signal, for example, from the side panel data generation circuit 6b. . Therefore, adder 6a outputs side panel signal data superimposed on the pedestal level, which is applied to switching circuit 6c together with pedestal level data from data latch 5b. The switching circuit 6c selectively selects one of the two inputs according to the signal P/S which becomes high level at the timing when the pedestal signal data should be added and becomes low level at the timing when the side panel signal data should be added. Output. In this way, the additional signal data Y' is obtained from the additional signal data generation circuit 6. However, the same applies to other video signals RY and B-Y.
Additional signal data R-Y' and B-Y' are output, respectively.

[0004] Such additional signal data is given to the data addition circuit 7, and the data addition circuit 7 adds the data to the Y signal data, R-Y signal data, and B-Y signal data from the horizontal time axis compression circuit 4, respectively. Signal data Y', R-
Y' and B-Y' are added and provided to the D/A converter 8. The video signal data is converted into an analog video signal by the D/A converter 8, which is converted into RGB by the matrix 9.
decoded into a signal.

[0005]

Problem to be Solved by the Invention The conventional pedestal level detection circuit 5 shown in FIG. 6 samples the pedestal level only once per line.
The drawback was that the pedestal level became unstable due to the influence of noise. Therefore, the main object of the present invention is to provide a pedestal level detection circuit that can detect the pedestal level more stably by reducing the influence of noise.

[0006]

[Means for Solving the Problems] The present invention provides input means for inputting at least two digital data by sampling a video signal at least twice in the same or different pedestal periods, and inputting at least two digital data from the input means. This pedestal level detection circuit is provided with averaging means for obtaining average value data based on the pedestal level detection circuit.

[0007]

[Operation] The input means samples the pedestal level at least twice per line, or once per line for at least two lines, or twice or more per line for two or more lines, and inputs at least two digital data. do. The averaging means obtains average value data based on the at least two digital data, and the pedestal level is determined based on the average value data.

[0008]

According to the present invention, since the pedestal level is determined from average value data, even if there is some noise, the influence of the noise can be reduced. Therefore, the pedestal level can be detected more stably. The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0009]

[Embodiment] The pedestal level detection circuit 50 and additional signal data generation circuit 60 of the embodiment shown in FIG.
This corresponds to the pedestal level detection circuit 5 and additional signal data generation circuit 6 shown in FIG. The pedestal level detection circuit 50 includes a data latch 51a, which latches Y signal data, RY signal data, and BY signal data input from respective input terminals in response to clock signals CLKa, CLKb, and CLKc, which will be described later. 51b and 51
The outputs of data latches 51a, 51b and 51c are commonly given to multiplier 52. Multiplier 52
is for dividing the input data by 1/n, and its output is given to one input of the adder 53. However, "n"
is the number of lines filtered in the vertical direction by the recursive filter. The output of adder 53 is applied to data latches 54a, 54b and 54c responsive to the above-mentioned clock signals CLKa, CLKb and CLKc, and the outputs of data latches 54a, 54b and 54c are applied in common to multiplier 55. This multiplier 55 is (1-1/n)
, and its output is given to the other input of the adder 53 mentioned above. In this way, the data latches 51a to 51c, the multiplier 52, the adder 53, the data latches 54a to 54c, and the multiplier 55 constitute a time division cyclic filter.

A timing signal generation circuit 10 shown in FIG. 2 is provided, and this timing signal generation circuit 10 includes a monostable multivibrator 12 that is triggered by the rising edge (trailing edge) of the horizontal synchronization signal Hsync. The counter 14 is reset by the output of the stable multivibrator 12. The counter 14 is provided with a clock, and thus counts the clock and for each output of the monostable multivibrator 12,
That is, it is reset for each line. counter 14
The count value of is given to the timing decoder 16. The timing decoder 16 outputs clock signals CLKa and C as shown in FIG. 3 according to the count value of the counter 14.
LKb and CLKc and timing signals a, b, c, d
, e and f. Clock signals CLKa to CL
Kc is output during the first pedestal period of each line, and as described above, clock CLKa is applied to data latches 51a and 54a as their latch signals, and clock CLKb is applied to data latches 51b and 54.
b, and the clock CLKc is applied to the data latch 51c.
and 54c. The timing signal a becomes a low level when the cyclic filter calculates the average value of the pedestal level of the Y signal, and the timing signal b becomes a low level when the cyclic filter calculates the average value of the pedestal level of the R-Y signal. Therefore, the timing signal c becomes low level when calculating the average value of the pedestal level of the BY signal in the recursive filter.

Each side panel data from side panel data generating circuits 61a, 61b, and 61c included in the additional signal data generating circuit 60 is commonly applied to one input of an adder 62, and the output of the cyclic filter, that is, The outputs of data latches 54a to 54c are commonly applied to the other input of adder 62. The output of adder 62 is provided to data latches 63a, 63b and 63c, respectively, and the outputs of data latches 54a, 54b and 54c are further provided to data latches 64a, 64b and 64c, respectively. data latches 63a and 64a,
63b and 64b and 63c and 64c include
The timing signal generation circuit 10 in FIG. 2 to FIG. 3, respectively.
Latch signals d, e, and f as shown in FIG.

Data latches 63a and 64a, 63b
The outputs of 64b and 63c and 64c are provided to switching circuits 65a, 65b and 65c, respectively. These switching circuits 65a to 65c, like the conventional switching circuit 6c shown in FIG. 6, use a signal P that becomes high level at the timing when pedestal signal data should be added and becomes low level at the timing when side panel signal data should be added. /S selectively outputs either of the two inputs.

During the period of the timing signal a, the recursive filter operates to detect the pedestal level of the Y signal. That is, the pedestal data of the Y signal obtained by sampling the pedestal level of the Y signal during this period is latched into the data latch 51a in response to the first clock CLKa. The pedestal data of the Y signal latched by the data latch 51 a is multiplied by 1/n by the multiplier 52 and input to the adder 53 . On the other hand, the pedestal data of the Y signal obtained in the previous line, which is latched in the data latch 54a, is multiplied by (1-1/n) by the multiplier 55 and is provided to the adder 53. Therefore, the adder 53 adds 1/2 of the pedestal level of the current line and 1/2 of the pedestal level of the previous line, and outputs average value data. In response to the second clock CLKa, the data latch 51a again latches the pedestal data of the Y signal of the current line. At this time, the average value data previously obtained by the adder 53 as described above is latched into the data latch 54a. Therefore, the above operation is repeated,
The average value of the pedestal level of the Y signal is latched in the data latch 54a again. In this way, the pedestal level is sampled twice (m times) for each line and repeated over multiple lines (n). therefore,
Pedestal data of the Y signal filtered in the horizontal and vertical directions is latched in the data latch 54a, and this data is latched in the data latch 64a in response to the timing signal d.

Further, the pedestal data of the Y signal latched in the data latch 54a is provided to an adder 62, and the adder 62 adds the side panel data and the average pedestal data to output side panel signal data. The side panel signal data is latched into the data latch 63a in response to the timing signal d. Therefore, the switching circuit 65a outputs the Y signal pedestal data from the data latch 64a when the signal P/S is at a high level, and outputs the pedestal data of the Y signal from the data latch 64a when the signal P/S is at a low level.
Side panel signal data of the Y signal is output from a. In this way, the average value data of the pedestal level of the Y signal and the side panel signal data to which the side panel data is added are provided as additional signal data Y' to the data addition circuit 7 shown in FIG. 5.

Note that the operation regarding the RY signal and the BY signal in the embodiment shown in FIG. 1 is similar to the operation regarding the Y signal described above, and therefore, redundant explanation will be omitted here. In this way, in the embodiment shown in FIG. 1, filtering is performed not only in the horizontal direction but also in the vertical direction using a recursive filter, so that the influence of noise can be suppressed, and the pedestal level for each line is stabilized. Since the recursive filter is shared for each signal in a time-division manner, the required circuit scale can be minimized. However, if the number of samplings for one line is m,
The coefficient n of the recursive filter cannot be expected to have a vertical filtering effect unless it is larger than 2m, so 2m<
It is assumed that the relationship is set to n.

FIG. 4 shows another embodiment of the invention. In the embodiment shown in FIG. 1, sampling is performed m times in the horizontal direction, and an average value is obtained for n lines in the vertical direction. However, the embodiment of FIG. 4 eliminates vertical filtering and filters only horizontally. Although this embodiment is somewhat less effective than the embodiment shown in FIG. 1, it is less susceptible to noise than the prior art shown in FIG.

Although only the Y signal is shown in FIG. 4, it should be noted that the same applies to the other signals RY signal and BY signal. Referring to FIG. 4, in pedestal level detection circuit 50' of this embodiment, pedestal data of the Y signal is sequentially latched into two data latches 56a and 57a in response to clock CLKa shown in FIG. The pedestal data latched in data latches 56a and 57a is then applied to averaging circuit 58a. Therefore, the averaging circuit 58a averages different pedestal data in one line and outputs average value data. This average value data is applied to, for example, an adder 6a and a switching circuit 6c similar to those shown in FIG. However, since the subsequent operations are repetitive, they will be omitted.

In the embodiment shown in FIG. 1, one line is sampled m times and averaged over n lines.
It goes without saying that sampling may be performed only once per line and averaging processing may be performed over a plurality of lines, and in the embodiment of FIG. 4, the number of samplings per line may be three or more.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a timing signal generation circuit of the embodiment of FIG. 1;

3 is a timing diagram showing a clock signal and other timing signals output from the timing signal generation circuit of FIG. 2; FIG.

FIG. 4 is a block diagram showing another embodiment of the invention.

FIG. 5 is a block diagram showing an NTSC-HD converter that is the background of the present invention.

FIG. 6 is a block diagram showing a prior art.

[Explanation of symbols]

50, 50'...Pedestal level detection circuit 60
...Additional signal data generation circuits 51a to 51c, 54
a~54c, 63a~63c, 64a~64c, 56a
, 57a...data latch

Claims (1)

[Claims] 1. Input means for inputting at least two digital data by sampling a video signal at least twice in the same or different pedestal periods, and obtaining average value data based on at least two digital data from the input means. A pedestal level detection circuit with averaging means.