JPH04329024A - Input output buffer circuit - Google Patents

Abstract

PURPOSE:To suppress increase of a process and to enhance reliability even when the circuit is interfaced with a device inputting and outputting a signal at a power supply voltage level higher than a power supply voltage of the circuit itself. CONSTITUTION:The input output buffer circuit is provided with an input output terminal PAD inputting and outputting a signal at the outside of the circuit, an input buffer circuit 2 receiving a signal from the input output terminal PAD, an inverter circuit 3 driven by a 1st power supply VCC1, a P-channel MOS transistor(TR) QP3 whose one terminal connects to the 1st power supply VCC1, whose other terminal connects to the input output terminal PAD and whose base connects to a 2nd power supply VCC2, an N-channel MOS TR QN4 connected to a round potential terminal, and an N-channel MOS TR QN2 connecting to the output terminal N3 of the inverter 3 or the like, and even when a signal of the same potential as that of the 2nd power supply VCC2 is inputted from the input output terminal PAD, no forward bias is caused and input leakage current and a through-current are prevented.

Description

[Detailed description of the invention]

[Object of the invention]

0002

[Industrial Application Field] The present invention relates to an input/output buffer,
In particular, the present invention relates to input/output buffers that enable input/output interfaces with devices operating at different power supply voltages.

0003

2. Description of the Related Art A conventional input/output buffer circuit will be described below with reference to the drawings.

FIG. 6 shows a circuit diagram of a conventional input/output buffer circuit. When used as an output buffer, by setting the output activation signal EN to "H", the output data signal Dou
"H"/"L" is output to the output pad PAD according to the "H"/"L" level of t. When used as an input buffer, when the output activation signal EN is set to "L", the gate node N101 of the P-type output transistor QP101 and the gate node N102 of the N-type output transistor QN101 go to "H". and enters the high impedance state of "L", and the PMO from the input pad PAD
A signal is input to the input gate made up of the S transistors QP102 and QN102, and the input signal Din is finally input into the device.

FIG. 7 shows a conceptual diagram of a process cross section related to output nodes N101, N102, and N103. This example shows the case where it is used as an input pad.
Gate N102 is at Vss level, gate N103 is at Vss level.
It is at cc level.

By the way, with the miniaturization of elements, the power supply voltage of the devices themselves has been forced to drop from the viewpoint of reliability. For example, the power supply voltage transition from 5V to 3.3V. In such a case, it is conceivable that the voltage of the device itself is 3.3V, and the other interfacing device operates at 5V. In particular, with the latest microprocessor chips, etc., low voltage 3.3
It is thought that there will be a transition to V, but when configuring a system, 5V devices may be required as peripheral logic and memory. When operating as an input, up to a 5V level is applied to the input level of node N103 in FIG. N well potential is 3.3V; 3.
An input potential of 3V+VF (forward bias potential of the PN junction) or higher causes the PN junction indicated by PN1 in the figure to become forward biased, making the interface impossible. In addition, input gates QP102 and QN10
An input voltage of 5V is applied to the terminal 2, which poses a reliability problem.

[0007] In order to solve the above problem of forward bias,
As shown in FIG. 8, the PMO of the conventional input/output buffer circuit
It is conceivable to connect the N-well potential of the S transistor QP111 to 5V. In Figure 8, the circle mark is 3.3V (Vc
c1), ◎ mark indicates the potential of 5V (Vcc2).

FIG. 9 shows a conceptual diagram of a related process cross section. Even if a 5V level signal is input to node N114, the potential of the N well of node N116 is 5V, so it will not be forward biased. However, when in the input state, P
Since the inverter output N112 at the previous stage of the MOS transistor QP111 is at the Vcc1 level, the PMOS transistor QP111 is turned on when the Vcc2 level is input. QP111 is an output transistor,
Since the PMOS normally has a large channel width, another problem arises in that a large input current i1 flows toward the power supply N115 when turned on.

In order to solve the problems of forward bias and large input leakage current, an example of an input/output buffer as shown in FIG. 10 has been proposed in the literature (Randy Allmon et al.
,”System, and Design Impl
cation of a Reduced Supp
ly Voltage Microprocessor
”, ISSCC'90, Digest, p48,
1990. ). Only the circuits related to problem solving are shown here, and various control circuits are omitted. ○ mark is 3.3V (Vcc1), ◎ mark is 5V
(Vcc2). The forward bias problem is similar to that in Figure 8, when the potential of the N well of the output PMOS transistor is set to V
Connected to cc2 to prevent forward bias. Also, even if 5V is input to the node N124 by the circuit shown by I, the input N12 is passed through the PMOS transistor QP123.
This prevents a large amount of input leakage current from flowing from the power source N125 to the power source N125.

FIG. 11 shows nodes N122, N123, and N1.
The operation in 24 input states is shown. From time t1 “H”
``Starting level input, node N124 exceeds the Vcc1 (3.3V) level at time t2, and at time t3 the node N124 exceeds the Vcc1 (3.3V) level.
c1+Threshold value Vt of PMOS transistor QP122
When the potential of p is exceeded, the PMOS transistor QP123
The potential of gate N123 rises following the potential of node N124, and finally node N123 reaches Vcc2 (5V
). This allows a large output PMO
S transistor QP123 is completely turned off, and a large amount of input leakage current through PMOS transistor QP123 is suppressed.

However, there is a problem with the circuit of the PMOS transistor QP121 and the NMOS transistors QN121 and QN122 in the I section. In order to turn off the output transistor QP123, the PMOS transistor Q
In order to turn on P121 and transmit the level of Vcc1 of node N122, an NMOS transistor QN122 whose gate potential is connected to Vcc2 (5V) is inserted. At the time of output, the level of Vcc1 (3.3V) at the node N122 is transmitted to the node N123, and the PMOS transistor QP123 is surely turned off. NMOS transistor QN
122 functions to conversely transmit the potential of node N123 to node N122 at the time of input. For PMOS transistor QP121, output transistor QP123
Similarly, to avoid forward bias, the N-well potential is set to V
cc2 (5V) is connected. However, as shown in the operation of FIG. 11, the potential of the node N122 is
Due to variations in the characteristics (back bias effect, etc.) of the transistor QN122, there is a possibility that the value becomes Vcc1+α, and there will be an input leak as shown in the path of i2. This input leak current i2 is thought to be about 1 to 2 mA, but in the case of a microprocessor having 100 or more input/output pads, the total input leakage may be 100 mA or more, which is a serious problem.

In addition, in this circuit configuration, the output NMOS transistor QN123, the PMOS transistor QP121 of the circuit I section, and the NMOS transistors QN121, QN1
22 and an input gate (not shown), a potential of 5V level is applied, which poses a problem in terms of process reliability.

[0013]

[Problems to be Solved by the Invention] As described above, in the conventional input/output buffer, its own power supply voltage (for example, 3.3V
) When interfacing with a device that inputs/outputs signals at a higher power supply voltage level (for example, 5V), a large amount of input leakage current may flow, or a high power supply voltage level will be applied to the input gate, which may affect process reliability. There was a drawback that it was a problem.

[0014] The present invention solves the above problems.
The purpose is to provide an input/output buffer circuit that suppresses the increase in process steps and has high process reliability even when interfacing with a device that inputs and outputs signals at a power supply voltage level higher than its own power supply voltage. .

[0015]

[Means for Solving the Problems] In order to solve the above problems, the first feature of the input/output buffer circuit of the present invention is as shown in FIG.
As shown in the figure, the input/output terminal P inputs and outputs signals from outside the circuit.
AD, an input buffer circuit 2 that inputs signals from the input/output terminal PAD, and a first buffer circuit 2 whose one end is connected to the first power supply Vcc1, the other end is connected to the input/output terminal PAD, and the board is connected to the second power supply Vcc2. P-type MOS transistor QP11
and a first N-type MOS transistor QN with one end connected to the input/output terminal PAD and the other end connected to the ground potential terminal.
11, one end of which is connected to the first P-type MOS transistor QP.
a second N-type MOS transistor QN1 whose gate terminal is connected to the first power supply Vcc1, respectively;
2, and one end is connected to the first P-type MOS transistor QP1.
The other end is connected to the input/output terminal PAD, the gate terminal is connected to the first power source Vcc1, and the substrate is connected to the second power source Vcc2.
second P-type MOS transistors QP connected to
12.

The second feature of the input/output buffer circuit of the present invention is that, as shown in FIG. 2, an inverter circuit 3 driven by the first power supply Vcc1, and one end connected to the first power supply Vcc1.
The other end of the board is connected to the input/output terminal PAD to the second power supply Vc.
a first P-type MOS transistor QP3 connected to c2, and a first N-type MOS transistor QP3 connected to the ground potential terminal at one end.
an OS transistor QN4, and one end connected to the first P-type MO
The other end is connected to the gate terminal N4 of the S transistor QP3, and the other end is connected to the output terminal N3 of the inverter 3, and the gate terminal is connected to the first power supply V.
a second N-type MOS transistor QN2 connected to cc1, one end connected to the gate terminal N4 of the first P-type MOS transistor QP3, and the other end connected to the input/output terminal PAD.
a second P-type MOS transistor QP2 whose gate terminal is connected to the first power supply Vcc1 and whose substrate is connected to the second power supply Vcc2, and one end of which is connected to the input/output terminal PAD, and the other end of which is connected to the first N-type MOS transistor. A third terminal whose gate terminal is connected to the first power supply Vcc1 at the other end N5 of QN4, respectively.
An N-type MOS transistor QN3 has one end connected to the input/output terminal PAD and the other end connected to the input terminal N6 of the input buffer circuit 2.
and a fourth N-type MOS transistor QN5 whose gate terminals are connected to the first power supply Vcc1.

The third feature of the present invention is as claimed in claim 1 or 2.
In the input/output buffer circuit described in , the threshold value of the second N-type MOS transistor QN12 or QN2 is set to a value lower than the threshold values of the other N-type MOS transistors.

A fourth feature of the present invention is the input/output buffer circuit according to claim 1, 2, or 3, wherein the first
The P-type MOS transistor QP11 or QP3 is set to a threshold value higher than the threshold value of the other P-type MOS transistors.

The fifth feature of the present invention is as set forth in claims 1, 2, and 3.
, or 4, wherein the input/output buffer circuit includes a first N-well to which a first power supply is applied and a second N-well to which a second power supply is applied. It is to be.

[0020]

[Operation] In the input/output buffer circuit according to the first feature of the present invention, the respective substrates of the first P-type MOS transistor QP11 and the second P-type MOS transistor QP12 are connected to the second power supply Vcc2. , even if a signal having the same potential as the second power supply Vcc2 is input to the input/output terminal PAD, it will not be forward biased. Thereby, it is possible to interface with a device whose power supply voltage (voltage of the first power supply) is higher than that at which it operates.

In the input/output buffer circuit according to the second feature of the present invention, on the output side, there is a first P-type MOS for output whose source is connected to the first power supply Vcc1 and whose substrate is connected to the second power supply Vcc2. One end of a second N-type MOS transistor QN2 connected in series to the output terminal N3 of the output control inverter 3 is connected to the gate of the transistor QP3, and a second power supply Vcc2 is connected to the gate terminal of the substrate connected in series to the input/output terminal PAD. The second power supply Vcc1 is connected to the second
A third N-type MOS transistor QN3, whose gate terminal is connected to the first power supply Vcc1, is connected to the input/output terminal PAD, and the ground is connected to the gate terminal of the third N-type MOS transistor QN3. A first N-type MOS connected to each output terminal N2 of the output control circuit 1
The fourth N-type MOS transistor QN5 is inserted between the input/output terminal PAD and the input buffer circuit 2 on the input side. Therefore, the problem of forward bias can be solved in the same way as in the input/output buffer circuit of the first feature. Furthermore, when the "H" level is input from the input/output terminal PAD, the potential of the input/output terminal PAD rises from 0V,
First power supply Vcc1 + second P-type MOS transistor Q
When the threshold value of P2 reaches the level of Vtp, the second P
The P-type MOS transistor QP2 is turned on and the potential of the input/output terminal PAD rises to the second power supply Vcc2, while the gate potential of the first P-type MOS transistor QP3 follows and rises to the second power supply Vcc2. The first P-type MOS transistor QP3 is turned off, and the first P-type MOS transistor QP3 is turned off.
It is possible to cut a path for a large amount of input leakage current flowing from the input/output terminal PAD toward the first power supply Vcc1 through the S transistor QP3. Further, when an "L" level is input from the input/output terminal PAD, both the ground side and the power supply side can be maintained in a high impedance state.

Furthermore, in the input/output buffer circuit according to the third or fourth feature of the present invention, by satisfying the respective requirements, it is possible to prevent through current during input/output operations.

[0023]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 shows a configuration diagram of an input/output buffer circuit according to a first embodiment of the present invention.

The integrated circuit including the input/output buffer circuit of this embodiment is supplied with a power supply voltage Vcc1 of, for example, 3.3V as an operating main power supply. The output circuit transistors connected to pad PAD are PMOS transistors QP3 and N.
Consisting of MOS transistors QN3 and QN4,
The N-well which is the substrate of the PMOS transistor QP3 is connected to the level potential of the operating power supply voltage Vcc2 of the interfacing device. Here, Vcc2 may be higher than 3.3V, for example 5V. Here the manufacturing process is P
In the case of type substrates, no additional processing is required to fabricate two different types of N-wells.

First, a gate control circuit for PMOS transistor QP3 will be explained. The output node N1 of the input/output control circuit block 1 to which the output data signal Dout and the output activation signal EN are input is a PMOS
An NMOS transistor Q is input to an inverter circuit 3 consisting of a transistor QP1 and an NMOS transistor QN1, and its output N3 is connected to the gate voltage Vcc1.
The configuration is such that one end of the NMOS transistor QN2 is connected to one end of the NMOS transistor QN2, and the other end of the NMOS transistor QN2 is connected to the gate terminal N4 of the PMOS transistor QP3. Also, gate terminal N4 and pad PAD
A PMOS transistor QP2 whose gate voltage is connected to Vcc1 and whose substrate N-well is connected to Vcc2 is inserted between the two.

Next, NMOS transistors QN3 and Q
The gate control circuit of N4 will be explained. N
The gate terminal of the MOS transistor QN3 is connected to Vcc1, and the gate terminal of the NMOS transistor QN4 is connected to the output node N2 of the input/output control circuit block 1. The circuit related to the input side is an NMOS transistor Q whose gate terminal is connected to Vcc1.
Pad PAD is connected to one end of N5, and the other end is connected to input buffer circuit 2.

The operation of the input/output buffer circuit shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows a schematic diagram of operation timing waveforms of each node when the input/output buffer circuit of FIG. 1 is used as an output buffer. Output data signal Dout
, node N1 changes from 0V to Vc at time t0.
Standing up on c1. In response to this, the inverter output N3 becomes 0V, and the node N4 becomes 0V through the NMOS transistor QN2, so that the output PMOS transistor QP3 is turned on. As a result, time t1
At this point, Vcc1 is outputted to pad PAD as "H" level. At this time, the node N2 falls from Vcc1 to 0V at time t0, and the output NMOS transistor QN4 is in the off state, so there is no problem with the through current path in the output stage. Also, PMOS transistor Q
P2 always remains off and has no effect on operation.

Next, depending on the output data signal Dout,
A case where node N1 falls from Vcc1 to 0V at time t2 will be described. In response to the voltage change at node N1, inverter output N3 outputs Vcc1. In response to this, NMOS transistor QN2 has a gate voltage of Vc.
c1, the node N4 which is the gate terminal of the PMOS transistor QP3 has Vcc1-Vtn(QN2).
This results in the transmission of a level potential of . Here, Vtn(
QN2) is a value related to the threshold value of the NMOS transistor QN2. If the PMOS transistor QP3 is set to be turned off by the gate input of this Vcc1-Vtn (QN2), the problem of through current will disappear, and the node N2 that rises from 0V to Vcc1 in response to the output data signal Dout will be turned off by the NMOS transistor QP3. The transistor QN4 is turned on, and the series NMOS transistors QN3 and QN4 output an "L" level (0V) to the pad PAD at time t3.

Here, the PMOS transistor QP3
In order to satisfy the off condition of (1) Vtn(QN
2) It is possible to reduce the value of , that is, to reduce the threshold value of the NMOS transistor QN2. One possible method for this is to adjust the threshold value by adjusting the amount of impurity implanted. In particular, when the gate material is N-type polysilicon, the intrinsic threshold value produced without performing this control impurity implantation is small, and if the conditions are satisfied with that value, there is no need for additional processes, which is desirable.

(2) There is also a method of increasing the threshold value of the PMOS transistor QP3. PMOS transistor Q
The board of P3 is connected to Vcc2, for example, Vcc
Assuming that 1 is 3.3V and Vcc2 is 5V, this means that the substrate voltage is +1.7V. The absolute value of the threshold value of the PMOS transistor QP3 is originally higher than that of the PMOS connected to the other substrate Vcc1 in the chip. It is sufficient if this condition is satisfied, and similarly to (1), it is possible to adjust the threshold value to become larger by adjusting the amount of implanted impurities for controlling the threshold value. Particularly when the gate material is N-type polysilicon, the intrinsic threshold value produced without implanting the control impurity increases, which is desirable since there is no need for additional processes.

It is conceivable to adopt either or both of the above (1) and (2) to satisfy the conditions.

Next, input will be explained. Figure 3 is Figure 1
2 is a schematic diagram of operation timing waveforms of each node when the input/output buffer circuit of FIG. 1 is used as an input buffer. Since it is in the input state, the outputs N1 and N2 of the input/output control circuit block 1 output 0V. The 0V of the output N2 turns the NMOS transistor QN4 off, and the ground side of the output stage goes into a high impedance state. Further, the node N3 receiving the output N1 continues to maintain the Vcc1 level potential, and as in the explanation at the time of output, the gate terminal N4 of the PMOS transistor QP3 is connected to the node N3.
The potential becomes Vcc1-Vtn (QN2), and a high impedance state on the power supply side is guaranteed.

First, the case where "H" level is input from pad PAD at time t0 will be described. First, the potential of pad PAD rises from 0V and becomes Vcc1+Vt.
When the level increases to p, the PMOS transistor QP2
turns on, and then the potential of pad PAD rises to the level of Vcc2, while node N4 follows and rises to Vcc2.
2, turning off the PMOS transistor QP3 and cutting off the path of the large input leakage current flowing from the pad PAD toward Vcc1 through the PMOS transistor QP3. Note that even if the potential of the node N4 rises to Vcc2, the gate voltage of the NMOS transistor QN2 remains Vcc1, and the voltage of the node N3 does not become higher than Vcc1.

Furthermore, when the "L" level is input from the pad PAD at time t2, the node N4
is the potential of Vcc1-Vtn(QN2),
The PMOS transistor QP3 is guaranteed to be in a high impedance state on the power supply side, and the gate voltage of the NMOS transistor QN4 as well as the ground side is maintained in a high impedance state by the 0V input to the node N2. As explained above, the output circuit can maintain a high impedance state on both the ground side and the power supply side.

The input side circuit is composed of an NMOS transistor QN5 whose gate voltage is connected to Vcc1 and an input buffer circuit block 2.
0 from the pad PAD, and after passing through the NMOS transistor QN5, the node N6 receives Vcc.
1-Vtn (QN5) level is transmitted. In response to this, the input buffer 2 outputs a high level of Vcc1 at time t1.
Transmit the level to the inside of the chip. Further, when the "L" level of 0V is input from the pad PAD at time t2, the node N6 follows and becomes 0V, and the input buffer circuit block 2 that receives this inputs the "L" level inside the chip at time t3. Communicate.

In the input/output buffer circuit of this embodiment shown in FIG. 1, the absolute voltage is Vcc1 during the input/output operation described above.
Since a voltage exceeding the magnitude of is never applied between the gate and the drain/source, there is a great advantage that no large electric field is applied to the gate oxide film, eliminating problems with process reliability of NMOSFETs and PMOSFETs.

FIG. 4 shows a second embodiment of the present invention.
Only the circuit portions for solving the forward bias problem are selected and illustrated. Although the input/output operation will be omitted, it is essentially the same as the circuit diagram of FIG.

FIG. 5 shows a cross-sectional view of a process related to the present invention. For devices with only Psub Logic on the substrate, there is no need to add to the normal well process. In addition, when the board is Psub and memory is mixed, and when the board is Ns
In the case of ub, a process with a triple well structure as shown in FIG. 2(b) is required.

[0041]

As described above, according to the present invention, a device whose power supply voltage is higher than its own operating power supply voltage (for example, a logic device or a memory device which operates at another 5V even if its own power supply voltage is 3.3V) It is possible to provide an input/output buffer that can be directly interfaced with the input/output buffer to configure a system with no input leakage current at the time of input.

Particularly when the substrate is of P type, there is no need to add a new PEP to the normal CMOS process, which is effective.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an input/output buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of operation timing waveforms of each node when the input/output buffer circuit of FIG. 1 is used as an output buffer.

FIG. 3 is a schematic diagram of operation timing waveforms of each node when the input/output buffer circuit of FIG. 1 is used as an input buffer.

FIG. 4 is a configuration diagram of an input/output buffer circuit according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a process related to the input/output buffer circuit of the present invention.

FIG. 6 is a circuit diagram of a conventional input/output buffer circuit (first conventional example).

7 is a schematic process cross-sectional diagram of the input/output buffer circuit of FIG. 6; FIG.

FIG. 8 is a circuit diagram of a conventional input/output buffer circuit (second conventional example).

9 is a schematic cross-sectional process diagram of the input/output buffer circuit of FIG. 8; FIG.

[Figure 10] Conventional input/output buffer circuit (third conventional example)
FIG.

11 is a waveform diagram illustrating an outline of the operation of the input/output buffer circuit of FIG. 10. FIG.

[Explanation of symbols]

1 Input/output control circuit 2 Input buffer circuit 3 Output control inverter circuit QP11, QP3 First P-type MOS transistor Q
P2, QP12 Second P-type MOS transistor QN
4, QN11 First N-type MOS transistor QN1
2, QN2 Second N-type MOS transistor QN3
Third N-type MOS transistor QN5 Fourth N-type MOS transistor PAD Input/output terminal Vcc1 First power supply Vcc2 Second power supply Dout Output data signal Din Input data signal EN Output activation signal

Claims (5)

[Claims] 1. An input/output terminal for inputting/outputting signals from outside the circuit, an input buffer circuit for inputting signals from the input/output terminal, one end of which is connected to a first power supply, the other end of which is connected to the input/output terminal. a first P-type MOS transistor connected to the second power source, a first N-type MOS transistor having one end connected to the input/output terminal and the other end connected to the ground potential terminal, and one end connected to the first P-type MOS transistor; A second transistor whose gate terminal is connected to the first power supply is connected to the gate terminal of the MOS transistor.
an N-type MOS transistor, one end of which is connected to the first P-type M
An input/output buffer comprising a gate terminal of an OS transistor, a second P-type MOS transistor whose other end is connected to the input/output terminal, whose gate terminal is connected to a first power supply, and whose substrate is connected to a second power supply. circuit. 2. An input/output terminal for inputting and outputting signals from outside the circuit, an input buffer circuit for inputting signals from the input/output terminal, an inverter circuit driven by a first power source, and one end connected to the first power source. a first P-type MOS transistor whose other end is connected to the input/output terminal and whose substrate is connected to the second power supply; a first N-type MOS transistor whose one end is connected to the ground potential terminal; a second N-type MOS transistor whose other end is connected to the gate terminal of the P-type MOS transistor, whose other end is connected to the output terminal of the inverter, and whose gate terminal is connected to the first power supply;
an OS transistor, and a second P-type MOS transistor having one end connected to the gate terminal of the first P-type MOS transistor, the other end connected to the input/output terminal, the gate terminal connected to the first power supply, and the substrate connected to the second power supply. a third N-type MOS transistor, one end of which is connected to the input/output terminal, the other end of which is connected to the other end of the first N-type MOS transistor, and a gate terminal of which is connected to the first power supply.
A fourth N-type MOS transistor having one end connected to the input/output terminal, the other end connected to the input terminal of the input buffer circuit, and the gate terminal connected to the first power supply. buffer circuit. 3. The input device according to claim 1, wherein the threshold value of the second N-type MOS transistor is set to a value lower than the threshold values of other N-type MOS transistors. Output buffer circuit. 4. The input/output device according to claim 1, wherein the first P-type MOS transistor is set to a threshold value higher than the threshold value of the other P-type MOS transistors. buffer circuit. 5. The input/output buffer circuit includes a first N-well to which a first power source is applied and a second N-well to which a second power source is applied. 5. The input/output buffer circuit according to 1, 2, 3, or 4.