JPH04326231A - Interface circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of each circuit and to enable a high- accuracy demodulating operation by outputting a lock-up signal together with a demodulated signal when a phase lock loop is synchronized with a transmitted signal and a demodulating means executes the normal operation during the prescribed period. CONSTITUTION:A receiving means 10 is provided to receive a transmitted signal DIN and to generate a first clock according to timing for switching a bit, and a phase lock loop 13 is provided to compare the phase of the first clock DCK with that of the second clock oscillated by a voltage controlled oscillator and to control the oscillation frequency of the voltage controlled oscillator corresponding to phase difference. In the state of locking the phase lock loop 13 to generate the reference clock BCK, when no error is generated at a data demodulation circuit 11 while a sub code detection circuit 14 synthesizes sub code data SBC having the prescribed number of bits, a lock-up signal LUP is outputted together so as to show that the operation of each circuit is normal and that an audio signal ADS and the sub code data SBC are correct.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit that receives a transmission signal on a receiving side when data is transmitted between a plurality of devices.

0002

[Prior Art] When data is transmitted according to a predetermined format between digital audio devices such as compact disc players and digital audio tape recorders, the receiving side of the transmitted signal synchronizes each device with the transmitted signal, and It is configured to demodulate the transmission signal into a format compatible with each device. With this configuration, even if the signal formats used in each device are different, data can be exchanged with each other.

[0003] FIG. 3 is a block diagram of an interface circuit that receives a transmission signal in a receiving device, and FIG. 4 is a timing diagram showing its operation. A transmission signal DIN sent from a device on the transmitting side is first taken into a receiving circuit 1, and then input from this receiving circuit 1 to a data demodulating circuit 2. This transmission signal DIN is composed of a fixed signal part of 4 bits (a to d) and a data part of 28 bits (1 to 28), for example, in accordance with the format of EIAJ (Electronic Machinery Industries Association of Japan). The signal is continuous. In the receiving circuit 1, switching of bits in the data portion of the transmission signal DIN modulated into a bi-phase code is detected, and a data clock DCK synchronized with the timing of the switching is output. This data clock DCK is input to the phase-locked loop 3, and the data clock DCK
It is configured to generate a reference clock BCK synchronized with K. The phase-locked loop 3 generally consists of a voltage-controlled oscillator, a phase comparator, and a low-pass filter, and the output of the voltage-controlled oscillator whose oscillation frequency is controlled according to the output of the phase comparator is used as the reference clock BCK by the data demodulation circuit 2. supplied to Further, in this phase-locked loop 3, a lock signal LOK indicating that the oscillation of the voltage-controlled oscillator is synchronized with the transmission clock DCK is outputted from the determination of the output of the phase comparator. The data demodulation circuit 2 uses a reference clock BCK synchronized with the transmission signal DIN.
Based on this, the transmission signal DIN is subjected to processing such as parity checking of each bit and demodulation to a format compatible with the audio equipment, and the audio signal ADS in the desired format synchronized with the transmission signal DIN is output to the next stage circuit. do. For example, the audio signal ADS is the transmission signal D
Audio data represented by 16 bits of the 28-bit data portion of IN is extracted, and this 16-bit audio data is associated with the latter 16 clock periods of each data period. At this time, the data portion of the transmission signal DIN other than the audio data is assigned communication data between the transmitting side device and the receiving side device, etc., and is subjected to predetermined processing in the data demodulation circuit 2 and the next data is transmitted along with the audio signal ADS. It is supplied to the stage circuit. In addition, in the case of a stereo compatible audio signal ADS, data on the L channel side and data on the R channel side are output alternately, and the channel discrimination signal LRCK that sets the timing of switching between these data is It is output from the demodulation circuit 2 together with the audio signal ADS.

On the other hand, the transmitting device is configured to modulate the signal from the format corresponding to the audio device to a predetermined format common to each audio device and then send it to the transmission line. Therefore, according to such an interface circuit, the transmission signal D is
Since the audio signal ADS can be obtained in synchronization with IN and in a format compatible with each audio device, it is possible to transmit signals even if the signal formats differ between the audio devices.

By the way, in the specific bits of the data portion of the transmission signal DIN, an appropriate number of bits of subcode data are stored in a data period corresponding to the number of bits (one data period is 32
1 bit is assigned to each data over a period of 64 clock periods), and this subcode data is taken in and synthesized in the data demodulation circuit 2 one bit at a time in one data period. For example, for 28-bit subcode data, 28
One bit is assigned to a specific bit during each data period, and 28-bit subcode data is obtained by taking in this specific bit into a register continuously during 28 data periods.

[0006]

[Problem to be Solved by the Invention] In the circuit receiving various signals output from the above-mentioned interface circuit, only when the lock signal LOK indicating the locked state of the phase lock loop 3 is output. It is configured to take in the audio signal ADS and the channel discrimination signal LRCK to prevent malfunction of the circuit. That is, the reference clock BCK generated by the phase-locked loop 3
If the data demodulation circuit 2 is not synchronized with the data clock DCK, the data demodulation circuit 2 will not perform the correct demodulation operation, so the reliability of the data of the audio signal ADS will be lost, and the capture of such audio signal ADS will be stopped. .

However, when multiple bits of subcode data are assigned one bit to each data over multiple data periods, the voltage is If the phase lock loop 3 loses lock even once due to fluctuations in the oscillation of the controlled oscillator, power supply noise, etc., the timing at which subcode data is captured is shifted, and data of a different bit from the bit to which the subcode data was assigned is captured. There is a possibility. Therefore, even if the phase-locked loop 3 is in a locked state at a specific timing, a problem arises in that the subcode data obtained at that time is not necessarily correct.

[0008]

[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems, and its feature is that a transmission signal of a predetermined format sent from a transmitting device is transmitted to a receiving device. In an interface circuit that receives the transmission signal and demodulates the transmission signal into a format compatible with the receiving device, and generates a basic clock synchronized with the transmission signal, a first circuit receives the transmission signal and follows the bit switching timing. a phase-locked loop that compares the phase of the first clock with a second clock oscillated by a voltage-controlled oscillator and controls the oscillation frequency of the voltage-controlled oscillator according to the phase difference; demodulating means for demodulating the transmission signal into a desired format based on the second clock; and determining an error in the demodulated signal demodulated by the demodulating means, and detecting an error when an error occurs within a predetermined period. an error detection circuit to detect;
If the error detection circuit does not detect an error within a predetermined period after the phase-locked loop synchronizes with the first clock, a lock-up signal indicating that the operation of the demodulation circuit is normal is applied to the demodulation signal. The present invention also includes an output means for additionally outputting the output.

[0009]

[Operation] According to the present invention, when the phase-locked loop is in synchronization with the transmission signal and the demodulation means operates normally during a predetermined period, the lock-up signal is output together with the demodulation signal. It is possible to determine whether or not the demodulated signal obtained from the demodulation means includes an error within that period, and by taking the demodulated data into the next stage circuit according to this determination, the demodulated signal containing the error is transferred to the receiving side. It will no longer be imported into the device.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an interface circuit according to the present invention. The transmission signal DIN sent from the transmitting device is first input to the receiving circuit 10, where the bit switching timing is detected and the data clock DCK is created. The data is input to the data demodulation circuit 11. This transmission signal DIN is modulated into a biphase code, and 32-bit data according to the EIAJ format is serially arranged as in FIG. 4. here,
When the transmission signal DIN is stereo compatible, L channel data and R channel data are alternately repeated as shown in FIG. is configured. The data clock DCK synchronized with the data switching timing of the transmission signal DIN is input to the phase lock loop 13.
The reference clock BCK that is generated is the data clock DCK.
A reference clock BCK synchronized with the transmission signal DIN is supplied to the data demodulation circuit 11 and the subcode detection circuit 14 which takes in the subcode from the data demodulation circuit 11.

The data demodulation circuit 11 that receives the transmission signal DIN from the reception circuit 10 performs predetermined signal processing on the transmission signal DIN based on the reference clock BCK, and outputs the audio signal ADS in a desired format to the next stage circuit. do. In the signal processing here, processing similar to that shown in FIG. 4 is performed, and for example, 16
An audio signal ADS is obtained in which 16 bits of audio data are associated with each bit period. This data demodulation circuit 11 is provided with an error detection circuit 12 that detects errors by determining whether or not signal processing has been performed correctly for each frame of the transmission signal DIN, and this detection result is used in a lock-up determination circuit to be described later. 15 is input. Further, the data demodulation circuit 11 is provided with a timing generation section for setting the timing of taking in the transmission signal DIN and the timing of switching the audio signal ADS to be output.
By operating based on the data demodulation circuit 11, the demodulation operation of the data demodulation circuit 11 is synchronized with the transmission signal DIN. Also,
The data demodulation circuit 11 successively extracts subcodes assigned to specific bits of each frame of the transmission signal DIN and supplies them to the subcode detection circuit 14 . That is, as shown in FIG. 2, clocks SCK1 and SCK2 are set in synchronization with specific timing of each frame of the transmission signal DIN, and the transmission signal DIN is set according to these clocks SCK1 and SCK2.
By extracting data of specific bits, subcodes distributed and given to a plurality of frames of the transmission signal DIN are configured to be taken into the subcode detection circuit 14. Here, the clocks SCK1 and SCK2 are created by the timing generation section of the data demodulation circuit 11, and if no error occurs in the data demodulation circuit 11, the transmission signal D
Timing pulses are set that correspond to specific bits of each frame of IN.

The subcode detection circuit 14, which receives the subcode from the data demodulation circuit 11, is composed of a register that operates in synchronization with the reference clock BCK, and detects the subcode from the data demodulation circuit 11 for each frame of the transmission signal DIN. One bit at a time is continuously captured, and when a predetermined frame has elapsed, a predetermined bit of subcode data SBC is obtained and output. For example, when the subcode data has a 28-bit configuration, the subcode is given over 28 frames of the transmission signal DIN, and 28 bits of subcode data are synthesized every 28 frames. Then, a signal indicating a period from the timing of taking in the first bit of the subcode data SBC to the timing of taking in the final bit is given to the lockup judgment circuit 15 from this subcode detection circuit 14, and during this period, the lockup judgment circuit 15 15, a lock-up signal indicating that the operation of each part is normal is generated based on the detection result of the error detection circuit 12 that detects an error occurring in the data demodulation circuit 11 and a lock signal indicating that the phase lock loop 13 is locked. Output LUP. That is, the lock-up determination circuit 15 continuously or intermittently detects the occurrence of an error in the data demodulation circuit 11 and the phase lock during the period from when the sub-code detection circuit 14 takes in the first bit of the sub-code to when it takes in the final bit. It is determined whether the loop 13 is locked, and if the phase lock loop 13 does not become unlocked within that period and no error occurs in the data demodulation circuit 11, the operation of each part is normal and the audio signal A
It is configured to output a lockup signal LUP indicating that DS and subcode data SBC do not contain errors.

The lock detection of the phase-locked loop 13 can be recognized from the error detection of the data demodulation circuit 11. It is also possible to generate a lockup signal LUP. That is, by configuring the phase lock loop 13 to be in a locked state and to obtain the lockup signal LUP from the determination result of the error detection circuit 12 during a period when the data demodulation circuit 11 is operating normally, The configuration of the lockup determination circuit 15 can be simplified.

[0014]The circuit connected to the next stage of this interface circuit takes in the audio signal ADS and subcode data SBC in accordance with the lockup signal LUP, thereby preventing errors from occurring in the data demodulation circuit 11. If the phase lock loop 13 loses lock, the audio signal ADS and subcode data SBC will be ignored as containing errors. Therefore, the audio signal ADS or subcode data SBC containing an error will not be taken into the receiving device, and malfunctions can be prevented.

[0015]

[Effects of the Invention] According to the present invention, the interface circuit no longer takes in data that may contain errors to the receiving device, and it is possible to prevent malfunction of each circuit and realize highly accurate demodulation operation. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an interface circuit of the present invention.

FIG. 2 is a diagram showing the format of a transmission signal.

FIG. 3 is a block diagram showing the configuration of a conventional interface circuit.

FIG. 4 is a timing diagram illustrating demodulation operation.

[Explanation of symbols]

1 Receiving circuit 2 Data demodulation circuit 3 Phase-locked loop 10 Receiving circuit 11 Data demodulation circuit 12 Error detection circuit 13 Phase-locked loop 14 Subcode detection circuit 15 Lockup judgment circuit 15

Claims (2)

[Claims] Claim 1: A receiving device receives a transmission signal in a predetermined format sent from a transmitting device, demodulates the transmission signal into a format compatible with the receiving device, and generates a basic clock synchronized with the transmission signal. In the generating interface circuit, receiving means receives the transmission signal and generates a first clock according to the bit switching timing, and a phase comparison of the first clock with a second clock oscillated by a voltage controlled oscillator. a phase-locked loop for controlling the oscillation frequency of the voltage controlled oscillator according to the phase difference; a demodulating means for demodulating the transmission signal into a desired format based on the second clock; an error detection circuit that determines an error in the demodulated signal and detects an error when an error occurs within a predetermined period; and an error detection circuit that detects an error after the phase-locked loop is synchronized with the first clock. An interface circuit comprising output means for adding and outputting a lock-up signal to the demodulation signal indicating that the operation of the demodulation circuit is normal if the detection is not within a predetermined period. 2. A subcode that sequentially takes in subcodes that are allocated and given to specific bits of each data of the transmission signal that is serially transmitted over a certain period of time, and synthesizes a plurality of codes to obtain subcode data. The phase-locked loop is synchronized with the first clock during a period in which the subcode detection means obtains at least one subcode data, and if no error is detected by the error detection circuit, the output is output. 2. The interface circuit according to claim 1, wherein said means adds a lockup signal to said demodulated signal and outputs the resultant signal.