JPH04324981A - Forming method of compound semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a compound semiconductor integrated circuit device where an element Tr mounted on it is micronized and an electrostatic charge outlet path functioning independently of the action of the element Tr is formed. CONSTITUTION:In a compound semiconductor circuit device, a Schottky gate electrode 7 is formed through a lift-off technique using an electron beam drawing method while a constant power 21 is supplied to a P-type semiconductor region 2 which is isolated from a MESFET with a P-N junction and serves as an electrostatic charge outlet path 1.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a compound semiconductor integrated circuit device, and more particularly, to a compound semiconductor integrated circuit device in which patterns of transistor electrodes, wiring, or regions formed on the main surface of a compound semiconductor substrate are formed by electron beam lithography. This invention relates to techniques that are effective when applied to circuit devices.

0002

2. Description of the Related Art A single-structure compound semiconductor device used as a high-frequency oscillator of an optical disk system has a MESFET mounted on the main surface of a semi-insulating semiconductor substrate (compound semiconductor substrate) made of GaAs. Compound semiconductor devices are
As is well known, MOSFETs have higher frequency characteristics than MOSFETs formed on semiconductor substrates made of Si.

The MESFET is mainly composed of a channel region, a source region and a drain region formed as an n-type region on the main surface of a semi-insulating semiconductor substrate, and a Schottky gate electrode formed on the channel region. . This Schottky gate electrode is formed of, for example, aluminum, although it is not limited to this material.

The Schottky gate electrode of the MESFET is formed using a lift-off technique. That is, first, a photoresist film is applied and baked on the main surface of a semi-insulating semiconductor substrate, and then the photoresist film is exposed and developed in the area where the Schottky gate electrode is to be formed. remove the affected area. That is, a photoresist mask having a Schottky gate electrode pattern is formed. The exposure is performed using an electron beam drawing method that does not require a photomask (reticle) during drawing and can form fine patterns. Next, after aluminum is deposited or vapor-deposited on the entire surface including the Schottky gate electrode formation region and the photoresist mask, the photoresist mask and the aluminum formed on the photoresist mask are removed by etching. As a result, aluminum remains only in the region where the Schottky gate electrode is to be formed, and this aluminum is formed as the Schottky gate electrode.

[0005] This type of single-structure compound semiconductor device is
During the electron beam irradiation during the process of forming the Schottky gate electrode described above, the channel region, source region, or drain region in the vicinity is charged (charged up). When this charge-up occurs, the electron beam is charged with the same polarity as the electron beam and repels each other, so the electron beam is scattered and a fine pattern cannot be formed.

Therefore, in conventional single-structure compound semiconductor devices, the n-type region (
For example, a source region) is electrically coupled to a guard ring (n-type region) formed around a semi-insulating semiconductor substrate, and the aforementioned charge-up is absorbed by this guard ring. A semi-insulating semiconductor substrate has a resistance value about four orders of magnitude higher than a semiconductor substrate made of Si, and since it is not possible to form a charge-up release path from the main surface to the back surface, it is necessary to combine it with the guard ring described above. A discharge path for charge-up must be constructed.

[0007] A compound semiconductor integrated circuit device having a MESFET is described, for example, in IEICE technical report, ED86-12, pages 41 to 46.

[0008]

Problem to be Solved by the Invention However, the present inventor has attempted to convert a compound semiconductor device of a single structure into a plurality of MEs.
Prior to the development of a compound semiconductor integrated circuit device (IC or LSI) in which SFETs are integrated and a circuit is assembled, the following problems were discovered.

In the manufacturing process of compound semiconductor integrated circuit devices, when patterns are formed using electron beam lithography, the patterns are formed between the source regions, between the drain regions, and between the source and drain regions of a plurality of MESFETs. If all of the above are combined to form the charge-up emission path described above, scattering of the electron beam can be suppressed. However, during actual use of compound semiconductor integrated circuit devices (during normal operation),
An independent signal or power supply is supplied to each of the source region and drain region of the MESFET, or multiple MESFETs
Different and independent signals and power supplies are supplied between each of them. Therefore, if the charge-up release path described above is secured, it is impossible to configure a circuit system (it does not function as an integrated circuit), and a compound semiconductor integrated circuit device cannot be realized.

An object of the present invention is to provide a technique that enables the realization of a compound semiconductor integrated circuit device and the miniaturization of elements mounted on this compound semiconductor integrated circuit device.

Another object of the present invention is to provide a technique in which a charge-up release path that acts independently on the operation of the device can be formed in a compound semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0013]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

A method for forming a compound semiconductor integrated circuit device in which patterns of electrodes, wiring, or regions of a plurality of transistors constituting an integrated circuit arranged on the main surface of a semi-insulating semiconductor substrate are formed by electron beam lithography. The transistor forming region of each of the plurality of transistors on the main surface of the semi-insulating semiconductor substrate and each region other than the transistor forming region are mutually short-circuited, and the channel conductivity type of the transistor is a step of forming a semiconductor region set to have a conductivity type opposite to that of the semi-insulating semiconductor substrate; While a fixed potential having a relatively opposite polarity is applied to the main surface of the semiconductor region formed in the transistor formation region, any of the electrodes, wiring, or regions of a plurality of transistors is formed using an electron beam lithography method. and a step of forming the pattern. The semi-insulating semiconductor substrate is a GaAs semiconductor wafer, and the transistor is an n-channel conductivity type ME.
It is an SFET, and the semiconductor region is a p-type semiconductor region.

[0015]

[Operation] According to the above-mentioned means, when forming patterns of electrodes, wiring or regions of a plurality of transistors of an integrated circuit of the compound semiconductor integrated circuit device by electron beam drawing,
Charges that are charged up in the transistor formation region by electron beam irradiation are transferred to the semiconductor region of the transistor formation region and the region other than the transistor formation region (charge-up outlet), which has a lower resistance value than the semi-insulating substrate. Since it can be taken out to the outside of the semi-insulating substrate through each, scattering of electron beams caused by the above-mentioned charging can be reduced, and patterns can be made finer.

Further, the semiconductor region formed in the transistor formation region is formed with a conductivity type opposite to the channel conductivity type of the transistor, and since the semiconductor region and the transistor are separated from each other by a pn junction, the normal During operation, it is possible to prevent short circuits between the plurality of transistors and short circuits between each of the plurality of transistors and the semiconductor region.

The structure of the present invention will be described below in which a plurality of MESs are formed on the main surface of a semi-insulating semiconductor substrate made of GaAs.
An embodiment will be described in which the present invention is applied to a compound semiconductor integrated circuit device equipped with an FET.

In all the drawings for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (cross-sectional view of essential parts) shows a schematic structure of a compound semiconductor integrated circuit device which is an embodiment of the present invention.

As shown in FIG. 1, a plurality of compound semiconductor integrated circuit devices 10 are formed on a semi-insulating semiconductor wafer (semi-insulating semiconductor substrate) 1. As shown in FIG. The semi-insulating semiconductor wafer 1 shown in FIG. 1 shows a state in which electrode forming processes such as a Schottky gate electrode (7), a source electrode (6), a drain electrode (6), etc. have been completed, and a wiring forming process and a dicing process are completed. Indicates the previous state. The semi-insulating semiconductor wafer 1 is made of GaA
Formed by s.

Although only one element is shown for convenience in each of the plurality of compound semiconductor integrated circuit devices 10 of the semi-insulating semiconductor wafer 1, a plurality of MESFETs (Tr) constituting an integrated circuit are mounted thereon. Ru. Multiple MES
Each of the FETs is of n-channel conductivity type, and includes an n-type channel region 4, an n-type source region 3, and an n-type drain region 3.
and a Schottky gate electrode 7.

The MESFET is formed on the main surface of a p-type semiconductor region (p-type well region or p-type buried region) 2 formed on the main surface of a semi-insulating semiconductor wafer 1, and this p-type semiconductor region 2 has a plurality of The MESFETs are electrically isolated from each other.

The n-type channel region 4, source region 3, and drain region 3 of the MESFET are all p-type semiconductor regions 2.
Constructed on the main surface of. The Schottky gate electrode 7 is
Although not limited to this material, it is made of, for example, aluminum or an aluminum alloy.

Schottky gate electrode 7 of MESFET
Although not shown in FIG. 1, they are connected to wiring formed in a step after the step shown in FIG. For example, this wiring is T
It is formed of a composite film in which an iW film and an Al-Si alloy film are sequentially laminated from the bottom layer to the top layer. The source region 3 is connected to the same wiring as described above through the source electrode 6, and the drain region 3 is connected to the wiring through the drain electrode 6. Each of the source electrode 6 and the drain electrode 6 is formed within a region defined by the insulating film 5, and is formed of a composite film in which, for example, an AuGe film, a Ni film, and an Au film are sequentially laminated as ohmic contact electrodes. Ru.

In this embodiment, the p-type semiconductor region 2 is formed for each of a plurality of compound semiconductor integrated circuit devices 10,
Furthermore, the p-type semiconductor regions 2 formed in each of the plurality of compound semiconductor integrated circuit devices 10 are electrically coupled (integrated) to each other. That is, in this example,
The p-type semiconductor region 2 is formed over the entire main surface of the semi-insulating semiconductor wafer 1. This p-type semiconductor region 2 is also formed in the peripheral region (corresponding to the charge-up outlet) of the main surface of the semi-insulating semiconductor wafer 1, and the p-type semiconductor region 2 formed in this peripheral region are electrically coupled (integrated) similarly to the respective p-type semiconductor regions 2 formed for each of the plurality of compound semiconductor integrated circuit devices 10.

This p-type semiconductor region 2 is used as a discharge path for charge-up from the vicinity of each of the plurality of MESFETs of the plurality of compound semiconductor integrated circuit devices 10 to the peripheral edge region of the semi-insulating semiconductor wafer 1. be done. An n-type extraction region 3 is formed on the main surface of the p-type semiconductor region 2 formed in the peripheral edge region of the semi-insulating semiconductor wafer 1, and an ohmic contact electrode is formed on the main surface of the n-type extraction region 3. A take-out electrode 6 is configured.

Between the p-type semiconductor region 2 used as the discharge path for the charge-up and each of the plurality of MESFETs of the plurality of compound semiconductor integrated circuit devices 10, there is a parasitic region as seen from the MESFET side. A diode element D1 inserted in reverse bias is constructed. Similarly, p
A diode element D2 inserted with a reverse bias when viewed from the n-type extraction region 3 is configured between the type semiconductor region 2 and the n-type extraction region 3 formed in the peripheral edge region of the semi-insulating semiconductor wafer 1. Ru. In particular, the former diode element D1 has a voltage range that does not exceed its threshold voltage, that is, MESFE
During normal operation of T, the MESFET and p-type semiconductor region 2 can be separated by pn junction. Conversely, if diode element D1 exceeds its threshold voltage, MESFE
Current can flow between T and p-type semiconductor region 2. In other words,
When the threshold voltage of the diode element D1 is exceeded, a current path is formed between the MESFET and the n-type extraction region 3 via the diode element D1, the p-type semiconductor region 2, and the diode element D2.

Next, a method for forming a compound semiconductor integrated circuit device 10 using the semi-insulating semiconductor wafer 1 described above will be described using FIGS. 2 to 4 (cross-sectional views of main parts shown for each manufacturing process). , briefly explained.

First, the MESF of the compound semiconductor integrated circuit device on the main surface of the semi-insulating semiconductor wafer 1 made of GaAs is
An n-type source region 3 and an n-type drain region 3 are formed in the ET formation region, and in the same step, an n-type extraction region 3 is formed in the peripheral region of the main surface of the semi-insulating semiconductor wafer 1.

Next, a p-type semiconductor region 2 is formed over the entire main surface of the semi-insulating semiconductor wafer 1. This p-type semiconductor region 2 is formed using, for example, an ion implantation method.

Next, as shown in FIG.
In the ET formation region, an n-type channel region 4 is formed on the main surface of the p-type semiconductor region 2 formed on the main surface of the semi-insulating semiconductor wafer 1.

Next, an insulating film 5 is formed over the entire main surface of the semi-insulating semiconductor wafer 1, and then, as shown in FIG. 3, a part of the insulating film 5 is removed in the MESFET formation region. Then, a source electrode 6 is formed on the n-type source region 3 and a drain electrode 6 is formed on the n-type drain region 3. In the same step as the step of forming the source electrode 6 and the drain electrode 6, the extraction electrode 6 is formed in the peripheral edge region of the main surface of the semi-insulating semiconductor wafer 1. The source electrode 6, drain electrode 6, and extraction electrode 6 are each formed using well-known photolithography and etching techniques.

Next, after removing the insulating film 5 in the MESFET formation region, a photoresist film 8 is formed over the entire main surface of the semi-insulating semiconductor wafer 1 except over the lead-out electrode 6 in the peripheral edge region. Thereafter, as shown in FIG. 4, with the charge absorption needle 20 in contact with the extraction electrode 6 in the peripheral region of the semi-insulating semiconductor wafer 1, an electron beam 9 is applied to the photoresist using an electron beam lithography method. A part of the film 8 is irradiated (exposed) to form a photosensitive area 8A.

The charge absorption needle 20 has a polarity opposite to that charged up by the electron beam 9 (negative polarity) (positive polarity).
A fixed power supply 21 is connected to, for example, a ground potential (ground). As a result, the charge-up generated near the irradiation of the electron beam 9 (the area surrounded by the dotted line in FIG. 4) is
MES of semi-insulating semiconductor wafer 1 in the direction of the arrow
The charge reaches the peripheral region from the FET region through the p-type semiconductor region (charge-up release path) 2, and is emitted from this peripheral region. Therefore, scattering of the electron beam 9 is reduced,
A fine pattern of the photosensitive area 8A can be formed.

Next, using the lift-off technique, the Schottky gate electrode 7 shown in FIG. 1 described above is formed, and as a result, the MESFET is completed. In the lift-off technique, the photosensitive area 8A is removed by development, an aluminum alloy film (or aluminum film) is formed on the entire surface including the removed area and the photoresist film 8, and the photoresist film 8 and its This is a technique that removes the upper aluminum alloy film and leaves the aluminum alloy film in some areas.

In this way, a plurality of MESFs constituting an integrated circuit arranged on the main surface of the semi-insulating semiconductor wafer 1
A method of forming a compound semiconductor integrated circuit device 10 in which the pattern of the Schottky gate electrode 7 of ET is formed by electron beam lithography, and the pattern of the Schottky gate electrode 7 of each of the plurality of MESFETs on the main surface of the semi-insulating semiconductor wafer 1 is In each of the MESFET formation region and the peripheral edge region other than this MESFET formation region,
Both are short-circuited to each other, and the n of the MESFET
A step of forming a p-type semiconductor region 2 having a conductivity type opposite to the channel conductivity type, and a p-type semiconductor region formed in a peripheral region other than the MESFET formation region on the main surface of the semi-insulating semiconductor wafer 1. 2 (actually n-type extraction area 3)
In the above-mentioned state, the MES
A step of forming a pattern of Schottky gate electrodes 7 of a plurality of MESFETs by electron beam lithography on the main surface of the p-type semiconductor region 2 formed in the FET formation region is provided. With this configuration, when forming the patterns of the Schottky gate electrodes 7 of the plurality of MESFETs of the integrated circuit of the compound semiconductor integrated circuit device 10 by electron beam lithography, charge-up generated in the vicinity by irradiation with the electron beam 9 can be avoided. Since the electron beam 9 caused by the charge-up can be extracted to the outside of the semi-insulating semiconductor wafer 1 through the p-type semiconductor region (charge-up emission path) 2, which has a smaller resistance value than the semi-insulating semiconductor wafer 1, This reduces scattering and allows for finer patterns. Further, the p-type semiconductor region 2 formed in the MESFET formation region is formed with a conductivity type opposite to the n-type channel conductivity type of the MESFET, and each of the p-type semiconductor region 2 and the MESFET has a pn junction (diode element D
1), so during normal operation of MESFETs, multiple MESFETs are mutually short-circuited, multiple MESFETs are
Any short circuit between each of the SFETs and the p-type semiconductor region 2 can be prevented.

Furthermore, as shown in FIG. 5 (a cross-sectional view of a main part showing a modified example), the present invention eliminates the extraction electrode 6 in the peripheral edge region of the semi-insulating semiconductor wafer 1 and replaces the n-type extraction region 3. The fixed power source 21 may be directly supplied from the.

Further, the present invention is applicable to the case where a gate preceding process is adopted in which the source electrode 6 and the drain electrode 6 are formed after the Schottky gate electrode 7 is formed in the manufacturing process of the compound semiconductor integrated circuit device 10 described above. It can also be applied to

Further, the present invention provides a compound semiconductor integrated circuit device 10 in which mutually independent (electrically isolated from others) p-p transistors are provided in each region of a plurality of MESFETs or in the vicinity thereof. A p-type semiconductor region (charge-up release path) 2 may be formed, and these individual p-type semiconductor regions may be interconnected with a wiring material or an electrode material (for example, 6).

[0040] Furthermore, in the compound semiconductor integrated circuit device 10 described above, the present invention uses an electron beam lithography method to form electrodes such as the source electrode 6 or regions such as the n-type source region 3 in addition to the Schottky gate electrode 7. may be formed.

[0041] As described above, the invention made by the present inventor is as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof.

For example, the present invention is not limited to GaAs, but can be applied to compound semiconductor integrated circuit devices formed from compound semiconductor wafers such as GaInAs and GaInP.

Furthermore, the present invention can be applied to a compound semiconductor integrated circuit device equipped with a bipolar transistor.

Furthermore, the present invention can be applied to a wafer-scale compound semiconductor integrated circuit device in which one compound semiconductor integrated circuit device is constructed on one semi-insulating semiconductor wafer.

[0045]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

A compound semiconductor integrated circuit device can be realized, and elements mounted on this compound semiconductor integrated circuit device can be miniaturized.

In a compound semiconductor integrated circuit device, it is possible to form a charge-up release path that acts independently on the operation of the device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of essential parts showing a schematic configuration of a compound semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of a first step for explaining the method for forming the compound semiconductor integrated circuit device.

FIG. 3 is a sectional view of the main part of the second step.

FIG. 4 is a sectional view of the main part of the third step.

FIG. 5 is a sectional view of a main part showing another example of the compound semiconductor integrated circuit device.

[Explanation of symbols]

1...Semi-insulating semiconductor wafer (semi-insulating semiconductor substrate),
2...p-type semiconductor region (charge-up release path), 3
...Source region, drain region or take-out region, 4...Channel region, 6...Source electrode, drain electrode or take-out electrode, 7...Schottky gate electrode, 8...Photoresist film, 8A...Photosensitive region, 10...Compound semiconductor integrated circuit Device, 20...Charge-up absorption needle, 21...Fixed power supply, T
r...MESFET.

Claims (2)

[Claims] 1. A compound semiconductor integrated circuit device in which a pattern of electrodes, wiring, or regions of a plurality of transistors constituting an integrated circuit arranged on the main surface of a semi-insulating semiconductor substrate is formed by electron beam lithography. A forming method, wherein a transistor forming region of each of a plurality of transistors on a main surface of the semi-insulating semiconductor substrate and a region other than the transistor forming region are mutually short-circuited, and a channel of the transistor is A step of forming a semiconductor region having a conductivity type opposite to the conductivity type, and applying an electron beam during electron beam lithography to the semiconductor region formed in a region other than the transistor formation region on the main surface of the semi-insulating semiconductor substrate. When a fixed potential of opposite polarity is supplied to
A compound semiconductor comprising the step of forming a pattern of electrodes, wiring, or regions of a plurality of transistors on the main surface of the semiconductor region formed in the transistor formation region by electron beam lithography. A method of forming an integrated circuit device. 2. The semi-insulating semiconductor substrate is a GaAs semiconductor wafer, the transistor is an n-channel conductivity type MESFET, and the semiconductor region is a p-type semiconductor region. compound semiconductor integrated circuit devices.