JPH04323829A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To avoid malfunctioning of an EPROM caused by penetration of moisture, oxygen, etc., and realize levelling of the EPROM surface by high temperature reflow such as pyroflow. CONSTITUTION:An EPROM composed of a first gate insulating film 4, a floating gate 5, a second gate insulating film 6, a control gate 7, an n-type source region 8, a n-type drain region 9, a thermal oxide film 10, etc., is formed on a p-type semiconductor substrate 1. A precise silicon nitride film 15 having a thickness of 20nm-50nm which can prevent moisture, oxygen, etc., from penetration and can transmit an ultraviolet radiation is formed on the EPROM by a CVD method. Then a doped silicon oxide film 11 is formed and the surface of the silicon oxide film 11 is levelled by high temperature reflow such as pyroreflow.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor devices, especially EPR devices.
OM (Erasable and Programab
The present invention relates to a semiconductor device having a semiconductor element constituting an ultraviolet erasable memory such as LE ROM), and a method of manufacturing such a semiconductor device.

0002

[Prior Art] Since information in an EPROM is erased by irradiation with ultraviolet rays, after the semiconductor elements constituting the EPROM are formed, interlayer insulating films, surface protection films, etc. A silicon film is used.

FIG. 2 shows a cross-sectional structure of a conventional semiconductor device having a semiconductor element constituting an EPROM. This semiconductor device will be explained in order of manufacturing steps. First, a transistor formation region 2 and an element isolation region 3 are provided on a p-type semiconductor substrate 1. Next, a first gate insulating film 4, a floating gate 5 made of a polycrystalline silicon film, a second gate insulating film 6, and a control gate 7 made of a polycrystalline silicon film are sequentially laminated on the transistor formation region 2. Using photolithography and etching techniques, patterning is performed as shown in the figure. Note that the polycrystalline silicon films that will become the floating gates 5 and the control gates 7 are subjected to phosphorus doping treatment.

[0004] Thereafter, using well-known ion implantation techniques, n
A shaped source region 8 and drain region 9 are formed. Next, the surface of the transistor formation region is oxidized using a thermal oxidation method to form a thin thermal oxide film (pre-oxide film) 10. Thereafter, a PSG film 11 is formed by a normal chemical vapor deposition method (hereinafter referred to as "CVD method"), and the surface of this PSG film 11 is planarized by performing reflow at a high temperature. Subsequently, using well-known photolithography and etching techniques, contact holes 12, 12, 12, aluminum interconnections 13, 13, 13, etc. are formed, and finally, a surface protection film 14 made of a PSG film or a SiO2 film is formed. . In this way, a device structure capable of transmitting ultraviolet light is completed.

In this semiconductor device, since the surface of the PSG film 11 is flattened by reflow, the PSG film 11
Disconnection of the aluminum wiring 13 due to the step on the surface of the film 11 does not occur.

[0006]

[Problem to be Solved by the Invention] However, in the structure and manufacturing method of the semiconductor device explained with reference to FIG.
Since the film made of SG, SiO2, etc. has poor moisture resistance, the first problem is likely to occur: moisture enters from the surface, reaches the semiconductor element region, and interferes with the normal operation of the element.

[0007] Furthermore, in EPROMs in which information must be erased by ultraviolet irradiation, there is a second problem in that pyroflow, which has been widely used in recent years as an excellent planarization method for interlayer insulating films, cannot be used. because,
To use pyroflow, the already formed EP
In order to prevent oxidation of elements such as ROM, it is essential to provide a silicon nitride film layer in the interlayer film layer, and this silicon nitride film absorbs ultraviolet rays used for erasing information. Planarization of an interlayer insulating film has become an extremely important factor as semiconductor devices become smaller and more highly integrated. However, at present, pyroflow cannot be applied to the manufacture of EPROMs, so the planarization is improved only by increasing the phosphorus concentration of the PSG film to 9 wt% or more and reflowing using ordinary N2. However, when the phosphorus concentration is increased, a new problem arises in that the aluminum wiring becomes susceptible to corrosion due to a chemical reaction between the aluminum wiring, moisture, and phosphorus in the PSG film, even if normal reflow is used.

[0008] The present invention solves the above problems.
An object of the present invention is to provide a semiconductor device that can prevent abnormal operation of a semiconductor element due to the intrusion of moisture, oxygen, etc. A further object of the present invention is to provide a method for manufacturing a semiconductor device that can realize flattening of an element surface by reflow using high temperature such as pyroflow.

[0009]

[Means for Solving the Problem] In order to solve the above-mentioned problem, the invention of claim 1 provides a thin silicon nitride layer between the EPROM and the doped silicon oxide film to prevent moisture and oxygen from entering. It enables prevention and UV transmission.

Specifically, the solution taken by the invention of claim 1 includes an element formed on a semiconductor substrate and capable of erasing information by ultraviolet irradiation, and a 20 nm thick layer formed on the gate of the element by chemical vapor deposition. The structure includes a silicon nitride film with a thickness of ~50 nm and a doped silicon oxide film formed on the silicon nitride film and having a flattened surface.

[0011] Furthermore, the invention according to claim 2 is a method of forming an EPROM by forming a thin silicon nitride layer on the EPROM and forming a doped silicon oxide film on the silicon nitride film.
This makes it possible to flatten the surface of the silicon oxide film by high-temperature reflow such as pyroflow while preventing oxidation of the ROM.

Specifically, the solution taken by the invention of claim 2 includes a step of forming an element whose information can be erased by ultraviolet irradiation on a semiconductor substrate, and a step of forming a 20 nm thick layer on the gate of the element by chemical vapor deposition. The surface of the silicon oxide film is flattened by forming a silicon nitride film with a thickness of ~50 nm, forming a doped silicon oxide film on the silicon nitride film, and performing reflow at a high temperature. The configuration includes the step of:

[0013]

According to the structure of the first aspect of the invention, the dense silicon nitride film formed by the CVD method and having a thickness of 20 nm or more prevents moisture and oxygen from entering the EPROM. Further, since the thickness of the silicon nitride film is 50 nm or less, the absorption loss of ultraviolet rays is slight, and information can be erased with an ultraviolet irradiation time that does not cause any practical problems.

[0014] Furthermore, according to the structure of the invention of claim 2, CV
A dense silicon nitride film with a thickness of 20 nm or more formed by the D method functions as a barrier against moisture, oxygen, and the like. Therefore, even if reflow using high temperature such as pyroflow is performed after forming a doped silicon oxide film on this silicon nitride film, the already formed EPROM can be protected from oxidation.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 shows a cross-sectional structure of an embodiment of a semiconductor device according to the present invention, which includes a semiconductor element constituting an EPROM. In the figure, 1 is a p-type semiconductor substrate, 2 is a transistor formation region, 3 is an element isolation region, 4 is a first gate insulating film, 5 is a floating gate made of a polycrystalline silicon film, and 6 is a second gate insulating film. 7 is a control gate made of a polycrystalline silicon film, 8 is an n-type source region,
Reference numeral 9 indicates an n-type drain region, and reference numeral 10 indicates a thin thermal oxide film formed by a thermal oxidation method, which constitute an EPROM, and are all the same as in the conventional example shown in FIG. Further, these are manufactured by the same manufacturing method as the conventional example shown in FIG.

After forming the thermal oxide film 10, for example, S
100m using iH2 Cl2 gas and NH3 gas
Under reduced pressure of Torr to 1 Torr, 700°C to 800°C
The film thickness is 20nm to 50nm by CVD method at a reaction temperature of ℃.
A silicon nitride film 15 is grown controlled to m. In this example, the thickness of the silicon nitride film 15 was set to 40 nm. If the thickness of the silicon nitride film 15 is less than 20 nm, the barrier ability against moisture and oxygen will be insufficient;
If it exceeds m, the absorption loss of ultraviolet rays becomes large and EPRO
This is not practical because it takes a long time to erase the information on M. The silicon nitride film 15 is formed using, for example, SiH4 gas or NH3 gas at 700°C to 850°C under atmospheric pressure.
It can also be formed by a CVD method at a reaction temperature of .degree. Thereafter, a PSG film 11 with a phosphorus concentration of 7 wt% to 9 wt% is formed to a thickness of 700 nm to 700 nm using a well-known normal pressure or low pressure CVD method.
It is grown to a thickness of 1000 nm. Next, pyroflow is performed at 900° C. for 90 minutes using H2 gas and O2 gas. Thereafter, contact holes 12 and 1 are formed on the control gate 7, the source region 8, and the drain region 9, respectively.
2 and 12 are formed. Next, aluminum wiring 13, 1
After forming 3 and 13, a surface protective film 14 is formed. Contact hole 12, aluminum wiring 13, surface protection film 1
4 has the same configuration as the conventional example. In this way, the semiconductor device of this example is completed.

The semiconductor device of this embodiment includes a PSG film 11.
The thickness of the layer formed by CVD method is 20 nm ~
Since the 50 nm thick silicon nitride film 15 is provided, moisture and oxygen are prevented from entering the EPROM. Further, according to the method of manufacturing a semiconductor device of this embodiment, since the silicon nitride film 15 can prevent moisture and oxygen from entering, the PSG film 11 can be flattened by pyroflow while preventing oxidation of the already formed EPROM. It becomes possible to perform

FIG. 3 shows the actual device erase characteristics of the semiconductor device of this embodiment shown in FIG. 1 and the conventional semiconductor device shown in FIG. 2 in which the silicon nitride film 15 is not formed below the PSG film 11. Shown below. In FIG. 3, numeral 30 represents the erase characteristic of the semiconductor device of the conventional structure, and numeral 31 represents the erase characteristic of the semiconductor device of this embodiment. In this example, the thickness of silicon nitride is 40 nm as described above. As is clear from FIG. 3, in both cases, the threshold voltage completely returned to the value before writing within several minutes after irradiation with ultraviolet rays, indicating that sufficient erasure was achieved. Since the time required for erasing an EPROM by ultraviolet irradiation is normally standardized by the user to about 30 minutes, the EPROM of this embodiment poses no problem in actual use.

Note that instead of the above-mentioned PSG film 11, a BPSG film (for example, a B concentration of 1 to 2 wt.
%, P concentration 3 to 6 wt%) without any problem. Further, in this embodiment, the planarization was performed by pyroflow, but the planarization may be performed by performing normal reflow at a high temperature.

Furthermore, in this embodiment, a polycrystalline silicon film is used for the control gate 7 of the semiconductor device serving as an EPROM and the usual transistors around it, but a polycrystalline silicon film is used, which has been widely used in recent years to increase speed. Melting point metals may also be used. Furthermore, the gate structure of the semiconductor element may be any one of a normal structure, a DDD structure, an LDD structure, and the like. Further, the silicon nitride film may be formed below the surface protection film 14 as long as the base is made of a material that can withstand the temperature at which the silicon nitride film is formed.

[0022]

As explained above, according to the semiconductor device according to the invention of claim 1, a 20nm semiconductor device formed by the CVD method on an element whose information can be erased by ultraviolet irradiation.
EPRO
Abnormal operation of elements such as M can be prevented from occurring. Further, since the thickness of the silicon nitride film is 50 nm or less, the absorption loss of ultraviolet rays is small, and information can be erased within a practical level of ultraviolet irradiation time.

Further, according to the semiconductor manufacturing method according to the second aspect of the invention, a dense silicon nitride film is formed with a thickness of 20 nm or more by the CVD method, and this silicon nitride film has sufficient resistance to moisture and oxygen. To act as a barrier,
After forming a doped silicon oxide film on this silicon nitride film, high-temperature reflow such as pyroflow can be performed. As a result, sufficient planarization can be achieved even if the concentration of impurities such as phosphorus and boron contained in the silicon oxide film is low, and the problem of corrosion of the aluminum wiring does not occur.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a sectional view of a main part of a conventional semiconductor device.

FIG. 3 shows the difference between a semiconductor device of the present invention and a conventional semiconductor device.
This is a comparison of erasing characteristics by ultraviolet rays.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Transistor formation area 3 Element isolation region 4 First gate insulating film 5 Floating gate 6 Second gate insulating film 7 Control gate 8 Source area 9 Drain region 10 Thermal oxide film 11 PSG film (silicon oxide film) 12 Contact hole 13 Aluminum wiring 14 Surface protective film 15 Silicon nitride film

Claims (2)

[Claims] 1. An element formed on a semiconductor substrate and capable of erasing information by ultraviolet irradiation; a silicon nitride film with a thickness of 20 nm to 50 nm formed on the gate of the element by chemical vapor deposition; 1. A semiconductor device comprising: a doped silicon oxide film formed on a silicon nitride film and having a planarized surface. 2. Forming on a semiconductor substrate an element whose information can be erased by ultraviolet irradiation, and forming a silicon nitride film with a thickness of 20 nm to 50 nm on the gate of the element by chemical vapor deposition. a step of forming a doped silicon oxide film on the silicon nitride film;
A method for manufacturing a semiconductor device, comprising the step of planarizing the surface of the silicon oxide film by performing reflow at a high temperature.