JPH04322426A - Dry etching method - Google Patents

Abstract

PURPOSE:To improve base selectivity at the time of overetching in the case of dry etching a silicon-based material layer without using fluorocarbon based gas. CONSTITUTION:For example, in the case of forming a gate electrode of a MOS- FET, S2F2, S2Cl2, etc., is used to (just) etch a polycrystalline silicon layer in thickness corresponding to that of the layer, and a gate electrode having an anisotropic shape is formed at a high speed by contribution of F*, Cl*, etc., and sidewall protecting operation of S(sulfur). Thereafter, in order to remove the residual polycrystalline silicon layer, bromine-based gas such as HBr, S2Br2, etc., is used to overetch it. As apparent from the fact that magnitude relationship of interatomic bonding energy is Si-O>Si-Br, the Br* does not spontaneously etch SiO2, and hence high selection ratio to a ate oxide film is performed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a dry etching method applied in the field of manufacturing semiconductor devices, etc., and in particular, when etching a silicon-based material layer without using a fluorocarbon-based gas, selection of a substrate for over-etching. Concerning how to improve sex.

0002

[Prior Art] As semiconductor devices become more highly integrated and performant as seen in VLSI, ULSI, etc. in recent years, etching of silicon-based material layers also requires high anisotropy, high speed, and high performance. There is a strong desire for technology that can achieve the various requirements of selectivity, low damage, and low contamination without sacrificing any of them.

Conventionally, fluorocarbon-based gases such as fluorocarbon 113 (C2 Cl3 F3) have been widely used as etching gases for etching silicon-based materials. Since fluorocarbon-based gas has F and Cl as constituent elements in one molecule, it is possible to perform etching by both radical reactions and ion-assisted reactions, and while protecting the side walls with carbon-based polymers deposited from the gas phase. Anisotropic processing can be achieved. However, as is well known, fluorocarbon gases have been pointed out to be the cause of the destruction of the earth's ozone layer, and their production and use are likely to be prohibited in the near future. Therefore, in the field of dry etching, there is an urgent need to find a substitute for fluorocarbon-based gas and to establish an effective method for using it. Furthermore, if the design rules for semiconductor devices become even smaller in the future, carbon-based polymers deposited in the gas phase may become a source of particle contamination, and in this sense, measures to eliminate fluorocarbons are desired.

[0004] Low-temperature etching is a promising technique for eliminating fluorocarbons. By keeping the temperature of the substrate (wafer) to be etched below 0°C, the etching rate in the depth direction is maintained at a practical level due to the ion assist effect, while radical reactions on the sidewalls of the pattern are frozen or suppressed. This technique attempts to prevent shape abnormalities such as undercuts. For example, the 35th
On page 495 of the lecture proceedings of the Annual Conference on Applied Physics (Spring 1988 Annual Conference), title number 28a-G-2,
An example has been reported in which silicon trench etching and n+ type polycrystalline silicon layer etching were performed using SF6 gas after cooling the wafer to -130°C.

However, if one attempts to achieve high anisotropy in low-temperature etching by relying solely on freezing or suppressing radical reactions, a corresponding level of low-temperature cooling is required, which may greatly reduce economic efficiency and throughput. Therefore, a more practical approach would be to combine suppression of radical reactions at low temperatures and sidewall protection, and perform etching in a temperature range closer to room temperature.

[0006] The applicant has developed this side wall protection using sulfur (S).
) have proposed a number of techniques to date. This S deposition is caused by the halogen (X) in one molecule.
This is made possible by using an etching gas mainly composed of sulfur halide, which has a relatively small ratio of the number of atoms to the number of S atoms, that is, the X/S ratio. For example,
The specification of No. 198045 describes S2 F2 , SF2 , SF4 , S2 F10 as such halogenated sulfur.
is disclosed. These sulfur fluorides are SF6, which is also the most well-known sulfur fluoride.
In contrast, S can be generated in the gas phase by discharge dissociation. If the substrate is cooled to a low temperature, this S will be deposited on the surface of the substrate and exert a sidewall protection effect. Moreover, since the deposited S can be easily sublimed and removed by heating the substrate after etching, there is no possibility of causing particle contamination. The applicant of this application has proposed that F* from these sulfur fluorides
Focusing on the fact that the amount of (fluorine radicals) produced is smaller than that of SF6, and an ion-assisted reaction by SFx + can be expected, we applied this to the etching of silicon oxide-based material layers and achieved high selectivity to the silicon substrate. did.

[0007] Thus, the first compound proposed as a sulfur halide was sulfur fluoride, which has a relatively low F/S ratio, and was intended for etching silicon oxide-based material layers. The applicant has since proposed various techniques for applying halogenated sulfur to etching silicon-based material layers. For example, patent application No. 2-199249
In the specification, sulfur chloride such as S2 Cl2 or S2 B is etched while the substrate to be etched is cooled to below 0°C.
Discloses a technique for low-temperature etching of silicon-based materials using a gas containing sulfur bromide, such as R2. this is,
By using a gas that cannot generate highly reactive F*, the influence of radicals is reduced and high anisotropy is attempted to be achieved more advantageously.

[0008]

[Problems to be Solved by the Invention] Among various processes for etching silicon-based material layers, gate electrode processing, which involves etching polycrystalline silicon, high melting point metal silicide, polycide, etc., requires particularly high precision. It's a process. In the manufacturing process of MOS-FET, in which the source/drain regions are formed in a self-aligned manner, the dimensional accuracy and cross-sectional shape of the gate electrode are important, such as the channel length, the dimensional accuracy of the sidewalls to realize the LDD structure, and the source/drain region. This is because it directly affects the formation region of the drain region, etc. Another important reason is that gate insulating films, which have become thinner and thinner in recent years, need to be processed with extremely high selectivity to the underlying layer.

However, in general, in the dry etching process, it is essential to perform slight overetching in consideration of the uniformity of the process within the wafer surface, and it is necessary to maintain high substrate selectivity and high anisotropy throughout the process. It's actually not easy to maintain. For example, among the above-mentioned sulfur halides, S2 F2 is expected to have a high etching rate and is relatively easy to handle, so it would be desirable to use it for gate electrode processing. However, in systems where F*, which is highly reactive, is the main etching species, silicon oxide (SiO2
), it is difficult to maintain high selectivity even during over-etching. this is,
The value of interatomic bond energy is 111k for Si-O bond.
cal/mol, whereas for Si-F bond it is 13
This is supported by the fact that it is as large as 2kcal/mol. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a dry etching method that can prevent deterioration of the anisotropic shape and decrease of selectivity to the substrate even during over-etching, and can take advantage of the characteristics of sulfur halide.

0010

[Means for Solving the Problems] The dry etching method of the present invention is proposed to achieve the above-mentioned objects, and includes controlling the temperature of the substrate to be etched to below room temperature,
S2 F2 , SF2 , SF4 , S2 F10,S
3. A step of etching the silicon-based material layer using an etching gas containing at least one compound selected from Cl2, S2 Cl2, and SCl2, and over-etching using an etching gas mainly composed of bromine-based gas. It is characterized by having a step of performing.

[0011]

[Operation] In the present invention, most of the silicon-based material layer is etched using sulfur fluoride or sulfur chloride (hereinafter, the etching process up to this point is referred to as just etching), and the subsequent over-etching is performed using bromine-based gas. This is done using an etching gas mainly composed of .

The sulfur fluoride or sulfur chloride used in the steps up to just etching is F/
It is a compound with a low S ratio or Cl/S ratio. When sulfur fluoride is used, F*, which has a small atomic radius and is extremely reactive, is produced, and this serves as the main etching species, so that the etching reaction progresses at high speed. On the other hand, when sulfur chloride is used, the main etching species is Cl*, so the etching rate is slightly lower than in the case of F*, but it is more advantageous from the viewpoint of selectivity to SiO2. The interatomic bond energy of Si-Cl bond is 96 kcal/mol, and Si-
This is clear from the fact that it is smaller than that of O bond. Either compound can generate F* or Cl*, which is an etchant for the silicon-based material layer, by discharge dissociation, and simultaneously generate S in the plasma. The generated S easily precipitates onto the surface of the substrate to be etched because the temperature of the substrate is maintained at a temperature below room temperature. Here, the S deposited on the ion incident surface is immediately removed by sputtering, but S continues to accumulate on the sidewall portions of the pattern where few ions are incident, and this serves as a sidewall protective film. Moreover, since radical reactions are suppressed to some extent by controlling the temperature of the substrate to be etched, high anisotropy is ensured. Moreover, the deposited S can be easily sublimated and removed by heating the substrate to be etched to a temperature higher than room temperature after etching is completed, so that no particle contamination is caused in the etching system.

[0013] A bromine gas is used for the subsequent over-etching. Since the interatomic bond energy of the Si--Br bond is 88 kcal/mol, which is smaller than that of the Si--O bond, Br* does not spontaneously etch SiO2. This is SiO2 in the present invention.
This is the reason why high selectivity can be achieved with respect to the gate insulating film.

[0014] Regarding the technique of using bromine-based gas during over-etching, the present inventor previously disclosed the patent application No.
265236, specifically, after etching the polycide film to a just-etched state using an SF6/HBr mixed gas system, etching the substrate to be etched to a temperature below 0°C using a single HBr gas system. Over-etching is being performed. The present invention follows the idea of this prior application with respect to over-etching, but is even more advantageous than the above-mentioned prior application with respect to the steps up to just etching. That is, in the above-mentioned SF6/HBr mixed gas system, S deposition does not occur, and sidewall protection is performed by SiBrx, which is a reaction product of resist mask fragments and Br or an etching reaction product. On the other hand, in the present invention, S generated from the gas phase protects the sidewalls, making it possible to reduce particle contamination and improve resist selectivity.

[0015]

[Examples] Specific examples of the present invention will be described below.

Example 1 In this example, the present invention is applied to gate processing, and S2 F2
This is an example in which a polycrystalline silicon layer is etched to a just-etched state using HBr, and then over-etched using HBr.

First, SiO2 is deposited on a single crystal silicon substrate.
A wafer was prepared in which an n+ type polycrystalline silicon layer was formed through a gate oxide film consisting of a gate oxide film, and a resist mask patterned into a predetermined shape was further formed. This wafer is set on a wafer mounting electrode of a magnetic field microwave plasma etching system, and ethanol refrigerant is supplied and circulated from a cooling system such as a chiller to cooling piping built into the wafer mounting electrode. was cooled to about -60°C. In this state, S2 F2 flow rate 20SCCM, gas pressure 1.3 Pa (10 mTorr)
, microwave power 850W, RF bias power 1
Etching the above polycrystalline silicon layer by approximately the layer thickness under the condition of 0W (2MHz) (just etching)
did. In this process, F* generated from S2 F2
Etching progressed by a mechanism in which a radical reaction was assisted by ions such as S+ and SFx+, while sidewall protection was performed by S, which was also generated from S2F2 and deposited on the sidewalls of the pattern. As a result, a gate electrode having a good anisotropic shape was formed.

However, in the process up to the above-mentioned just etching, F* is the main etching species, so the selectivity to the gate oxide film is about 5 to 6 at most. Therefore, if over-etching is performed under these conditions, there is a high possibility that the gate oxide film will be removed in the region where the gate oxide film is exposed relatively quickly. Therefore, over-etching was performed by switching the etching gas to HBr. The conditions at this time include, for example, an HBr flow rate of 50S.
CCM, gas pressure 1.3 Pa (10 mTorr), microwave power 850 W, RF bias power 5 W (2M
Hz), and the wafer temperature was -60°C. Under these conditions, the selectivity to the gate oxide film was approximately 50, and local removal of the gate oxide film could be prevented. This is H
This is because Br* generated by dissociation from Br does not spontaneously etch the gate oxide film, and furthermore, the RF bias power is reduced.

In this example, deposition of S cannot be expected during over-etching, but carbon-based compounds such as CBrx, which is a reaction product between Br and the resist mask, or SiBrx, which is an etching reaction product, are deposited in the pattern. They were deposited on the side walls and exerted the effect of protecting the side walls. Therefore, the anisotropic shape of the gate electrode was well maintained even during over-etching. Since the amount of these deposits is relatively small, they do not cause particle contamination or the like. Furthermore, the S deposits that served as sidewall protection during the process up to just etching were easily sublimated and removed by heating the wafer to about 90° C. after etching. Therefore, no particle contamination occurred.

Example 2 In this example, the present invention is applied to gate processing, and S2 F2
This is an example in which a polycrystalline silicon layer is etched to a just-etched state using S2 Br2 and then over-etched using S2 Br2.

First, as in Example 1 described above, the polycrystalline silicon layer was etched to a just-etched state, and then the etching gas was switched to S2 Br2 to perform over-etching. The over-etching conditions are, for example, S2 Br2 flow rate 20SCCM, gas pressure 1.3 Pa (10 mTorr), and microwave power 8.
50 W, RF bias power 5 W (2 MHz), and wafer temperature -60°C. Generally, during over-etching, radicals tend to be relatively excessive because the material layer to be etched is reduced. Excessive radicals cause migration on the wafer surface, which attacks the pattern sidewalls and causes shape abnormalities such as undercuts or reverse taper shapes. However, in this example, unlike in Example 1, S2 is applied even during over-etching.
Sidewall protection is performed by S generated from Br2. Therefore, in this example, not only high selectivity to the gate oxide film was achieved as in Example 1, but also more reliable anisotropic processing was also possible.

It should be noted that the present invention is not limited to the above-described embodiments; for example, various additive gases may be mixed with the etching gas. For example, when N2 is added, side wall protection can be expected to be strengthened by reaction products, and H* and/or silicon-based active species can be added to the etching system, such as H2, H2S, and silane-based gases. By adding gas that can be supplied, excess halogen and
It can trap radicals and enhance the S deposition effect. Furthermore, a rare gas such as He or Ar may be added for the purpose of obtaining a sputtering effect, a cooling effect, and a dilution effect.

[0023]Although the above embodiment describes the case where S2F2 is used as the etching gas, even when other sulfur fluoride and sulfur chloride proposed in the present invention are used, etching can be achieved by the same mechanism. Seed generation and sidewall protection by S take place. However, for compounds that are liquid at room temperature, it is necessary to vaporize them by bubbling with an inert gas before introducing them into the etching reaction system. In particular, when using sulfur chloride, F
* Since extremely reactive etching species such as * are not generated, the etching rate tends to decrease slightly, but it is advantageous from the viewpoint of achieving anisotropy.

[0024]

Effects of the Invention As is clear from the above description, the dry etching method of the present invention allows silicon-based material layers to be etched with high anisotropy, high speed, high selectivity, and without using fluorocarbon gas. Etching can be performed with low contamination. Moreover, since an etching gas mainly composed of bromine gas is used during over-etching,
It becomes possible to improve base selectivity. Therefore, the present invention is designed based on fine design rules, and is suitable for manufacturing semiconductor devices having high integration and high performance, and is also extremely excellent as a measure against CFCs.

Claims (1)

[Claims] [Claim 1] The temperature of the substrate to be etched is controlled below room temperature, and S2 F2 , SF2 , SF4 , S2 F
10, Etching containing at least one compound selected from S3 Cl2 , S2 Cl2 , SCl2
A dry etching method comprising the steps of etching a silicon-based material layer using gas and over-etching using an etching gas mainly containing bromine-based gas.