JPH04321270A - Integrated circuit - Google Patents

Abstract

PURPOSE:To provide the title integrated circuit avoiding the fluctuation in characteristics or erroneous actuation thereof with no parasitic current running therein. CONSTITUTION:The voltage V1 of an outer power supply is impressed as the voltage V2 of an input terminal of the CMOS integrated circuit 10 through an outer resistor R3. The gate potential V3 of a transistor T2 is specified by another transistor T1 and a resistor R1. At this time, when said voltage V1 is boosted, both transistors T2, T3 are turned on so that the current I may start running into the input terminal of the CMOS integrated circuit 10 through the outer resistor R3. Accordingly, said voltage V2 is made lower than said voltage V1 by the voltage (1XR3). Through these procedures, said voltage V2 will never exceed the power supply voltage Vcc so that the CMOS integrated circuit 10 may avoid the fluctuation in characteristics or erroneous actuation thereof due to the parasitic current.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit which prevents an input voltage from exceeding a power supply voltage and prevents fluctuations in characteristics and malfunctions.

0002

2. Description of the Related Art An integrated circuit is an assembly of circuit sections having multiple functions. In this case, the voltage level of the input signal may differ in each circuit section. For example, switch S
A circuit for detecting on/off of W11 is shown in FIG. Here, the voltage V11 of the external power supply is, for example, a battery voltage of 12V for an automobile. Moreover, the voltage V21 is
This is the input voltage to the integrated circuit 100 on the right side of the broken line in the figure, and the voltage VCC is the power supply voltage (=5V) of the integrated circuit 100. FIG. 8 shows the structure of integrated circuit 100 in FIG. The diode D11 in FIG. 7 has an N substrate (N
It is formed by a P+ layer (P-type diffusion layer) 12 provided on the N-type silicon substrate 11 and serving as an input terminal. A first circuit section, for example, an inverter 13, is connected to this P+ layer 12. Further, a P+ layer 14, which serves as another input terminal, is provided on the N substrate 11 adjacent to the P+ layer 12. This P+ layer 1
4 is connected to an inverting input terminal of a comparator 15, which is a second circuit section. A comparison voltage Vref expressed by the following formula, obtained by dividing the power supply voltage VCC by resistors R21 and R22, is input to the inverting input terminal of the comparator 15 via the P+ layer 14. Vref=VCC×R21/(R21+R22) Further, the output of an amplifier (not shown) is input to the non-inverting input terminal of the comparator 15.

0003

[Problem to be Solved by the Invention] In this case, the N substrate 11
A parasitic transistor 16 having a PNP structure, which is an unintended transistor, is formed from the P+ layer 12 provided in the P+ layer 12 and the adjacent P+ layer 14. Then, when the voltage V11 becomes higher than the power supply voltage VCC, the emitter-base of the parasitic transistor 16 is forward biased, and the P+ layer 1
2 to the N substrate 11 (the diode D11 described above).
D11 is played. As a result, the parasitic transistor 1
6 becomes conductive, P+ layer 12 and P+ layer 14 become conductive, and external power supply of voltage V11→external resistor R11→P+
An unintended parasitic current IP flows through the paths of layer 12→N substrate 11→P+ layer 14→resistance R21. This parasitic current IP changes the comparison voltage Vref of the comparator 15 to a voltage (IP×R21×R22/(R2
1+R22)). In other words, the threshold voltage of the comparator 15 increases,
There is a problem in that the characteristics of the integrated circuit 100 connected to the comparator 15 at the subsequent stage fluctuate or malfunction.

The present invention has been made to solve the above-mentioned problems, and its purpose is to prevent the interference in the circuit section without causing the above-mentioned parasitic current to flow, thereby reducing the variation in characteristics. Another object of the present invention is to provide an integrated circuit that can prevent malfunctions.

[0005]

[Means for Solving the Problems] The structure of the invention for solving the above problems includes a semiconductor substrate and a first conductive region connected to the semiconductor substrate and having one conductive region in common.
and a second PN junction diode, a first circuit section in which the first PN junction diode is inserted in parallel between the input line and the power supply, and the second PN junction diode is inserted between the input line and the power source. The second one inserted in parallel with the power supply
In the integrated circuit, a voltage higher than a power supply voltage supplied to the second circuit section is introduced into the first circuit section via an external resistor, the first circuit section comprising: The device is characterized in that it includes a circuit that bypasses an input current so that the input voltage of the unit does not exceed the power supply voltage.

[0006]

[Operation] The integrated circuit includes a circuit for bypassing the input current so that the input voltage of the first circuit section does not exceed the power supply voltage. Here, when the input voltage introduced into the first circuit section via an external resistor becomes higher than the power supply voltage, the circuit provided in the first circuit section in the integrated circuit becomes conductive. . Then, a current flows through the external resistor through the circuit, thereby reducing the voltage introduced into the first circuit section. Thereby, the input voltage to the first circuit section does not exceed the power supply voltage.

[0007]

EXAMPLES The present invention will be explained below based on specific examples. FIG. 1 shows a CMOS (CMOS) integrated circuit according to the present invention.
Complementary Metal Oxide
1 is a circuit diagram showing a Semiconductor (complementary MOS) integrated circuit 10. FIG. T1 and T2 are p-channel MOS field effect transistors (p-ch MOS
T3 is an n-channel MOS field effect transistor (n-ch MOSFET). R1 and R2 are resistors provided within the CMOS integrated circuit 10, and R3 is an external resistor provided outside the CMOS integrated circuit 10. Hereinafter, T1, T2, and T3 are simply referred to as transistors. The source S1 side of the transistor T1 is connected to the power supply voltage VCC, and the gate G1 side is connected to the gate G2 side of the transistor T2. The gate G1 side of the transistor T1 is connected to the drain D1 side, and is grounded via a resistor R1. Further, the substrate B1 side of the transistor T1 is connected to the power supply voltage VCC. An external resistor R3 is connected to the source S2 side of the transistor T2.
A voltage V1 from an external power supply is supplied through the terminal. The drain D2 side of the transistor T2 is connected to the gate G3 side of the transistor T3 and is grounded via a resistor R2. Further, the substrate B2 side of the transistor T2 is connected to the power supply voltage VCC. The drain D3 side of the transistor T3 is the source S2 of the transistor T2.
It is connected to the inverter circuit (input circuit), which is a first circuit (not shown) at the subsequent stage. Then, the source S3 side of the transistor T3 and the substrate B3
The side is grounded.

[0008] Next, its operation will be explained. When the power supply voltage VCC is supplied to the source S1 side of the transistor T1, the substrate B1 side has the same potential as the power supply voltage VCC,
The voltage on the gate G1 side of the transistor T1 is the power supply voltage VC.
Since the voltage is lower than C, the voltage between the source S1 and the gate G1 is forward biased, the transistor T1 is turned on, and a current begins to flow between the source S1 and the drain D1. Then,
The potential V3 on the drain D1 side of the transistor T1 begins to rise due to the resistor R1. If the power supply voltage VCC is 5V, this potential V3 becomes balanced and constant at 3.5V by appropriately setting the value of the resistor R1. That is, the potential on the gate G2 side of the transistor T2 is also constant at 3.5V.

Here, when the voltage V1 of the external power supply is lower than a voltage Va (described later) which is lower than the power supply voltage VCC, both transistors T2 and T3 are off, and the voltage V1 of the external power supply is directly applied to the CMOS integrated circuit 10. The voltage at the input terminal becomes V2 (V1=V2). Next, the voltage V1 becomes high, and the voltage between the source S2 and the gate G2 of the transistor T2 becomes the threshold voltage VTP (= 1.0V).
When the voltage Va (=4.5V) becomes higher or higher, the transistor T2 turns on. Then, the transistor T2 is turned on and the source S2-drain D
Current begins to flow between the two. Then, the potential V4 of the drain D2 of the transistor T2 begins to rise due to the resistor R2. And source S3-gate G of transistor T3
The potential V4, which is the voltage between 3 and 3, is the threshold voltage VTP (
= 1.0V), the transistor T3 also turns on. In this way, when transistors T2 and T3 are both turned on, current I begins to flow into the input terminal of CMOS integrated circuit 10 via external resistor R3. Due to this current I, the voltage V2 at the input terminal of the CMOS integrated circuit 10 becomes lower than the voltage V1 by a voltage (I×R3). If the value of the resistor R2 is equal to the value of the resistor R1, and if the voltage V2 at the input terminal becomes equal to the power supply voltage VCC, the potential V4 will be 3.5V, so the bias between the gate G3 and the source S3 of the transistor T3 will be becomes extremely deep, and transistor T3 is completely turned on. Therefore, the voltage V2 at the input terminal does not rise above the power supply voltage VCC. Therefore, when the voltage V2 at the input terminal of the CMOS integrated circuit 10 exceeds the voltage Va, it approaches the power supply voltage VCC. Note that the voltage V1 is, for example, a battery voltage of 12V in an automobile, and its maximum voltage V1max=16V.

As a design example, transistors T1, T2,
The value of W/L (gate width/gate length) of T3 is 2 each.
5, 25, and 106, and the resistance values of resistors R1, R2, and R3 are 100KΩ, 100KΩ, and 10KΩ, respectively. Then, as shown in FIG. 2, which shows the relationship between the voltage V1 and the voltage V2, in the past, the voltage V1 was equal to the power supply voltage VCC.
, the voltage V2 also exceeds the power supply voltage VCC, but in the CMOS integrated circuit 10 of the present invention,
Even if voltage V1 exceeds power supply voltage VCC, voltage V2 does not exceed power supply voltage VCC. That is, the commercial of the present invention
In the OS integrated circuit 10, since the above-mentioned parasitic current IP does not flow, fluctuations in characteristics or malfunctions are prevented.

Next, as another embodiment, a CMOS integrated circuit 20 has a circuit configuration as shown in FIG. That is, C
When the number of inputs to the MOS integrated circuit 20 is two or more,
A circuit (the circuit shown within the dashed line in FIG. 3) consisting of transistors T2', T3' and resistors R2', R3' is added for each input channel. Note that the transistor T1 and the resistor R1 can be made common to each channel. The operation of each channel of the CMOS integrated circuit 20 of this embodiment is the same as that of the above-mentioned embodiment, and the explanation thereof will be omitted.

Next, as another embodiment, a CMOS integrated circuit 30 has a circuit configuration as shown in FIG. That is, the resistor R1 and transistor T1 in the CMOS integrated circuit 10 of FIG. 1 are replaced with resistors RA and RB. Then, the gate potential V3 of the transistor T2 is calculated using the following equation, and its value becomes constant. V3=VCC×RA/(RA+RB) As a design example, resistors RA and RB are each 70
KΩ, 30KΩ. Here, power supply voltage VCC=5
V, and threshold voltage VTP of transistor T2 = 1
．． Set it to 0V. Then, the gate potential V3 of the transistor T2 becomes 3.5V from the above equation, and the gate potential V3 of the transistor T2 becomes 3.5V.
The voltage Va at which the switch turns on and current begins to flow is 4.
It becomes 5V. The operation of the CMOS integrated circuit 30 of this embodiment is the same as that of the above-mentioned embodiment, and its explanation will be omitted.

Next, as another embodiment, a CMOS integrated circuit 40 has a circuit configuration as shown in FIG. That is, the circuit configuration is such that the resistor R2 and transistor T3 are removed from the CMOS integrated circuit 10 of FIG. The transistor T2 begins to conduct when the voltage V2 at the input terminal is 4.5V, and as the voltage V2 increases, the bias between the source and gate becomes deeper and the voltage drop between the source and drain gradually decreases. Therefore, the rise in voltage V2 is suppressed. Figure 6 shows the voltage V2 versus voltage V1 in the circuit of Figure 5.
FIG. In this characteristic diagram, the voltage V
The slope of the curve after 1 exceeds the power supply voltage VCC is shown in Figure 1.
This shows that the slope is larger than the slope in the circuit. still,
In order to prevent characteristic variations or malfunctions of the CMOS integrated circuit 40 of this embodiment, it is necessary to use the voltage V2 within a range that does not exceed the power supply voltage VCC after the voltage V1 exceeds the power supply voltage VCC. Then, since the range of voltage V1 in which V2≦VCC is narrow, the CMOS integrated circuit 4 of this embodiment
The uses of CMOS integrated circuit 10 of FIG. 1 will be more limited.

[0014]

[Effects of the Invention] The present invention includes a circuit that bypasses an input current so that the input voltage of the first circuit section in an integrated circuit does not exceed the power supply voltage, and the circuit bypasses the input current to the first circuit section through an external resistor. When the input voltage introduced by the input voltage becomes higher than the power supply voltage, a circuit provided in the first circuit section that bypasses the input current becomes conductive. Then, a current flows through the circuit to the external resistor, thereby lowering the input voltage, and the input voltage of the first circuit does not exceed the power supply voltage. Therefore, in the integrated circuit of the present invention, no parasitic current flows, making it possible to prevent variations in characteristics and malfunctions.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a CMOS integrated circuit according to a specific embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the relationship between the input voltage to the integrated circuit and the voltage of the external power supply according to the same embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of a CMOS integrated circuit according to the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of a CMOS integrated circuit according to the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of a CMOS integrated circuit according to the present invention.

6 is a characteristic diagram showing the relationship between the voltage of the external power supply and the input voltage to the integrated circuit according to the embodiment of FIG. 5 in comparison with the embodiment of FIG. 1;

[Figure 7] Conventional CMO that detects on/off of a switch
FIG. 2 is a circuit diagram showing an S integrated circuit.

FIG. 8 is a diagram showing the structure of the CMOS integrated circuit according to FIG. 7;

[Explanation of symbols]

10-CMOS integrated circuit VCC-power supply voltage V1
- External power supply voltage V2 - Input voltage T1, T2 -
P channel field effect transistor (transistor) T3-n channel field effect transistor (transistor)

Claims (1)

[Claims] Claim 1: A semiconductor substrate;
and a second PN junction diode, a first circuit section in which the first PN junction diode is inserted in parallel between the input line and the power supply, and the second PN junction diode is inserted between the input line and the power source. The second one inserted in parallel with the power supply
In an integrated circuit in which a voltage higher than a power supply voltage is introduced into the first circuit part via an external resistor, the input voltage of the first circuit part exceeds the power supply voltage. What is claimed is: 1. An integrated circuit characterized by comprising a circuit for bypassing input current to prevent input current from flowing.