JPH04321146A - Storage protection system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage protection system for protecting storage areas.

0002

2. Description of the Related Art Conventionally, for an area that can be used by a program, for example, the user area shown in FIG. When this happens, an access permission signal is sent to access the area in order to protect the area.

0003

[Problem to be Solved by the Invention] Therefore, when trying to expand the user area that can be used by a program, as shown in the user area (b) of FIG. area of use must be moved,
The problem was that the address simply could not be expanded.

[0004] The present invention provides at least two pairs of address range specification registers, sets upper and lower limit addresses for the basic area in one pair, and sets upper and lower limit addresses for the extended area in the other pair to protect memory. The purpose is to easily protect the memory of the extended area without changing the address settings of the basic area.

[0005]

[Means for Solving the Problems] Means for solving the problems will be explained with reference to FIG. In FIG. 1, address range designation registers 3 and 2 are registers for setting upper and lower limit addresses that can be used by programs within the basic area. Address range designation registers 5 and 4 are registers for setting upper and lower limit addresses that can be used by programs in the extended area and the like.

[0006]

[Operation] As shown in FIG. 1, the present invention sets the upper limit address and lower limit address within the basic area that the program intends to use in a pair of address range specification registers 3 and 2.
and an upper limit address and a lower limit address such as within the extended area are set in at least one pair of address range specification registers 5 and 4, and the access address is set in any pair of address range specification registers 3 and 2 or address range specification registers 5 and 4. When within range, an access permission signal is sent to allow access.

[0007] Therefore, at least two pairs of address range specification registers are provided, upper and lower limit addresses are set for use by programs in the basic area and extended area, and permission is granted when accessing within any of these ranges. By doing so, it becomes possible to easily protect the memory of the extended area without changing the address settings of the basic area.

[0008]

Embodiment Next, the structure and operation of an embodiment of the present invention will be explained in detail using FIGS. 1 to 3. In FIG. 1, an instruction execution unit 1 takes in and accesses instructions from a memory to be protected, which is not shown, and processes the instructions.

Address range specification registers 3 and 2 are registers for setting the upper and lower limit addresses of the user area that can be used by programs in the basic area (see FIG.
reference). Address range specification registers 5 and 4 are registers for setting the upper and lower limit addresses of the user area that can be used by programs in the extended area, etc. (Figure 2
reference).

The comparators 6 to 9 compare the addresses set in the address range specification registers 2 to 5 with the memory access address at which the instruction execution unit 1 attempts to access a memory not shown, and determine whether the address is large or small. This is to determine equality. The AND circuit 10 performs a logical product operation of the signals from the comparators 6 and 7, and when the memory access address is within the range of the upper and lower limit addresses set in the address range designation registers 3 and 2. It outputs 1.

The AND circuit 11 performs a logical product operation of the signals from the comparators 8 and 9, and is configured to perform an AND operation on the signals from the comparators 8 and 9, and is configured to perform a logical product operation when the memory access address is within the range between the upper and lower limit addresses set in the address range designation registers 5 and 4. It outputs 1 when . The OR circuit 12 is the AND circuit 10, 1
1, and the memory access address is the upper limit address of address range specification registers 3 and 2 or address range specification registers 5 and 4,
It outputs 1 (outputs a memory access permission signal) when it exists somewhere within the lower limit address range.

FIG. 2 shows an operational diagram of the present invention. Here, the upper limit address (upper limit 1) and lower limit address (lower limit 1) of the user area of the basic area are set in the address range setting register 3 and the address range setting register 2 in FIG. 1, respectively. Upper limit address of user area in extended area (upper limit 2
) and the lower limit address (lower limit 2) are set in the address range setting register 5 and the address range setting register 4 in FIG. 1, respectively.

Further, FIG. 2 shows a case where the program uses only the basic area during normal addressing. In this case, the upper limit address of the user area of the basic area (upper limit 1
) and the lower limit address (lower limit 1) are set in the address range designation registers 3 and 2 in FIG. 1, respectively. When extending an address, the program uses both the basic area and the extended area. In this case, set the upper limit address (upper limit 1) and lower limit address (lower limit 1) of the user area of the basic area in the address range specification registers 3 and 2 in Figure 1, respectively, and set the upper limit address (upper limit 1) of the user area of the extended area to 2) and the lower limit address (lower limit 2) are set in the address range designation registers 5 and 4 in FIG. 1, respectively.

Next, the operation of the configurations shown in FIGS. 1 and 2 will be explained in detail in accordance with the order shown in the flowchart shown in FIG. In FIG. 3, S1 sends out a memory access address. This sends out the address by which the instruction execution unit 1 in FIG. 1 accesses the basic area and extended area on the right side in FIG.

[0015] In S2, it is determined whether lower limit 1≦memory access address≦upper limit 1. This inputs the access memory address sent in S1 to the comparators 7 and 6, compares it with the upper limit 1 and lower limit 1 set in the address range specification registers 3 and 2, respectively, and determines whether the address exists within the range of both. or not(
It is determined whether the output of the AND circuit 10 in FIG. 1 is 1 or not. If YES, send an access permission signal in S3,
Memory access is executed in S4. On the other hand, in the case of NO, the process advances to S7.

In S5, it is determined whether lower limit 2≦memory access address≦upper limit 2. This inputs the access memory address sent in S1 to the comparators 9 and 8, compares it with the upper limit 2 and lower limit 2 set in the address range specification registers 5 and 4, respectively, and determines whether it exists within the range of both. or not(
It is determined whether the output of the AND circuit 11 in FIG. 1 is 1 or not. If YES, send an access permission signal in S6,
Memory access is executed in S4. On the other hand, in the case of NO, the process advances to S7.

In step S7, if both are outside the range, the access permission signal is suppressed, access is disabled, and the memory is protected. As described above, the address range specification register 3 sets the upper limit 1 and lower limit 1 of the user area of the basic area, and the upper limit 2 and lower limit 2 of the extended area user area, respectively;
By providing two pairs of address range specification registers 5 and 4 and comparing them with the memory access address to determine whether or not they are within the range, storage protection can be achieved for the extended area in the same way as for the basic area. It becomes possible.

In addition, in the case of the normal address shown on the left side of FIG. By setting the lower limit address (lower limit 1) of the user area of each area, even in the case of only the basic area, the circuit configuration shown in Figure 1 can be maintained and access to areas other than the user area of the basic area can be inhibited to protect the memory. becomes possible.

[0019]

[Effects of the Invention] As explained above, according to the present invention,
At least two pairs of address range specification registers are provided, upper and lower limit addresses are set for use by programs in the basic area and extended area, and accesses within either of these ranges are permitted. Therefore, it is possible to easily protect the memory of the extended area without changing the address settings of the basic area. Also,
By setting the upper and lower limit addresses of at least two pairs of address range specification registers to be the same,
Storage area protection can be achieved in the same way even in the case of only the basic area.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of the operation of the present invention.

FIG. 3 is a flowchart illustrating the operation of the present invention.

FIG. 4 is an explanatory diagram of the prior art.

[Explanation of symbols]

1: Instruction execution unit 2 to 5: Address range specification register 6 to 9: Comparator 10, 11: AND circuit 12: OR circuit

Claims (2)

[Claims] Claim 1: In a storage protection method that protects a storage area, a pair of address range specification registers (3) and (2) that set the upper and lower limit addresses that can be used by a program in the basic area, and a at least one pair of address range specification registers (5) for setting upper and lower limit addresses that can be used by the program;
(4), and when the access address is within the range of the above address range specification registers (3), (2) or any pair of the above address range specification registers (5), (4), an access permission signal is provided. A memory protection method characterized in that it is configured to be accessed by sending. 2. Set the same address as the upper limit address and lower limit address of the pair of address range specification registers (3), (2) and the at least one pair of address range specification registers (5), (4), respectively. 2. The storage protection system according to claim 1, wherein the storage protection system is configured to: