JPH04318707A - Synchronous type ecl-cmos converter - Google Patents

Abstract

PURPOSE: To improve the speed and the efficiency of the operation for the entire system by converting an emitter-coupled logic(ECL) level signal into a CMOS level signal through the adoption of a synchronous architecture. CONSTITUTION: In the case that a PMOS transistor(TR) is turned on and an ECL low-level signal is applied to an input terminal 2, the converter is transited to an active state. TRs 6, 8 act as a current source, and the TR 8 acts as a compensation device set under a high-speed process/mode skew condition. The TR 6 is saturated by the response of the ECL low level signal and a TR 10. Built-in compensation is provided to a TR group 15 in the manufacturing stage and shift-compensation is conducted by the TR 4 under a partial turn-on condition. An NMOS TR 18 turns on, in response to the ECL low level signal for driving a regenerative load 70 to act as a latch activation device. NMOS TRs 28, 30 respond to a clock signal to act as a reset circuit 31, that restores a node 3 to a stationary state and this circuit to a stationary state.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to emitter-coupled logic (E
CL) level signal to complementary metal oxide semiconductor (CMOS)
) Conversion circuits useful for converting to level signals.

0002

2. Description of the Related Art BiCMOS integrated circuits are semiconductor devices that combine bipolar technology and CMOS technology. Bi
CMOS integrated circuits are useful for providing both the desired switching speeds of bipolar devices and the desired area requirements of CMOS devices on a single chip. The resulting BiCMOS device has significantly less silicon area per unit current drive than an equivalent CMOS circuit. Therefore, one goal is to convert on-chip ECL level signals for use by CMOS logic circuits located on the chip.

Some BiCMOS integrated circuits communicate with the outside world at signal levels appropriate for bipolar logic circuits, while CMOS level signals are used within the device. A common bipolar logic used within BiCMOS devices is ECL, which has signals in the range of -0.9V to -1.7V. However, CMOS signals swing within a 5V range. Therefore, another goal is to convert the ECL signal to Bi
The goal is to convert these input signals to CMOS levels for introduction into a CMOS integrated circuit and use by the CMOS portion of the chip as soon as possible.

0004

SUMMARY OF THE INVENTION The present invention provides a decoder converter that converts ECL level signals to CMOS level signals and converts clock signals to active input domain latches in a synchronous architecture. The present invention is four to five times faster than currently known BiCMOS converters, improving overall system operating speed and efficiency compared to systems using conventional BiCMOS converters. .

According to one embodiment of the invention, the first PMOS
A gate of the transistor is connected to the input node to receive the ECL level signal. When the ECL signal is high, the converter circuit is in a quiescent (ie 0 input) state and the output of the circuit is a CMOS high level signal. When the ECL level signal goes low, the PMO
The S transistor turns on and activates the converter circuit. When the converter circuit is activated, one of the circuit nodes rises in potential from a quiescent level of ground, activating a pull-down transistor driving a capacitive load at the output terminal to a CMOS level.

The circuit is reset to the quiescent state by the input of two clock signals which activate the two NMOS transistors and return the circuit node to the quiescent state of ground. This circuit node is maintained at ground during quiescent periods by a current maintenance circuit.

The converter of the present invention has leff =0.9μ
m technology has a propagation delay of only 250-300 ps and is significantly faster than other known converter circuits. In particular, because the converter of the present invention is synchronous semi-dynamic and not ratioed, it is inherently faster than standard asynchronous converters. Furthermore, the output nodes are very lightly loaded. DC affecting output
There is no current source.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of the present invention. The circuit has an input terminal 2 for receiving an ECL signal from an input pad (not shown). Input terminal 2 is PM
It is coupled to node 3 via the gate of OS transistor 4 . The source of PMOS transistor 4 is VCC
, ie, to 0V, and the drain of PMOS transistor 4 is connected to node 3. PMOS
Transistor 4 is turned on by a 1V signal and serves to transition the converter from a quiescent state to an active state when an ECL low level signal is applied to input terminal 2.

NMOS transistors 6 and 8 are coupled to node 3, and PMOS transistor 10 and NMOS transistor 12 are coupled via these transistors. The drains of both transistors 6 and 8 are coupled to node 3, and the sources of both transistors are coupled to Vee. Transistor 6 acts as a current source and maintains node 3 at Vee during the quiescent state of the device. Transistor 8 is also a current source and connects node 3 to a high-speed process/
Functions as a compensator to maintain mode skew conditions.

The gate of transistor 6 is coupled to node 9, and the drains of transistors 10 and 12 are also coupled to node 9. Transistor 10 has its source connected to VCC and its gate connected to Vbb.
is connected to. The gate of transistor 12 is connected to Vbg and also to the gate of transistor 8. The source of transistor 12 is connected to Vee. Transistors 10 and 12 maintain node 9 at a reference voltage of +1.25V with respect to Vee, which indicates that E
When node 3 rises to VCC in response to the CL low signal, transistor 6 is allowed to saturate. Furthermore, device 6-12 functions to overcome process skew by modifying the voltage on the gate of transistor 6. This group of transistors 15 thus provides built-in compensation for differences in circuit parameters introduced by the manufacturing process and compensates for shifts due to transistors 4 being in a partially on condition. Node 3 is further connected to the gate of NMOS transistor 18 . This transistor turns on when the voltage at node 3 rises to VCC in response to the ECL low signal. The source of this transistor is connected to Vee and its drain is coupled to output node 19. Therefore, when transistor 18 turns on, node 19 is pulled low as a result of the ECL low signal. In this way, a regenerative load, designated by reference numeral 70, is driven. Therefore,
One possible purpose for this circuit is as a latch activator. However, this circuit can be used to drive any small capacitive load.

NMOS transistors 28 and 30 receive a clock signal RS applied to the gate of transistor 28.
It functions as a reset circuit 31 that returns the circuit to its quiescent state by returning node 3 to its quiescent condition in response to a clock signal RSTB applied to TA and the gate of transistor 30. The source of each transistor is connected to Vee, and the drain of each transistor is coupled to node 3.

Sustainer or PMOS transistor 40 turns on when node 3 falls to its quiescent state and returns node 19 from a low state to VCC. The sustainer has its gate connected to Vee and its source connected to VCC. Its drain is connected to node 19. On the other hand, node 19 can be reset by a PMOS transistor in response to a reset signal (RSTC).

FIG. 2 shows a timing diagram useful in explaining the operation of the circuit of FIG. The converter circuit of FIG. 1 is configured such that the input signal LCLKE52 has an E
Activated by falling from CL high level to -1.6V. This drop in signal voltage causes transistor 4 to turn on and causes voltage 54 at node 3 to begin rising. Node 3 rises to VCC and CMOS
Once above the compatible level VTH (the NMOS threshold voltage), transistor 18 turns on and pulls voltage 56 at node 19 low. As a result, a CMOS level low signal of 0V is obtained as an output on node L.

At time t2, the low signal on LCLKE transitions to a high state and LCLKE returns to a high state ECL signal of -900 mV. This operation turns off transistor 4. Transistor 40 then operates to return the signal level at node 19 to VCC. Clock signals 58 and 60, namely RSTA and R
STB appears at the gates of transistors 28 and 30, respectively. These transistors return node 3 to its initial value Vee, ie, to its quiescent state. Transistor 18 is turned off by reset signals RSTA/RSTB. The converter of the invention remains stationary as long as there is no ECL low signal at input terminal 2. While in the quiescent state, the voltage at node 3 is maintained at Vee by current sources 6 and 8. Transistors 6 and 8 then act to maintain node 3 at a level below the threshold voltage of transistor 18, preventing that transistor from being activated prematurely. Since transistor 4 is partially on, E
In the CC high state, Vgs≈900mV.

Although specific embodiments of the present invention have been described above in detail, the present invention is not limited to these specific examples, and various modifications may be made without departing from the technical scope of the present invention. Of course, modifications are possible. For example, recovery circuit 31 could be constructed from a single transistor instead of two transistors as shown in the preferred embodiment described above. A single transistor recovery circuit eliminates the overlap capacitance between the two transistors and improves circuit speed. Furthermore,
It is possible for a derivative from node 19 to cause all nodes in the circuit to be reset. Additionally, LCLKE can be used to reset the circuit after some time delay. It is also possible to construct the device with transistors of opposite polarity to those shown in FIG. 1, in which case it is necessary to apply voltages of opposite polarity.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

2 is a timing diagram useful in explaining the operation of the circuit shown in FIG. 1;

[Explanation of symbols]

2 Input terminal 15 Group of transistors 19 Output node 31 Reset circuit 70 Regeneration load

Claims (8)

[Claims] 1. A BiCMOS converter circuit comprising an input terminal for receiving an input signal and an output terminal for outputting an output signal, a gate electrode connected to the input terminal and a first voltage reference connected to the input terminal. A first MOS transistor is provided having a connected source electrode and a drain electrode connected to the first node for maintaining the first node at a fixed potential when the input signal is not asserted. A first MOS circuit is provided connected to the first node, a gate connected to the first node, a source connected to a second voltage reference;
a second MOS transistor having a drain electrode coupled to the output terminal and raising the first node above the fixed potential when the input signal is asserted; a gate connected to the first reference voltage, a source connected to the first reference voltage, and a drain coupled to the output node, the potential of the output node increasing when the first node rises above the fixed potential. A third MOS transistor is provided for lowering the voltage from a potential equal to the first reference voltage to a level equal to the second reference voltage, and has an input terminal and an output terminal, and the output terminal is connected to the first circuit. a second MO connected to a node and whose input is connected to a control signal that triggers the resetting of the first node to the fixed potential;
A converter circuit characterized by being provided with an S circuit. 2. The converter circuit of claim 1, further comprising a third MOS circuit connected to the output terminal and providing a capacitive load. 3. The converter circuit of claim 2, wherein the third MOS circuit includes two cross-coupled MOS transistors. 4. In claim 1, the first MOS circuit includes a drain electrode connected to the first node, a gate electrode connected to the second node, and a source electrode connected to the second reference voltage. a fourth MOS transistor comprising a fourth MOS transistor; a fifth MOS transistor comprising a drain electrode connected to the first node; a source electrode connected to the second reference voltage; and a gate electrode connected to the gate electrode of the sixth MOS transistor. The sixth MOS transistor has a gate electrode connected to a third reference voltage, a source electrode connected to a second reference voltage, and a drain electrode connected to the second node, and the sixth MOS transistor has a gate electrode connected to a third reference voltage, a source electrode connected to a second reference voltage, and a drain electrode connected to the second node. a seventh MOS transistor having a source electrode connected to a fourth reference voltage, a gate electrode connected to a fourth reference voltage, and a drain electrode connected to the second node. 5. The second MOS circuit according to claim 1, wherein the second MOS circuit has a gate electrode coupled to the first control signal, a source electrode coupled to the second reference voltage, and a drain electrode coupled to the first node. A MOS transistor comprising:
a second MOS transistor having a gate electrode coupled to a second control signal, a source electrode coupled to the second reference voltage, and a drain electrode coupled to the first node. circuit. 6. In claim 1, the first MOS transistor is a PMOS transistor, and the second MOS transistor is a PMOS transistor.
A converter circuit characterized in that the OS transistor is an NMOS transistor, and the third MOS transistor is a PMOS transistor. 7. The converter circuit according to claim 4, wherein the fourth, fifth, and sixth transistors are NMOS transistors, and the seventh transistor is a PMOS transistor. 8. The converter circuit according to claim 5, wherein the eighth and ninth MOS transistors are NMOS transistors.