JPH04318654A - Redirection system for interruption to microprocessor - Google Patents

Abstract

PURPOSE: To manage a large-area interruption with high performance by a multiprocessor(MP) system which has a common storage device and is equipment with architecturally separated multiple buses. CONSTITUTION: This system is provided with a redirector 402 which uses software or hardware for distribution by a large-area interruption to all processors of the MP system, and can have architecturally separated multiple buses. When interruptions are redirected by using the software, a processor receives all the interruptions and redirects them to destination processors at omission time. When interruptions are redirected by using the hardware, individual redirectors of the hardware transmits all the interruptions to a specific processor according to a routine and a look-up table. Interruption inquiry which uses software and hardware interruption redirection wherein an interruption response is important for I/O cards 126 and 1228 can be incorporated.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates to computer systems and, more particularly, to a computer architecture for providing efficient control and delivery of interrupts directed to multiple processors on multiple buses.

0002

[Background Art and Problems to be Solved by the Invention] As a result of the rapid development of the personal computer (hereinafter referred to as PC) industry, high-end PC has migrated. These high-performance applications require high-speed interaction with a large number of peripheral devices;
It is necessary to perform real-time operations by manipulating huge amounts of data to be recognized by the user.

As a result, multiple processors are implemented within the PC architecture to maximize speed by assigning tasks and responsibilities that can be performed in parallel. In other words, independent processors of a multi-processor (hereinafter referred to as MP) system execute instructions simultaneously via multiple line instructions configured to process transactions simultaneously.

As more processors are added to an MP system, interrupt delivery and control becomes more complex and becomes an unbearable burden on the MP system. Interrupts are signals that cause the central processing unit (CPU) to automatically and immediately execute certain required routines within a computer system.

[0005] Upon receiving an interrupt, the CPU follows an interrupt sequence. During an interrupt sequence, the CPU first completes the currently executing instruction. Next, the CPU
All register values (e.g., instruction pointer (IP), instruction segment (CS)) needed to move to the next instruction, either on the stack inside main memory or in special-purpose registers on the CPU or elsewhere. , processor state word (PSW), etc.). The interrupt routine then begins. After the interrupt is executed, C
The PU returns to the program it was originally executing with an instruction at the end of an interrupt routine that puts register values back into the CPU from the stack or special purpose registers.

In MP systems, interrupts often originate from several different places and are therefore given special names. Those with interrupts are
This is an "internal" interrupt. Internal interrupts are initiated by CPU status or instructions. For example, a typical internal interrupt is one that occurs on division by zero.

Other interrupts are "external" interrupts. External interrupts are caused by signals sent to the CPU from somewhere within the computer system. An example of an external interrupt is input/output (hereinafter referred to as
Some are caused by the needs of the device (referred to as I/O).

Furthermore, external interrupts are sometimes classified into two types in MP systems with complex interrupt networks: (1) "local" interrupts, and (2) "global" interrupts. be. A local interrupt is an interrupt that occurs locally with respect to the destination CPU, or in other words, an interrupt that occurs within the same subsystem. An example of a local interrupt is an interrupt from a mathematically dual processor. On the other hand,
Global interrupts occur in subsystems other than the destination CPU. Examples of global interrupts include those generated from user keyboards, system timers, disk drive controllers, video controllers, serial or parallel ports, and the like.

Efficient communication and control of interrupts is important to high performance MP systems. In particular, global interrupts must be easily managed among all processors in an MP system where the processors are spread across several different buses.

In the prior art, global interrupts are typically controlled by a "system" interrupt controller. The controller can take the form of a single unit or multiple units working together. Typical system interrupt controllers that can operate independently or in combination include, for example, the INTEL 8259
A programmable interrupt controller (PIC). The "INTEL" 8259 programmable interrupt controller is commercially available and manufactured by Intel Corporation of California, USA.

In the normal interrupt protocol, the system interrupt controller routes all interrupts to any "default" CPU. The default CPU places an identifiable data segment (containing instructions) in shared main memory that specifies the interrupt, the destination CPU, and the interrupt routine to be executed by the destination CPU. Other processors in the MP system constantly access the shared main memory to monitor data segment queues or identifiers. The destination CPU then recognizes the interrupt and processes it according to the specified interrupt routine.

However, the conventional global interrupt management techniques described above have problems in high performance MP systems having multiple buses. It is often the case that the default CPU must temporarily suspend execution of its own program in order to execute code related to channeling interrupts to main memory.

Additionally, there is an excessive amount of communication on the bus between all CPUs and the shared main memory. Due to the large number of transactions that must be performed between the CPU and main memory, the overall speed of the MP system is less than optimal. Furthermore, as a result of the reduced performance, the number of processors that can be connected to the MP system is further limited.

Another method known in the art is called "interrupt snooping." Interrupt nuisance is a problem when the CPU is running on a traditional Extended Industry Standard Architecture (EISA) bus or on a traditional Micro Channel (
It was proposed for MP systems in which the CPU is installed on an I/O card with a dedicated bus such as the MCA bus. The I/O card is plugged into, for example, a high speed system bus of a computer system, thereby forming a multiple bus system.

Interrupt Sensitiveness does not use the concept of a default CPU or any central location to generate interrupts and communicate them. Interrupts are generated and received by each I/O card.

[0016] To perform interrupt-sniff processing, the bus master of each I/O card is provided with an Intel 8259 interrupt controller or its equivalent circuit. Interrupts from that interrupt controller are masked from components of the computer system that are not intended to receive the interrupts. All bus masters monitor the system bus for their respective interrupts and then direct the interrupts to the local CPUs on their respective I/O cards. Essentially all responsibility for global interrupts is transferred from the computer system to the I/O card.

However, the interrupt management mechanisms described above are not ideal for high performance MP systems with multiple buses. This mechanism requires that interrupts be managed on the bus on a bus basis and that each bus has at least one interrupt transceiver mechanism. More specifically, when a CPU is added to the system bus to which an I/O card is connected, the added CPU uses hardware or Replication of the interrupt logic must be done somewhere in the software. Furthermore, standard interrupts from, for example, a system timer and/or user keyboard cannot be interfaced to the system bus without the addition of interrupt circuitry.

[0018]

SUMMARY OF THE INVENTION The present invention provides a system for high performance global interrupt management in a multiprocessor (MP) system having shared storage and which may include multiple architecturally separated buses. and method.

The present invention envisions the implementation of a redirector that receives global interrupts from a system interrupt controller. This redirector may either take the form of software on the default processor or a separate component of hardware, such as a programmable logic array.

After receiving the global interrupt, the redirector:
Global interrupts are communicated directly to individual processors within the MP system. Some of the individual processors may reside on remote, architecturally separate buses, perhaps on input/output (I/O) cards.

It is further envisioned that the present invention can be implemented in a cooperative manner using the concept of interrupt-sensitivity. Interrupt security has previously been contemplated for several commercially available I/O cards.

The present invention overcomes the drawbacks of the prior art as described above and provides additional features and advantages as described below.

First, the present invention reduces the amount of communication on a computer system bus by eliminating unnecessary repeated queries to main memory by the MP system's processor. As a result, the overall speed of the MP system increases and the number of processors that can be connected to the MP system increases.

Second, the invention can be implemented without respecifying the protocols and/or compatible models of the various buses of the MP system.

Third, the present invention is flexible in that it can be implemented in either software or hardware.

Fourth, the present invention allows for a variety of processor configurations. In other words, the present invention can be implemented using homogeneous or non- homogeneous MPUs. For example, “INT
It is possible to mix an MPU of the "EL" family (manufactured by Intel Corporation of the United States) with an MPU of the "MOTOROLA" family (manufactured by Motorola Incorporated of the United States of America).

Other features and advantages of the invention will become apparent to those skilled in the art from consideration of the following drawings and detailed description. All additional features and advantages are intended to be incorporated herein.

The present invention as defined in the claims can also be understood by referring to this document and the drawings.
be better understood.

[0029]

[Example] Figure 1 shows n central processing units (CPUs) 1
1 shows a conventional personal computer (PC) architecture comprising n microprocessing units (MPUs) 102-108, each having n microprocessing units (MPUs) 10-116. MPUs 102 to 108 are the main storage device 1
18 are shared.

MPUs 102-108 reside on several architecturally separated buses. MPU10
2 and MPU 108 reside on system bus 120 along with main memory 118 , while MPU 104 resides on bus 122 and MPU 106 resides on bus 124 . The bus interface is not shown for simplicity. Each of the n MPUs 102 to 108 has conventional input/output (I/O) plugged into the system bus 120.
O) Can be present on the card. As shown in the figure, in addition to the MPUs 104 and 106, their respective buses 1
22,124 may also be present on I/O cards 126,128.

In the MP system of FIG. 1, a system interrupt controller 130 provides for global interrupts within the MP system. This system interrupt controller 130 is connected directly to the system bus 120.

FIG. 2 illustrates a general interrupt protocol using the architecture of FIG. The system interrupt controller sends all interrupts to any "default" CPU. As shown, MPU 10
CPU 2 110 is arbitrarily selected as the default CPU.

Default CPU 110 receives global interrupts from system interrupt controller 130, as indicated by arrow 202. If an interrupt is received by CPU 110, then CPU 110
An acknowledgment (ACK) signal is sent from the system interrupt controller 130 to the system interrupt controller 130.

As shown by arrow 204, the default CPU
110 places the identifiable data segment into shared main storage 118 after receiving a global interrupt signal from system interrupt controller 130 . The data stored in this shared main storage 118 includes interrupts and the intended destination CPU (in the example of FIG.
112, 114, or 116) and an interrupt routine to be executed by the intended destination CPU.

The other CPUs 112 - 116 in the MP system on each MPU 104 - 108 use shared main memory as indicated by corresponding arrows 206 , 208 , 210 to monitor data segment queues or identifiers. 118 constantly.

Finally, the destination CPU (112, 114
, or 116) recognizes the interrupt after sampling the shared main storage 118. The data is then read from shared main memory 118 and the destination CPU
Operate according to the specified interrupt routine.

However, there are problems with the conventional global interrupt management method described above. The default CPU 110 must always temporarily suspend execution of its own programs in order to execute code related to the delivery of interrupts to shared main memory 118 .

Furthermore, there is an excessive amount of communication on the bus between all CPUs 110 - 116 and shared main storage 118 . In FIG. 1, in addition to buses 122 and 124, system bus 120 is also characterized by an excessive amount of communication due to the interrupt protocol.

As shown by arrows 204 to 210 in FIG.
Due to the huge number of transactions that must be made to and from the MPU, the overall speed of the MPU system is less than optimal. Furthermore, as a result of the performance degradation, the number of MPUs that can be connected to the MP system is further limited.

FIG. 3 illustrates the concept of "interrupt-sensitivity" and a management mechanism that uses interrupt-sensitivity in conjunction with the default CPU method.

[0041] Interrupt sniffing can be implemented using either the traditional Extended Industry Standard (EISA) bus or the traditional
) bus has been proposed for MP systems in which the CPU is located on an I/O card with a dedicated, architecturally separate bus, such as a bus. Figures 1 and 3
As shown, MPUs 104 and 106 reside on separate respective I/O cards 126 and 128, which are plugged into system bus 120.

According to interrupt snooping, interrupts are
As indicated by arrow 302, direct communication occurs between MPUs 104 and 106 located on different I/O cards. From an architectural standpoint, this communication, indicated by arrow 302, takes place via buses 120, 122, 124 of FIG. Pure interrupt nuisance will occur if the only ongoing interaction is of this type.

However, one or more other CPUs 102,1
In the MP system of FIG. 1, where CPUs 08 are directly connected to system bus 120, the concept of a default CPU, or some other technique, must be implemented to direct interrupts to these CPUs. Therefore, in this MP system, the default C
It incorporates a hybrid form of interrupt management that includes both the concept of PU and the concept of interrupt prudence.

[0044] In particular, interrupt snooping is
For example, between the I/O card 126 and the I/O
This occurs between card 128 and card 128. At the same time, the CPU
110 operates as the CPU by default. This CPU1
10 directs interrupts to all CPUs on system bus 120, ie, CPU 116. Additionally, the bus masters (not shown) of I/O cards 126, 128 listen for interrupts from system interrupt controller 130, as indicated by phantom line 304.

It should be noted that more than one CPU can be present on each I/O card. Furthermore,
All interrupts from the system interrupt controller 130 are sent to a specific I/O, rather than to a specific CPU on the I/O.
/O card indicates.

However, the above-described hybrid interrupt management mechanism is not suitable for high-performance MBs with multiple buses for several reasons.
Undesirable for P architecture. One reason for this is the unnecessary presence of redundant interrupt managers in MP systems. In fact, each I/O card 126,
In addition to being an interrupt manager, 128 is also a system interrupt controller 130.

Furthermore, a lot of unnecessary traffic is placed on the bus.
Specifically, it still exists on the system bus 120. As a result, speed is reduced and the number of processors that can be connected to the MP system is limited.

FIG. 4 shows a preferred embodiment of the invention. Redirector 402 is configured to connect individual CPs on an I/O card, e.g., I/O card 126 or I/O card 128.
It is implemented to direct interrupts from the system interrupt controller 130 to individual CPUs on every bus, including U.

As shown, redirector 402 communicates with system interrupt controller 1 via bus 404.
Communicate with 30. Furthermore, the redirector 402
individual MPUs 102 - 108 .

Redirector 402 can best be implemented as software-dominant, hardware-dominant, or a combination of software and hardware. If software dominance is implemented, the redirector 402
The functionality of is implemented by program code executed by any CPU, although of the "default CPU" type, but with different functionality as explained later in FIG.

In a hardware-based implementation, the functionality of redirector 402 is accomplished in physical logic circuits. This logic circuitry can be implemented on an external microchip, such as an application specific integrated circuit (ASIC), or on other discrete circuit devices. Furthermore, system interrupt controller 130 and redirector 402 can be integrated on the same circuit device, such as an ASIC. The preferred embodiment uses a programmable logic array (PAL) to implement the hardware logic.

Furthermore, as is well known in the art, a substantial portion of the necessary logic can be implemented in both software and hardware, or a combination thereof.

A system interrupt redirection method using software or hardware will be described below with reference to FIGS. 5 and 6. Figure 5 shows software (S/W)
) relates to interrupt redirection, whereas FIG. 6 relates to hardware (H/W) interrupt redirection.

(1) Block 514 of the flowchart
, 524, (a) redirector 402 and (
b) Any default CPU with code corresponding to the functionality of redirector 402 receives a global system interrupt from system interrupt controller 130 .

(2) Block 516 of the flowchart
, 526, (a) redirector 402 and (
b) either the default CPU, or (b) the default C
The PU uses a lookup table to find the destination CPU.
and its associated I/O address, corresponding interrupt vector, and interrupt priority.

(3) Block 518 of the flowchart
, 528, (a) redirector 402 and (
b) Either the default CPU then writes the contents of the lookup table to the destination CPU.

The present invention provides that redirector 402, or the default CPU, does not need to control or "own" the destination CPU before sending an interrupt, as is the case in semaphore-based systems. It's worth paying attention to. The semaphore scheme indicates whether the CPU is ready or able to receive an interrupt. The semaphore method prevents the CPU from being overwhelmed by multiple interrupt instructions at once.

The reason that neither the default CPU in a software implementation nor the redirector 402 in a hardware implementation is required to own the destination CPU is that the potential source of the global interrupt is , only one exists in the MP system. Additionally, the destination CPU handshakes interrupts from the default CPU or redirector 402;
That is, the response is made.

Another feature of the invention is that the redirector 402
This means that it functions as a kind of buffer/interface between the MPUs 110 to 116 in the MP system. In other words, the present invention enables homogeneous or non- homogeneous processors to be integrated into the same system interrupt controller 1.
It can be operated from 30.

A specific hardware embodiment of the invention is shown in FIGS. 7 and 8. This particular hardware implementation reduces the amount of traffic on the bus network while at the same time
We demonstrate an inexpensive and efficient implementation of generating up to 256 interrupt vectors in a high performance MP system.

The functionality of the redirector 402 is performed partly in a well-defined central location, perhaps at or near the system interrupt controller 130, and partly in local locations for each of the n MPUs 102-108. be done. FIG. 7 shows a portion called the vector translation transmitter that is associated with the system interrupt controller. On the other hand, FIG. 8 shows a portion called a vector conversion receiver associated with each MPU. Substantially, the vector conversion transmitter may be configured to
It communicates system interrupts to the U, while the vector conversion receiver includes handshake logic and logic to handle local interrupts.

[0062] In FIG. 7, a block 602 of imaginary lines indicates,
It can be seen that both the vector conversion transmitter and the vector conversion receiver can be implemented on one circuit unit, such as an ASIC, as shown in phantom block 702 in FIG. It should be noted that the vector translation transmitter may further include a system interrupt controller 130, as shown in FIG.

The vector conversion transmitter architecture of FIG. 7 is compatible with IBM PCs. More specifically, IBM's standard architecture includes a set of cascaded connections "I" that act as a system interrupt controller 130.
NTEL” 8259 Interrupt controller 604, 6
06 is required. Connecting the controllers 604 and 606 in cascade means
It is conventionally well known. The cascade configuration allows for 16 different interrupts, unlike the single ``INTEL'' 8259 interrupt controller, which allows only 8 interrupts. The vector conversion transmitter operates as follows. A 16-bit system interrupt (IRQ 15:0) from some part of the MP system is
latch 608 is under the control of 0. PAL16
10 controls latch 608 through chip enable (CE) control 612 and direction (DIR) control 614. Furthermore, the latch 608 connects a set of parallel PAL6
It consists of 16 to 622.

Cascade connection "INTEL" 8259 interrupt controllers 604, 606 (system interrupt controller 130) connect 4-bit bus 624 (I15:
I12), 4-bit bus 626 (I11:I8)
, 4-bit bus 628 (I7:I4), and 4-bit bus 630 (I3:I0). Next, “INTEL”
8259 interrupt controllers 604 and 606 are
System interrupts are signaled to the PAL 1610 via interrupt line 632. PAL 1610 then sends an interrupt acknowledgement to cascaded INTEL 8259 interrupt controllers 604, 606 via interrupt acknowledge (INT ACK) line 634.

Next, a set of cascade connections "INTEL" 82
59 The interrupt controllers 604, 606 (system interrupt controller 130) transmit a 4-bit interrupt vector (vd3:0) that can specify any of 16 different types of system interrupts to the PAL
1610 and PAL3636. Therefore, the PAL 1610 uses the chip enable control 612
Freezes latch 608 via chip enable control 640 and enables random access memory (RAM) 638 via direction control 642. The PAL3636 converts the 4-bit interrupt vector into an address (va3:va0). This address is sent to a lookup table in RAM 638. As a result, a 16-bit data word is transferred from RAM 638 to system data bus 644, as shown at bus 646. system data bus 64
4 may be a combination of several buses. Additionally, in the preferred embodiment, a 16-bit data word consists of an interrupt vector (8 bits), a vector priority, and the address (slot number) of the CPU to receive the interrupt vector.

The aforementioned 16-bit data word is stored in RAM 6.
38, the PAL 5636 connects the system control bus 648 via controls 650, 652 to write a 16-bit data word to the destination CPU.
generates an I/O cycle. System control bus 648
consists of both the address and control lines of the MP system, and can also be a combination of buses. As shown, PAL3636
can execute the following instructions on system control bus 648: (1) Control signal (CMD/D) indicating either command or data, (2) Storage device or I
Control signal (M/IO) indicating either /O, (3)
A control signal (RD
/WR), (4) a bus request (BUSRQ) signal, and (5) a bus acknowledge (BUSACK) signal.

Furthermore, the interrupt vector output from the RAM 638 is connected to the data line (v
d7:0) 654,656 while the data line (vd7:0) 654,656
Access to is still being considered. Data line (
vd7:0) 654,656 is accessed through the cascade connection “INTEL” 8259 interrupt controller 604
, 606.

Cascade connection "INTEL" 8259 In order to read or write (programs) to interrupt controllers 604 and 606, various signals are sent to P
Monitored from system control bus 648 by AL 1610. As shown, PAL 1610 receives the following signals from system control bus 648: (1
) A control signal (CMD) indicating either a command or data
/D), (2) a control signal (M/IO) indicating either a storage device or I/O, (3) a control signal (RD/WR) indicating either reading or writing, and (4)
) Address (A4:A0 or A4-AO). The above signal is generated by an external I/O device and is called "INTEL".
It can be used to read or write (programs) to either the 8259 interrupt controllers 604, 606 or the RAM 638.

[0069] The external I/O device connects the cascade connection “INTEL
'8259 When attempting to access interrupt controllers 604 and 606, PAL4658 and PAL
5660 is enabled, which causes the “INTE
L'8259 Interrupt controller 604, 606
can be accessed from the system data bus 644. On the other hand, if there are n system interrupts, M
If being sent to one of PUs 102-108, PAL4658 and PAL5660 are disabled, which causes the data line (vd7:0)
654 and 656 are separated from the system data bus 644 and thus ultimately from the 16-bit data word output by RAM 638.

FIG. 8 shows a vector conversion receiver installed near the destination CPU designated by the interrupt vector output from the RAM 638. The vector conversion receiver includes similar components and functionality associated with the vector conversion transmitter, as described below.

The vector translation receiver of FIG. 8 reads the interrupt vector into latch 704 from the system data bus 644 and ultimately from the vector translation transmitter of FIG. Latch 704 connects two parallel PALs, namely PAL2A
706 and PAL2B 708. Furthermore, the latch 704 is connected to the chip enable (CE) control 7
12 and direction (DIR) control 714 via PAL
1710. PAL1610 in Figure 7
Similarly, the PAL 1710 of FIG. 8 serves as the control logic.

A single INTEL 8259 interrupt controller 716 is connected to a parallel bus 71 as shown.
8 (I7:I4), 720 (I3:0) to receive a 7-bit interrupt vector (I7:I0). “I
NTEL” 8259 interrupt controller 716 is
into a 7-bit interrupt vector (along with local interrupts)
Give priority and convert the vector into a 3-bit interrupt vector (vd2:0).

Next, the "INTEL" 8259 interrupt controller 716 controls its associated local CPU (n
one of the MPUs 102-108) is notified of the system interrupt via interrupt line 732. The local MPU then knows that it must signal the INTEL 8259 interrupt controller 716 to perform an interrupt acknowledge cycle. Essentially, the interrupt acknowledge cycle is a special kind of I
/O read.

As shown, the PAL 1710 receives the following signals from the local MPU. (1) Either command or data (CMD/D), (2) Either storage device or I/O (M/IO), (3) Either read or write (RD/WR) ,as well as(
4) Address (A4:A0). PAL1710 is
Decodes the aforementioned signal from the local MPU and sends “INTEL” 8259 via interrupt acknowledge line 734.
Sends an interrupt acknowledgment to interrupt controller 716.

The "INTEL" 8259 interrupt controller 716 has a 3-bit interrupt vector (vd
2:0) to PAL1710. This vector can specify any of eight different types of interrupts. Therefore, PAL 1710 uses latch 7 via cache enable control 712.
04 and enables RAM 738 via cache enable control 740. Furthermore, this P.A.
L1710 converts a 3-bit interrupt vector into an address (va2:va0). This address is R
Sent to lookup table in AM738. Thus, the original interrupt vector (I7:I0) received from the system data bus 644 could be any of 8 different possibilities, and could be any of 256 different possibilities. Used to identify other vectors.

Finally, the interrupt vector is
8 to the associated local MPU via the system data bus (d7:0) 644.

The interrupt vector output by RAM 738 must be separated from the data line (vd7:0) of the "INTEL" 8259 interrupt controller 716, but the data line (vd7:0)
Access to is still being considered. One reason for this is the "INTEL" 8259 interrupt controller 71
In order to be able to access and program the data lines (vd7:0), access to the data lines (vd7:0) is required.

"INTEL" 8259 When attempting to read or write to the interrupt controller, PAL3
758 and PAL4760 are enabled, which causes the system data bus 644 to
” 8259 The interrupt controller 716 can be accessed. On the other hand, if the interrupt is being sent to the associated local MPU, the PAL3758
and PAL4760 are disabled, which causes the ``INTEL'' 8259 interrupt controller 71
The data lines from 644 (vd7:0) are separated from the system data bus 644 and therefore
It is separated from the interrupt vector (d7:0) output by 8.

The systems and methods of the present invention can also be implemented with interrupt sparing, as described above. The device is a hybrid of interrupt sensitivity and software interrupt redirection or hardware interrupt redirection. Such a method is desirable in MP systems with I/O cards where response needs are important.

Software interrupt redirection is suitable for PCs with only one, two, or three microprocessors and associated subsystems. One reason for this is that the invention can be implemented at low cost. Another reason is that there is no burden of adding more hardware to the MP system. Another reason is that the software overhead is not large. Furthermore, the system and method can be more easily designed to make connections across multiple architecturally separated buses.

Hardware interrupt redirection becomes a more desirable form of the invention in MP systems with a large number of global interrupts. In other words, the additional software overhead on the default CPU in such an MP system for handling interrupts can force the default CPU to stall.

Finally, interrupt sensitivity via software interrupt redirection, interrupt redirection, or software or hardware interrupt redirection is compatible with OS/2 or UNIX operating systems (drivers). The reason is that global interrupts are invisible to the operating system and application programs.

It should be understood that the invention is not limited to the preferred embodiments, and that the embodiments described above are merely examples for illustrative purposes. The scope of the invention should, therefore, be construed by the claims as defined by the foregoing detailed description and drawings.

[0084]

[Effects of the Invention] Since the present invention is configured as described above, M
Reduces the amount of communication on the computer system's bus by eliminating unnecessary repeated queries to main memory by the processor of the P system, thereby increasing the overall speed of the MP system and making it possible to connect to the MP system. The number of processors can be increased. Additionally, the present invention can be implemented without respecifying the protocols and/or compatible models of the various buses of the MP system, and can be implemented in both software and hardware. In addition, the present invention takes into account a variety of processor configurations, including homogeneous or non- homogeneous MPUs.
It can be carried out using Thus, the present invention makes it possible to manage global interrupts with high performance in an MP system that has a shared storage device and can have multiple architecturally separated buses.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a conventional multiprocessor system with n multiple processing units that can be employed in a personal computer architecture.

FIG. 2 is a block diagram illustrating a general interrupt protocol using the architecture of FIG. 1 in which a system interrupt controller routes all system interrupts to the MPU's optional "default" CPU.

[Figure 3] Concept of “interruption nosy” and default CP
FIG. 3 is a block diagram illustrating a management mechanism using interrupt prudence in combination with method U;

FIG. 4 illustrates a preferred embodiment of the present invention implementing a redirector in the form of hardware, software, and combinations thereof to channel global system interrupts from a system interrupt controller directly to individual CPUs of an MP system; It is a block diagram.

FIG. 5 is a flowchart illustrating a method for implementing software interrupt redirection of the present invention.

FIG. 6 is a flowchart illustrating a method for implementing hardware interrupt redirection of the present invention.

FIG. 7 is a block diagram illustrating a vector translation transmitter located near a system interrupt controller that is part of a particular hardware embodiment of a redirector according to the present invention.

FIG. 8 is a block diagram illustrating the remainder of a particular hardware embodiment of a redirector according to the invention, a vector conversion receiver located near each of the n MPUs of the MP system;

[Explanation of symbols]

102-108 MPU 130 System interrupt controller 4
02 Redirector

Claims (1)

[Claims] 1. A system for improving the performance of a computer system having a shared storage device and at least one processor, the system comprising: a system interrupt controller that generates interrupts; and a system that receives interrupts from the system interrupt controller. A redirection system for redirecting interrupts to a microprocessor, comprising: a redirector that receives the interrupt and directly notifies each processor in the computer system of the interrupt.