JPH04317226A - Data synthesizing circuit - Google Patents

Abstract

PURPOSE:To provide a data synthesizing circuit eliminating a need for a large capacity shift register, a gate circuit and a control signal and permitting simplification and size reduction of the circuit. CONSTITUTION:By providing latch circuits 58 and 59, respectively, on the output side of shift registers 51 and 52 retaining second data and setting these latch circuits 58 and 59 in a reset state, the lead bit of the second data is prevented from being outputted during the non-output period of the second data. When the second data is to be outputted, the second data are read out of shift registers 51 and 52 while synchronizing with a space position for the second data in a data train outputted from an error correction encoder 13, the second are supplied to an OR gate via the latch circuits 58 and 59 and inserted in the space in the data train.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a base station or mobile station used in a mobile radio communication system such as a mobile/car telephone system or a cordless radio telephone device, in which a plurality of pieces of data are combined to form transmission data. The present invention relates to a data synthesis circuit provided for the purpose of

0002

2. Description of the Related Art In recent years, a system employing a digital system has been proposed as one of mobile radio communication systems. This type of system digitizes not only control signals but also call content such as call voice, and uses this digital data between the base station and mobile station using time division multiple access (TDMA).
This method ensures confidentiality, improves compatibility with data, and makes effective use of radio frequencies.

FIG. 2 shows the configuration of a wireless communication device for a mobile station used in this type of system. This device is roughly divided into a transmitting system, a receiving system, and a control system. In addition, 4
0 is a battery as a power source.

First, the transmission system includes a transmitter 11, a speech encoder (SPCOD) 12, and an error correction encoder (CHCOD).
13, a digital modulator (MOD) 14, and an adder 1
5, a power amplifier (PA) 16, a high frequency switch circuit (SW) 17, and an antenna 18. The speech encoder 12 encodes the transmission signal output from the transmitter 11. Further, the error correction encoder 13 performs error correction encoding on the digitized transmission signal outputted from the audio encoder 12 and the digitized control signal outputted from the control circuit 30. The data is supplied to control circuit 30. In the control circuit 30, data that does not require error correction coding is further added to the data subjected to the error correction coding, and the added data is supplied to the digital modulator 14. This digital modulator 14 generates a modulated signal according to the transmission data supplied from the control circuit 30. The adder 15 adds this modulated signal to the carrier signal output from the frequency synthesizer 31, thereby converting the frequency. and power amplifier 16
Then, the wireless transmission signal output from the adder 15 is amplified to a predetermined transmission power. The high frequency switch 17 becomes conductive only during a transmission time slot specified by the control circuit 30, and during this period supplies the radio transmission signal output from the power amplifier 16 to the antenna 18, and sends the radio transmission signal from the antenna 18 to a base (not shown). Send it to the station.

On the other hand, the receiving system includes a receiver (RX) 21
, a digital demodulator (DEM) 22, an error correction decoder (CHDEC) 23, and a speech decoder (SPDEC) 2
4 and a receiver 25. In the receiver 21,
Frequency conversion of the radio reception signal received by antenna 18 and high frequency switch 17 is performed in a reception time slot of a predetermined radio frequency. In the digital demodulator 22, bit synchronization and frame synchronization are achieved with respect to the received signal output from the receiver 21, and the synchronization signal is supplied to the control circuit 30. Error correction decoder 23
Then, the digital demodulated signal output from the digital demodulator 22 is subjected to error correction decoding. The digitized reception signal obtained by this error correction decoding is output to the audio decoder 24, and the digitized control signal is supplied to the control circuit 30. The audio decoder 24 decodes the digitized call signal. Then, the analog reception signal restored by this decoding process is amplified and outputted from the receiver 25.

[0006] Furthermore, the control system includes a control circuit (CONT) 30
, a frequency synthesizer (SYN) 31, a received field strength detection circuit (RSSI) 32, and a transmission request switch (S
W) 33. Of these, the frequency synthesizer 31 generates local oscillation signals corresponding to each channel frequency for control and communication designated by the control circuit 30. The received field strength detection circuit 32 detects the received field strength of radio waves transmitted from the base station, and the detected signal is sent to the control circuit 30 for searching for empty channels and monitoring out of communication range.
will be notified.

By the way, the format of data transmitted from the mobile station device to the base station device is configured as shown in FIG. 3, for example. That is, guard time G and ramp time R each consisting of 6 bits are placed at the beginning, followed by 16 bits of user data DATA, 28 bits of synchronization signal SYNC, 122 bits of user data DATA, and 12 bits of low speed control data. SACCH(S
low Associated Control Ch.
annel), 12-bit collation code CDVCC (C
oded Digital Verification
Coler Code) are arranged in order, and finally, 122-bit user data DATA is arranged again.

Of these, the synchronization signal SYNC and the verification code CDVCC are data determined in advance according to instructions from the base station, and are transmitted without error correction encoding processing. On the other hand, user data DATA and low-speed control data SACCH are data that can be generated independently by the mobile station, and are transmitted after being subjected to error correction encoding processing. In other words, the transmission data includes data that requires error correction encoding and data that is unnecessary, and these data must be combined when being transmitted.

[0009]

[Problems to be Solved by the Invention] Conventionally, this data is synthesized as follows, for example. That is, a register for storing all data for one slot is provided in the control circuit 30, and the user data DATA and low-speed control data SACCH encoded by the error correction encoder 13 are stored in the control circuit 30. The synchronization signal SYNC and verification code CDVCC generated within the memory are temporarily stored, and after all data is stored, they are sequentially read out and supplied to the digital modulator. However, in such a configuration, the control circuit 30 must be provided with a large-capacity shift register corresponding to one slot data (324 bits), which causes the problem that the circuit configuration of the control circuit 30 becomes complicated and large. be.

On the other hand, as another conventionally considered data synthesis circuit, when outputting user data DATA and low-speed control data SACCH from the error correction encoder 13, for example, as shown in FIG. A space is formed in which the synchronization signal SYNC and the verification code CDVCC are inserted, and the control circuit 30 stores the user data D.
It has been considered that the ATA and low-speed control data SACCH are passed through as is, and the collation code CDVCC and synchronization signal SYNC are inserted in the above space as shown in FIGS. 4(b) and 4(c), and then output to the digital modulator 14. There is. FIG. 5 shows the circuit configuration.

In the figure, a control circuit 30 is provided with shift registers 51 and 52 for holding a verification code CDVCC and a synchronization signal SYNC, respectively.
These shift registers 51 and 52 have a verification code CD.
VCC and synchronization signal SYNC are preset. Then, during the space period in the data supplied from the error correction encoder 13, the gate control signals CG1 and CG2 set the AND gates 53 and 54 to the open state and supply the read clock CK to the shift registers 51 and 52. , As a result, from the shift registers 51 and 52 as shown in FIGS. 4(b) and (c)
As shown in the above, the verification code CDVCC and synchronization signal S
YNC is read out and these data are supplied to the digital modulator 14 via an OR gate 55. With such a circuit, a shift register for one slot data can be eliminated, so the control circuit 30
This makes it possible to simplify the circuit configuration.

However, this data synthesis circuit has the following problems that should be improved. In other words, the bit capacities of shift registers 51 and 52 are each equal to the collation code CDVC.
C and the bit length of the synchronization signal SYNC. Therefore, when the collation code CDVCC and synchronization signal SYNC are set in these shift registers 51 and 52, the first bit is always stored in the shift registers 51 and 52.
It will be in the state output from. Therefore, depending on the code of the first bit, the data output from the error correction encoder 13 may be masked and corrupted.

Therefore, in this circuit, as shown in FIG. 5, AND gates 56 and 57 are provided between the output terminals of each shift register 51 and 52 and the OR gate, and these AND gates 56 and 57 are connected to gate control signals CG3 and CG4. By controlling the gate with , the leading bit is prevented from being output to the OR gate 55 during a period other than the read period of the collation code CDVCC and the synchronization signal SYNC.

However, in such a configuration, the AND gates 56 and 57 must be newly provided, and gate control signals CG3 and CG4 for controlling these AND gates 56 and 57 must also be newly created. . Therefore, there is still a problem that the configuration of the control circuit becomes complicated.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a data processing system that can easily miniaturize the circuit by eliminating the need for large-capacity shift registers, gate circuits, control signals, etc. The purpose is to provide a synthetic circuit.

[0016]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a data output that outputs a data string in which an n-bit space is formed between first data or at a predetermined position in the first data. and a data storage means having a storage capacity of n+1 bits, in which second data is stored in the rear n bits, and the first bit is set to a reset state, and the data string is output from the data output means. The second data stored in the data storage means is serially output in synchronization with the space position of the data storage means, and this second data is combined with the data string output from the data output means. It is something.

The present invention also provides a data storage means arranged at an n-bit shift register for storing the second data and at the output side of the shift register, so that the data storage means is disposed on the output side of the shift register, and the data storage means is disposed on the output side of the shift register to It is also characterized by comprising a 1-bit flip-flop set to a reset state.

[0018]

[Operation] As a result, according to the present invention, the data storage means for storing the second data is constructed with one bit more than the first bit, and the first bit is set to the reset state, so that the second data is not output. During this period, the first bit of the second data is not output, and the reset bit is output. Therefore, even if the first bit of the second data is at the "H" level, the first data will not be masked and destroyed by this "H" level, thereby ensuring stable data synthesis at all times. It becomes possible to do so. Further, as the data storage means, it is sufficient to prepare one sufficient to store the second data and one bit for reset, and there is no need for a register to store all the first data and the second data. Therefore, the data storage means can be made to have a relatively small capacity, which allows the circuit to be easily miniaturized.

[0019]

[Examples] Examples of the present invention will be described below. FIG. 1 is a circuit diagram of a data synthesis circuit according to an embodiment of the present invention. In this figure, the same parts as those in FIG. 5 will be described with the same reference numerals.

The data synthesis circuit in the control circuit 300 includes:
Shift registers 51 and 52 are provided for storing a verification code CDVCC and a synchronization signal SYNC, respectively. The bit capacities of these shift registers 51 and 52 are determined by the collation code CDVCC and synchronization signal SYN, respectively.
It is determined in accordance with the number of bits of C. Furthermore, AND gates 53 and 54 are provided on clock supply paths to these shift registers 51 and 52. These AND gates 53 and 54 receive gate control signals CG1 and CG2 respectively supplied from a timing generation circuit (not shown).
The shift clock CK is gate-controlled according to the following. The timing generation circuit receives gate control signals CG1, C
G2 is output in synchronization with the data output operation of the error correction encoder 13 during a period corresponding to the space position shown in FIG. 4(a).

Now, the output paths of each of the shift registers 51 and 52 are provided with latch circuits 58 and 1 bits, respectively.
59 are provided. These latch circuits 58, 59
consists of a D flip-flop, and the above AND gate 53
, 54, the data shifted and output from the shift registers 51 and 52 is
Each bit is latched and output to the OR gate 55. The OR gate 55 inserts the data output from the latch circuits 58 and 59 into the space position of the data string output from the error correction encoder 13, and supplies this to the digital modulator 14 as transmission data.

In such a configuration, the control circuit 300
is set by inputting the verification code CDVCC and the synchronization signal SYNC in parallel to the shift registers 51 and 52, respectively, at a predetermined timing before the transmission time slot of the own station. In addition, each latch circuit 58
, 59 from a timing generation circuit (not shown) to reset the states of the latch circuits 58 and 59. In other words, the outputs of the latch circuits 58 and 59 are "l".
“It is set to the level.

Now, in this state, when the transmission time slot period of the own station comes, the timing generation circuit of the control circuit 300 issues a data output instruction to the error correction encoder 13. Then, from the error correction encoder 13, the data string shown in FIG.
H and synchronization signal SYNC and verification code CDV
Output of the data string in which a space for inserting a CC is formed is started, and is input to the OR gate 55. On the other hand, the AND gates 53 and 54 select the user data DATA and the low-speed control data SACCH among the data strings.
The gate is set to the closed state during the period in which is being output, and therefore the output level of the latch circuits 58 and 59 is “L”.
” is held at the level. Therefore, ORGATE 5
5, the data string output from the error correction encoder 13 passes through as is and is supplied to the digital modulator 14. That is, the user data DATA and low-speed control data SACCH output from the error correction encoder 13
is correctly transferred without being masked by the data set in the shift registers 51 and 52.

On the other hand, in the output period of a space for inserting a synchronization signal SYNC in the data string, for example, a gate control signal CG2 is generated from a timing generation circuit (not shown), and the AND gate 54 is thereby placed in an open state. . Therefore, a synchronizing signal SYNC is shifted out from the shift register 52 in synchronization with the shift clock CK, and this synchronizing signal SYNC is supplied to the OR gate 55 via the latch circuit 59. Therefore, the OR gate 55 inserts the synchronization signal SYNC into the space of the data string output from the error correction encoder 13 and supplies it to the digital modulator 14.

Similarly, when it comes to the output period of the space for inserting the collation code CDVCC in the data string,
Gate control signal CG from a timing generation circuit (not shown)
1 is generated, which causes AND gate 53 to be in an open state. Therefore, the verification code CDVCC is shifted out from the shift register 51 in synchronization with the shift clock CK, and this verification code CDVCC is supplied to the OR gate 55 via the latch circuit 59. Therefore, the OR gate 55 inserts the collation code CDVCC into the space of the data string output from the error correction encoder 13 and supplies it to the digital modulator 14.

As described above, in this embodiment, the latch circuits 58 and 52 are respectively provided on the output sides of the shift registers 51 and 52 that hold the verification code CDVCC and the synchronization signal SYNC.
59, verification code CDVCC and synchronization signal S
These latch circuits 58
, 59 are held in the reset state, the collation code CD held in the shift registers 51 and 52
The problem in which the first bit of VCC and the synchronization signal SYNC is output to the OR gate 55 is prevented, and thereby the problem in which the user data DATA and low-speed control data SACCH output from the error correction encoder 13 are masked and destroyed does not occur. .

Furthermore, in this embodiment, the latch circuits 58 and 59
Since this can be achieved by simply adding a gate control signal, there is no need to create a new gate control signal, thereby simplifying the configuration of the timing generation circuit. That is, according to this embodiment, prevention of masking of transmission data can be achieved with a simple circuit configuration.

It should be noted that the present invention is not limited to the above embodiments. For example, in the above embodiment, the shift register 51
, 52 are added with latch circuits 58 and 59, but a shift register with one bit more than the shift registers 51 and 52 is provided, and a collation code is stored in the area excluding the first bit of each of these shift registers. CD
It may be configured such that VCC and synchronization signal SYNC are set, and the first bit is set to "L" level. In that case, the verification code CDVCC and synchronization signal S
When configuring YNC, an "L" level code may be added to the first bit in advance. In this way, it is only necessary to set the verification code CDVCC and the synchronization signal SYNC in the shift register, and separately from setting these data, it is necessary to set the "L" level,
Furthermore, there is no need to reset the latch circuit. In addition, the type and length of data, the circuit configurations of the data storage means and data synthesis means, etc. can be modified in various ways without departing from the gist of the present invention.

[0029]

Effects of the Invention As described in detail above, according to the present invention, n
data output means for outputting a data string forming a bit space;
data storage means for storing second data in bits and setting the first bit to a reset state; By serially outputting the stored second data and combining this second data with the data string output from the data output means, large-capacity shift registers, gate circuits, and control signals can be It is possible to provide a data synthesis circuit which can be easily miniaturized by eliminating the need for the above.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a data synthesis circuit in an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing an example of the configuration of a mobile station wireless communication device of a mobile/automobile wireless telephone system.

FIG. 3 is a diagram showing an example of the format of a transmission signal used in a mobile/automobile radio telephone system.

FIG. 4 is a timing diagram showing an example of data synthesis operation.

FIG. 5 is a circuit diagram showing the configuration of a conventional data synthesis circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11... Transmitter, 12... Audio encoder, 13... Error correction encoder, 14... Digital modulator, 15... Adder, 16... Power amplifier, 17... High frequency switch, 18... Antenna, 2
1... Receiver, 22... Digital demodulator, 23... Error correction decoder, 24... Audio decoder, 25... Receiver, 30, 30
0... Control circuit, 31... Frequency synthesizer, 32... Received field strength detection circuit, 33... Transmission request switch, 40... Battery, 51, 52... Shift register, 53, 54... AND gate, 55... OR gate, 58, 59... latch circuit.

Claims (2)

[Claims] 1. Data output means for outputting a data string having first data and an n-bit space formed between the first data or at a predetermined position in the first data; data storage means having a storage capacity of , in which the second data is stored in the rear n bits and the first bit is set to a reset state; reading means for serially outputting the second data stored in the data storage means; and combining the data string output from the data output means and the second data output from the data storage means. A data synthesis circuit comprising: synthesis means. 2. The data storage means according to claim 1, wherein the data storage means comprises an n-bit shift register and a 1-bit flip-flop arranged on the output side of the shift register. Synthetic circuit.