JPH04311233A - Address translating device - Google Patents

Abstract

PURPOSE:To make a memory which is controlled for a virtual storage accessible by translating a logical address generated by means of a peripheral controller into a physical address. CONSTITUTION:A translation reference buffer (TLB) 7 is constituted by combining plural pieces of address translating information 5 respectively constituted to store a set of logical address information 16 and physical address information 18 and selects suitable one out of plural address translating information and outputs the physical address information contained in the selected address translating information to a memory 2 against address information 14 inputted from a graphics control unit 4. When the suitable address translating information cannot be selected, the TLB 7 outputs a mis-hit signal to a processor 1. Therefore, a graphics controller can translates a logical address into a physical address and a graphics system corresponding to a virtual storage can be realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation device for a peripheral controller, and more particularly to an address translation device for a drawing address in a computer system using virtual memory or multitasking in a graphics controller.

0002

2. Description of the Related Art In recent years, operating systems that support virtual memory control have appeared on personal computers as well. Along with improving the processing power and expanding the address space of microprocessors, this has led to the development of memory management units (hereinafter referred to as MMUs).
ENT Unit). } is built into the processor, which contributes to this.

[0003] In the case of a system that performs virtual memory control, an address translation mechanism is required. That is, it is necessary to convert a logical address output by a bus master (a device that outputs an address) such as a processor into a physical address that is actually accessed in a memory or the like. The MMU performs this address conversion, and modern processors often have it built-in. In this case, the address output from the processor becomes a physical address.

[0004] Here, the paging method, which is a typical virtual memory management method, will be briefly explained using FIG. In the paging method, the logical address 33 is divided into multiple parts (
In the case of FIG. 7, it is divided into three parts), which are called area ID, page ID, and intra-page offset. First, a page table address corresponding to the area ID is obtained from the area table 35. Next, the physical page number corresponding to the page ID is obtained from the page table 36 indicated by this page table address. The physical address 34 is obtained by combining this physical page number and the intra-page offset.

However, since the area table 35 and page table 36 are stored in the memory 32, repeating such table references every time the memory is accessed results in a very slow system. Therefore, the translation reference buffer {hereinafter referred to as TLB (Translation
Look-aside Buffer). }
37 is used. The TLB 37 is composed of an associative memory, uses a portion (area ID, page ID) obtained by removing the intra-page offset from the logical address 33 as a key input, and has a physical page number corresponding to the input as an output. If the same value as the key input is registered in the TLB 37, the corresponding physical page number is immediately output and the physical address 34 can be generated. If the key input value is not registered in the TLB 37, a miss-hit signal 38 is output. When the processor 31 receives this miss-hit signal 38, it refers to the area table 35 and page table 36 to obtain the physical page number. The obtained physical page number is used to generate the physical address 34 and is registered in the TLB 37 in combination with the area ID and page ID values. Therefore, when accessing a certain page, the table is referenced once and the TL
If you register on B37, access from the second time is on TL.
This can be done quickly through B37. The size of one page is usually set between 1 and 16 kilobytes.

FIG. 3 is an example of the correspondence between logical address space and physical address space. Here, one page is 4 kilobytes. In this way, in the paging method, consecutive logical pages correspond to discrete physical pages.

Now, general application level software operates based on logical addresses, and it is usually impossible to know which physical address the logical address corresponds to. Only an operating system (hereinafter referred to as OS) operating at a privileged level or in a mode called supervisor can operate the MMU and associate logical addresses with physical addresses.

The problem here is how to handle a peripheral controller that exists outside the processor and serves as a bus master. In non-virtual memory systems, the processor, peripheral controllers, and the software that controls them all operate based on the same address information. However, under virtual memory control, the addresses at which processors and peripheral controllers drive the bus are physical addresses;
Addresses managed by software are logical addresses. At this time, the processor itself automatically converts logical addresses and physical addresses using the MMU, but the peripheral controller cannot perform such conversion because it does not have an MMU. Naturally, it cannot support virtual memory systems as is. As a peripheral controller that can become such a bus master, DMAC (Dir
ect MemoryAccess Control
ller) and graphics controllers.

Regarding DMAC, for example, the 68450 (Motorola) and 82258 (Intel) have been announced as products compatible with virtual memory, but graphics controllers are not yet compatible with virtual memory. D.M.A.
Although it supports virtual memory in C, it only has a mechanism for continuously accessing discretized physical pages, and all the address information given to DMAC must be physical addresses, and the address information for that purpose is The conversion process must be performed by the processor. However, in the case of a DMAC, this is fine because the address to be accessed can be determined in advance, but in the case of a graphics controller, it is difficult to know the drawing address (=logical address) until the access is actually performed, so the processor Convert the logical address to a physical address,
It is impossible to set drawing parameters to a graphics processor that correspond to physical addresses. Therefore,
Conventionally, the following methods have been used to draw graphics in virtual memory systems.

The first is a method in which a memory area dedicated to graphics drawing is prepared without virtual storage, and the graphics controller draws only in that area.

The second method is that when drawing graphics in an area where virtual storage is performed, the processor performs the drawing without using a graphics controller.

[0012] That is, it is almost impossible for a graphics controller to draw in an area where virtual memory is managed. However, as virtual memory systems become more widespread in the future, the need for multitasking and window display functions is expected to increase, and in this case the graphics controller will need to be able to draw at high speed throughout the entire system memory.

[0013]

[Problem to be solved by the invention] As explained above,
Conventional graphics controllers cannot draw in memory areas managed by virtual memory. This is because the software that provides control information to the graphics controller is designed based on logical addresses, whereas the addresses accessed by the graphics controller must be physical addresses. Furthermore, when virtual storage is performed using a paging method, continuous areas on logical addresses are mapped as discrete areas on physical addresses, making it even more difficult to handle virtual storage.

[0014] Furthermore, multitasking, multiwindow, and other processes are often performed on virtual storage systems. When each task tries to display some kind of graphics independently in multitasking, it draws directly to the frame area (the contents of this area are displayed on a CRT, etc.. Normally, virtual memory management is not performed in this area). If you do so, confusion will occur such as the display priority order being broken, so
In some cases, a method is used in which drawing is performed once in the work area, and then only the portion to be displayed based on the drawing result is transferred to the frame area and displayed. In such a case, the drawing work area used by each task generally needs to be acquired in a system area (an area where virtual memory is managed). In this case, being able to freely access the virtual storage area is an essential condition, and there is a great need for a graphics controller that has such a function.

The above problems can be solved if the graphics controller incorporates an MMU equivalent to that of the processor, but on the other hand, the method for realizing virtual memory is
It varies depending on the hardware configuration and OS of the U.
Supporting only a specific method results in loss of versatility. Also, the graphics controller has MM
In order to incorporate U, it is necessary for the graphics controller itself to create address conversion information by referring to a page table, etc., and firmware, etc. for this purpose is required. Furthermore, referring to the table requires accessing a system area that should be protected by the OS, but it is dangerous and undesirable for a peripheral controller to access such a system area without being under the control of the processor.

An object of the present invention is to solve the above-mentioned problems, thereby making it possible to convert logical addresses and physical addresses in peripheral controllers, especially graphics controllers, and constructing a graphics system compatible with virtual memory. The purpose of the present invention is to provide an address translation device that can perform the following tasks.

[0017]

[Means for Solving the Problems] The present invention provides a logical address generation means for generating logical address information from data input from a processor, and a means for converting the generated logical address information into physical address information for use in a memory. In an address translation device including a translation reference buffer for outputting, the translation reference buffer is configured by combining a plurality of pieces of address translation information configured to store the logical address information and the physical address information as a set. , select one piece of address translation information that matches the input logical address information from among the plurality of address translation information, output the physical address information included in the address translation information to the memory, and The present invention is characterized in that it includes means for outputting a miss signal to the processor when the address conversion information that has been selected cannot be selected.

Further, in the present invention, the conversion reference buffer includes control information for controlling conversion processing in addition to the logical address information and the physical address information as the address conversion information, and a processing means for this control information is provided. It is characterized by containing.

[0019]

[Operation] The translation reference buffer (TLB) stores logical address information and physical address information as a set.
When logical address information is input, logical address information matching the logical address information is searched for, and if any, physical address information paired with the logical address information is extracted and output to the memory. If a matching one is not registered, a miss signal is output to the processor.

Therefore, according to the present invention, it is possible to convert logical addresses and physical addresses in the graphics controller, and it is possible to configure a graphics system compatible with virtual memory.

Furthermore, by adding control information such as a task number, access mode control information, or page size information in addition to the logical address information and physical address information, it is possible to easily support multitasking processing. It becomes possible to prohibit illegal memory access or reduce the number of access conversion information to be used.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which the present invention is applied to a graphics system. Further, FIG. 2 is an explanatory diagram showing the structure of the address translation information, and FIG. 3 is an explanatory diagram showing the memory map based on the virtual memory.

The first embodiment uses a drawing address generator (A
G) Graphics control unit 4 including 21
In the graphics controller 3 as an address conversion device equipped with a TLB 7 that converts the drawing address 14 into physical address information and outputs it to the memory 2, the TLB 7 is a feature of the present invention. The page ID 16 as the physical address information and the physical page number 18 as the physical address information are configured by combining four pieces of address conversion information 5. Select one matching address translation information 5 from among the address translation information 5, output the physical page number 18 as physical address information included in the address translation information 5 to the memory 2, and select the matching address translation information 5. 5
When the processor 1 cannot select the miss hit signal 19,
It includes means for outputting to.

In FIG. 1, reference numeral 4 denotes a graphics control unit having a graphics controller means, which includes a drawing address generator (AG) 21 that generates and outputs a drawing address 14 based on data input from the processor 1. Contains. Further, 10 is a system address bus for the processor 1 to access the memory 2 and the graphics controller 3, 11 is a system data bus, 12 is a graphics address bus for the graphics controller 3 to access the memory 2, and 13 is a system address bus for the processor 1 to access the memory 2 and the graphics controller 3. A graphics data bus, and 17 are part of the drawing address 14 and an offset within the page.

[0025] Here, the drawing address 14 is the page ID
16 and intra-page offset 17, page ID
16 is used as input to TLB7, and in-page offset 17 is the physical page number 18 which is the output of TLB7.
The graphics address bus 12 is combined with the graphics address bus 12. In the first embodiment, the address bus is 24 bits, and the page ID 16 and intra-page offset 17 are both 12 bits. Therefore, one page is 4 kilobytes.

Here, the system address bus 10 and the graphics address bus 12 are physical addresses,
The drawing address 14 is a logical address.

Next, the operation of the first embodiment will be explained. First, the processor 1 allocates memory to be used, sets coordinates, etc. to the graphics controller 3. In the case of Figure 3, 202000 in the logical address space
The area from addresses H to 204FFFH is used as a work area, and drawing is performed within that area.

Next, the processor 1 instructs processing such as drawing graphics such as straight lines and arcs, or copying the specified area to another area, as necessary. When the graphics controller 3 receives this instruction, it generates a drawing address and drawing data. Conventional graphics controllers accessed memory using the drawing address generated here as is. However, since the drawing address 14 obtained here is a logical address, it is necessary to convert this into a physical address in the virtual memory system. To do this, we need to set the drawing address 14 to the in-page offset 17 of the lower 12 bits and the page ID of the upper 12 bits.
The page ID 16 is input into the TLB7. If the value indicated by the drawing address 14 is address 203123H, the page ID 16 is 203H, and the offset within the page is 17.
is 123H.

[0029] Initially, nothing is registered in TLB7. There, the page ID 16 (20) of the first drawing address 14
3H) is input as a key, the address translation information corresponding to this key input does not exist in the TLB 7, so a miss signal 19 is output, causing an interrupt in the processor 1. At the same time, the graphics controller 3 suspends its execution. When the processor 1 recognizes the miss-hit signal 19 from the TLB 7, it reads the page ID 16 of the drawing address that caused the miss from the graphics controller 3, and obtains the corresponding physical page number (206H). This physical page number 1
The algorithm for calculating 8 depends on the processor and OS used.
The graphics processor is not concerned with this. After the address translation information 5 shown in FIG. 2 is created using the obtained physical page number 18 and page ID 16, the processor 1 registers the information in the TLB 7.

When the graphics processor 3 resumes operation after waiting for this registration, the TLB 7 registers the input page I.
Physical page number 18 (35
6H) is output. And physical page number 18 (35
6H) and intra-page offset 17 (123H) is output to the graphics address bus 12 as a physical address, and memory access for drawing is performed.

From now on, the physical page number 18 can be immediately obtained for the drawing address 14 having the same page ID as that registered in the TLB 7. If the drawing address has a page ID that is not registered in the TLB 7, the miss-hit signal 19 is outputted again and the processor 1 is asked to register new address conversion information 5.

[0032] If there is no room to register new address translation information 5 in TLB 7, select one of the address translation information 5 that has already been registered, delete that information, and replace the new address translation information in that part. Register. When processor 1 changes the correspondence between logical addresses and physical addresses, or swaps out physical pages (saving a certain page in memory to auxiliary storage and using that part as a new page), the change is It is necessary to reflect this in TLB7 as well. At this time, the processor 1 performs all operations such as determining the address translation information 5 to be deleted and registering the address translation information 5 in an arbitrary position. Therefore,
Processor 1 can freely access the contents of TLB 7 in the same way as reading or writing memory 2.

As described above, by converting the address output of a conventional graphics controller using the TLB, a drawing address, which is a logical address, can be converted to a physical address, and it is possible to correspond to virtual memory. Since all TLB operations are performed by the processor, any method can be used to implement the virtual memory. It is not necessary that the size of the TLB or its contents match the TLB of the MMU on the processor side. However, the size of the page managed by the MMU on the processor side and the size of the page according to the TLB on the graphics controller side must match.

Furthermore, in the case of a TLB with a simple configuration as in the first embodiment, it does not have a memory protection function between tasks by itself, but in that case, the contents of the TLB are invalidated every time the task in the processor is switched. This can prevent unauthorized access. Alternatively, each task may have a copy of the TLB in memory, and the TLB may be replaced so that only the address translation information regarding the task exists in the TLB while the task is being executed.

FIG. 4 is a block diagram showing a second embodiment of the present invention, showing a case where multitasking support and memory protection means are added to the TLB in the first embodiment of FIG. 1. Further, FIG. 5 is an explanatory diagram showing the structure of the address translation information, and FIG. 6 is an explanatory diagram showing the memory map based on the virtual memory.

The second embodiment is characterized in that the TLB 8 contains, as address translation information 6, logical address information consisting of an area ID 15 and a page ID 16, and a physical page number, as shown in FIG. In addition to the physical address information consisting of 18, it includes an access mode flag, a page size flag, and a task number as control information for controlling the conversion process, and as a processing means,
It includes a task number register (TR) 9 that stores the number of the task that requested drawing. Note that the number of entries in TLB8 (the number of address translation information that can be registered) is eight.

TLB8 has three key input fields and two
Consists of bits of flag information and one output field. Correspondingly, the drawing address 14 is the area ID
15, page ID 16, and intra-page offset 17
It is divided into three parts, area ID 15 and page ID
16 is input to TLB8 as a key. In FIG. 4, the area ID 15 is 12 bits, the page ID 16 is 8 bits, and the intra-page offset 17 is 12 bits. Furthermore, the task number register 9 is also used as a key input to the TLB 8. This means that in the case of multi-task processing, if it cannot be confirmed that the address translation information is that of the own task, there is a possibility that the address translation information of another task will be hit and the area of the other task destroyed. It is from.

The two types of flag information attached to the conversion information of TLB8 have the following meanings. Address conversion information 6 with an access mode flag of "1" means that only read access is possible and write access is not permitted, and address conversion information 6 with an access mode flag of "0" allows both read and write access. means that it has been

Address conversion information 6 whose page size flag is "1" ignores the key input of page ID 16 and converts to T.
Referring to LB8, the size of one page is set to 20 bits (=1 megabyte), which is the sum of page ID 16 and intra-page offset 17. Address conversion information 6 whose page size flag is "0" has area ID 15 and page ID 1.
6 refer to TLB 8, and the size of one page is 12 bits (4 kilobytes) at intra-page offset 17. This is to reduce the amount of entries used in the TLB 8 by increasing the size of one page for areas that are already mapped continuously in the physical address space, such as frame areas and font information.

Next, the address conversion method in the second embodiment will be explained with reference to FIG.

First, each task requests an address space of an arbitrary size from the OS as a work area for drawing, and obtains it. In Figure 6, task 1 is 300000H~3
02FFFH, task 2 is 2FE000H~2FFF
Assigned FFH. Each task sets the drawing coordinate system and other parameters for the acquired work area. From now on, the task will draw in the work area defined here.

A drawing request for each task is sent to the graphics controller 3 through the OS. At this time, O
S sets the number of the task that requested the graphics controller 3 to draw in the task number register 9. The drawing address 14 generated by the graphics control unit 4 is divided into three parts: an area ID 15, a page ID 16, and an intra-page offset 17, and the first two are input to the TLB 8.

In the TLB 8, if there is address conversion information 6 that satisfies all of the following conditions, the drawing address is a hit, and the physical page number 18 of the corresponding conversion information is output. If address translation information 6 that satisfies the condition does not exist, a miss-hit signal 19 is output. (a) The value of the task number register 9 and the value of the task number field of TLB 8 are equal. Or the value of task number register 9 is 000H. Or the value of the task number field of TLB8 is 0FFFH. (b) The value of area ID15 of the drawing address is equal to the value of area ID field of TLB8. (c) The value of the page size flag is "0" and the value of page ID16 of the drawing address is equal to the value of the page ID field of TLB8. Or the value of the page size flag is "1".

[0044] If there is a hit, the page size flag is set to "
0'', the physical address is obtained by combining the physical page number and the intra-page offset. The page size flag is "1"
'', the page ID and intra-page offset are added to the physical page number to obtain the physical address. For example, T.L.B.
In the state shown in Figure 6, the drawing address is 301234.
In the case of H, the page size flag of the corresponding address translation information is "0", so the physical page number (356H)
3562, which is the combination of and in-page offset (234H)
34H becomes the physical address. On the other hand, the drawing address is 6
In the case of 54321H, the page size flag of the corresponding address translation information is "1", so the physical page number (
D54321H, which is a combination of page ID (54H) and intra-page offset (321H), becomes the physical address.

In the case of a mishit, the graphics controller 3 temporarily interrupts processing and sends a mishit signal 19.
The process is handed over to processor 1. processor 1
Now, read the task number and logical address that caused the miss from the graphics controller 3, refer to the table according to them, create address conversion information, set the access mode flag and page size flag, and use this information. Register to TLB8.

[0046] Although the task number may be arbitrarily determined,
000H and 0FFFH are used as special values. 000
H represents a privileged level task, and tasks with this value can access all logical address spaces. 0FFFFH
represents a common task area, and address translation information having this value can be addressed from all tasks.

Furthermore, even if the TLB hits a drawing address, the access is a write access,
If the R flag of the hit entry is "1", this is an unauthorized access. This is to prevent write access to areas that should not be changed, such as font information, or the ROM area. Whether the access is a read access or a write access is identified by the read/write signal 20 output by the graphics control unit 4.

Furthermore, as in the first embodiment, when a memory protection function is incorporated into the TLB configuration, the memory protection function managed by the OS is incorporated at the stage of registering address translation information to prevent unauthorized access. It is possible to prevent this. In this case, the graphics controller
After receiving a drawing instruction from the processor, it becomes possible to perform processing independently of the processor, so it is also possible for the processor and graphics controller to process different tasks at the same time.

Although the graphics controller has been explained in the above embodiments of the present invention, the purpose of the address translation device according to the present invention is to convert the logical addresses generated by the peripheral controller into physical addresses to convert virtual memory. The goal is to allow controlled access to memory. From this, it is clear that the present invention is applicable not only to graphics controllers but also to peripheral controllers that need to access virtualized memory, such as DMA controllers, communication controllers, and disk controllers.

[0050]

[Effects of the Invention] As explained above, the present invention is capable of converting logical addresses and physical addresses in a graphics controller as a peripheral controller, and configures a graphics system compatible with virtual memory. There is an effect that can be done.

Furthermore, in the graphics controller address translation device according to the present invention, a slight hardware addition is required in which only the TLB, which is a part of the MMU, is built into the graphics controller, and other processing is performed by the OS. , can convert logical addresses and physical addresses at high speed with a high degree of freedom, and can also support multiple accesses, prevent unauthorized access, and reduce the number of address conversion information.
The effect is huge.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the structure of the address translation information.

FIG. 3 is an explanatory diagram showing a memory map based on the virtual memory.

FIG. 4 is a block configuration diagram showing a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing the structure of the address translation information.

FIG. 6 is an explanatory diagram showing a memory map based on the virtual memory.

FIG. 7 is a block configuration diagram showing a conventional example.

[Explanation of symbols]

1, 31 Processor 2, 32 Memory 3 Graphics controller 4 Graphics control unit 5, 6
Address conversion information 7, 8, 37 Translation reference buffer (TLB) 9 Task number register (TR) 10 System address bus 11 System data bus 12 Graphics address bus 13 Graphics data bus 14 Drawing address 15 Area ID 16 Page ID 17 Page Internal offset 18 Physical page numbers 19, 38 Mishit signal 20 Read/write signal 21 Drawing address generator (AG) 33 Logical address 34 Physical address 35 Area table 36 Page table

Claims (2)

[Claims] 1. A logical address generation means for generating logical address information based on data input from a processor, and a conversion reference buffer for converting the generated logical address information into physical address information and outputting it to a memory. In the address translation device, the translation reference buffer is configured by combining a plurality of pieces of address translation information configured to store the logical address information and the physical address information as a set, and the translation reference buffer is configured by combining a plurality of pieces of address translation information configured to store the logical address information and the physical address information as a set, and When one suitable piece of address translation information is selected from among the plurality of address translation information and the physical address information included in the address translation information is output to the memory, and the matching address translation information cannot be selected. An address translation device comprising means for outputting a mishit signal to the processor. 2. The address translation device according to claim 1, wherein the translation reference buffer includes, as the address translation information, control information for controlling translation processing in addition to the logical address information and the physical address information. An address translation device comprising processing means for this control information.