JPH0430757B2 - - Google Patents
Info
- Publication number
- JPH0430757B2 JPH0430757B2 JP15783183A JP15783183A JPH0430757B2 JP H0430757 B2 JPH0430757 B2 JP H0430757B2 JP 15783183 A JP15783183 A JP 15783183A JP 15783183 A JP15783183 A JP 15783183A JP H0430757 B2 JPH0430757 B2 JP H0430757B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ingaasp
- inp
- temperature
- surface layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
- H01S5/04252—Electrodes, e.g. characterised by the structure characterised by the material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/3235—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength longer than 1000 nm, e.g. InP-based 1300 nm and 1500 nm lasers
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、InGaAsP／InP半導体装置に係り、
特に電極との合金化反応に対し安定でありかつ信
頼性の向上をはかろうとするものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an InGaAsP/InP semiconductor device,
In particular, it is intended to be stable against alloying reactions with electrodes and to improve reliability.
〔発明の背景〕
従来、InGaAsPを用いた半導体装置の表面層
は、InGaAsPの組成の等しい一層から構成され
ていたために、電極等金属（主にAu）との反応
が生じる場合には、InGaAsとInPの界面にまで
金属が達し、素子の信頼性を損うという欠点があ
つた。[Background of the Invention] Conventionally, the surface layer of a semiconductor device using InGaAsP was composed of a single layer of InGaAsP with the same composition, so when a reaction occurs with metals such as electrodes (mainly Au), the InGaAs and The drawback was that the metal reached the InP interface, impairing the reliability of the device.
更にはInGaAsP／InP材料へのオーム接触の形
成方法も明確でなく、温度が低すぎる場合には、
接触抵抗の増大、高すぎる場合には、結晶中に非
発光センタの導入を招き、素子の信頼性を損うと
いう欠点があつた。 Furthermore, it is not clear how to form ohmic contacts to InGaAsP/InP materials, and if the temperature is too low,
There is a drawback that the contact resistance increases, or if it is too high, non-luminescent centers are introduced into the crystal, impairing the reliability of the device.
本発明の第１の目的は電極の形成に当つても信
頼度の高いInGaAsP系半導体装置を提供するに
ある。即ち、電極と結晶体との反応を当該結晶体
の表面第１層で止め、且つ合金化反応による結晶
体内への転位の発生をも防止せんとするものであ
る。
A first object of the present invention is to provide an InGaAsP semiconductor device that is highly reliable even when forming electrodes. That is, the purpose is to stop the reaction between the electrode and the crystal body at the first layer on the surface of the crystal body, and also to prevent the generation of dislocations into the crystal body due to the alloying reaction.
本発明の別の目的は安定で信頼性の高いオーム
性電極を有するInGaAsP系半導体装置を提供す
るにある。 Another object of the present invention is to provide an InGaAsP semiconductor device having a stable and highly reliable ohmic electrode.
本発明の半導体装置の基本構成は次の通りであ
る。
The basic configuration of the semiconductor device of the present invention is as follows.
所定の基板上に半導体層の積層体を有する半導
体装置であつて、その表面層が前記基板側から
In1-x′Gax′Asy′P1-y′およびIn1-xGaxAsyP1-yの
二層を少なくとも有し、且ｘ＞x′≠０なる関係を
有せしめる。 A semiconductor device having a stack of semiconductor layers on a predetermined substrate, the surface layer of which is formed from the substrate side.
It has at least two layers of In 1-x ′Gax′As y ′P 1-y ′ and In 1-x GaxAs y P 1-y , and has the relationship x>x′≠0.
ｘ＞x′＋0.05に選択するのがより好ましい。 It is more preferable to select x>x′+0.05.
InGaAsP結晶体にCr−Auの積層膜を用いて、
オーム性電極を得ようとする場合、結晶体からの
InやGaの外拡散が伴つた。この外拡散の生じる
温度はInとGaの組成比に依存するため、この組
成比を所定に選択することによつて、結晶体の表
面第１層のみ外拡散し、表面第２層は金属との反
応が生じない様にすることができる。 Using a Cr-Au laminated film on an InGaAsP crystal,
When trying to obtain an ohmic electrode,
This was accompanied by outward diffusion of In and Ga. The temperature at which this out-diffusion occurs depends on the composition ratio of In and Ga, so by selecting this composition ratio, only the first layer on the surface of the crystal will diffuse out, and the second layer on the surface will be made of metal. It is possible to prevent this reaction from occurring.
更に表面第２層がInP層である場合、InPは
InGaAsPに比較してパイエルス力が小さいため、
当該結晶体に転位が入りやすい。そこで表面第２
層として、InPよりもパイエルス力の大きな材
料、たとえばInGaAs層を用いることによつて、
表面第１層で生じた合金化によつて加わる応力が
緩和され、基板側への転位の進行を防ぐことがで
きる。 Furthermore, when the second surface layer is an InP layer, the InP is
Because the Peierls force is smaller than InGaAsP,
Dislocations are likely to enter the crystalline body. Therefore, the second surface
By using a material with a larger Peierls force than InP as a layer, such as an InGaAs layer,
The stress applied due to the alloying generated in the first surface layer is relaxed, and it is possible to prevent dislocations from progressing toward the substrate side.
同時に、たとえばCr−Au積層膜で当該結晶体
にオーム性電極を形成する場合、所定の表面層の
みに外拡散が生じる温度かつ、その表面層以下の
層（たとえばInP層）では外拡散の生じぬ温度で
熱処理することが好ましい。 At the same time, when forming an ohmic electrode on the crystal using, for example, a Cr-Au laminated film, the temperature is such that out-diffusion occurs only in a predetermined surface layer, and out-diffusion occurs in layers below that surface layer (for example, an InP layer). It is preferable to perform the heat treatment at a temperature below
また、In1-xGaxAsyP1-y層を表面層として有す
る化合物半導体材料積層体にAuを主体とする金
属をオーム性電極として形成するに当つては下記
条件で熱処理することが好ましい。 Furthermore, when forming a metal mainly composed of Au as an ohmic electrode on a compound semiconductor material laminate having an In 1-x GaxAs y P 1-y layer as a surface layer, it is preferable to perform heat treatment under the following conditions.
熱処理温度をＴ（℃）とすると、 350−90x＜Ｔ＜370（℃） 但し、ｘはGaのモル比である。 If the heat treatment temperature is T (°C), 350−90x＜T＜370(℃) However, x is the molar ratio of Ga.
の範囲内で行なう。Perform within the range of.
より好ましくは350℃以下が良い。 More preferably, the temperature is 350°C or less.
〔発明の実施例〕
以下、本発明の一実施例を図を用いて説明す
る。[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.
第１図は、、従来のInGaAsP／InPレーザの構
造模式断面図である。レーザ用結晶は、ｎ型InP
基板１上に、InGaAsP活性層２、ｐ型InPクラツ
ド層３、InGaAsP表面層４から成る。これに対
し、本発明では、第２図に示す如く表面層を２つ
の組成の異なる部分、即ち、ｘ＝0.25、ｙ＝2.2x
なる第１の表面In1-xGaxAsyP1-y層４１と、x′＝
0.15（ｙび＝2.2x′）なる第２の表面In1-x′
Gax′Asy′P1-y′層４２と分けたことが特徴であ
る。上述の構造体にAu／Cr積層体から成る電極
金属を蒸着し（Auが表面側）、温度330℃で熱処
理を行うと、良好なオーム接触が得られる。温度
330℃で30分間熱処理を行うと、第１の表面層に
はAuの反応が見られるものの、第２の表面層は
安定であつた。 FIG. 1 is a schematic cross-sectional view of the structure of a conventional InGaAsP/InP laser. Laser crystal is n-type InP
It consists of an InGaAsP active layer 2, a p-type InP cladding layer 3, and an InGaAsP surface layer 4 on a substrate 1. On the other hand, in the present invention, as shown in FIG.
The first surface In 1-x GaxAs y P 1-y layer 41 and x′=
The second surface In 1-x ′ is 0.15 (y = 2.2x′)
It is characterized by being separated from the Gax′As y ′P 1-y ′ layer 42. If an electrode metal consisting of an Au/Cr laminate is deposited on the above structure (Au on the surface side) and heat treated at a temperature of 330°C, good ohmic contact can be obtained. temperature
When heat-treated at 330° C. for 30 minutes, reaction of Au was observed in the first surface layer, but the second surface layer remained stable.
第３図はInGaAsPのAuとの反応開始温度をGa
のモル比に対し、打点したものである。Gaのモ
ル比が高い程、反応開始温度が下がり、反応温度
Ｔは、
Ｔ350−90x（℃）
に従つた。 Figure 3 shows the temperature at which InGaAsP starts reacting with Au.
The dots are plotted against the molar ratio of . The higher the molar ratio of Ga, the lower the reaction initiation temperature, and the reaction temperature T followed T350-90x (°C).
従つて、Δx＝ｘ−x′を0.05以上に選ぶことよ
り、反応温度にほぼ4.5℃の差が生じ、制御可能
な範囲で、、熱処理温度の制御が可能となつた。 Therefore, by selecting Δx=x−x′ to be 0.05 or more, a difference of about 4.5° C. was generated in the reaction temperature, and it became possible to control the heat treatment temperature within a controllable range.
表面第２層を四元層とすることにより、表面第
１層で生じた合金化によつて入る応力が、InPよ
りもパイエルス力の大きな四元層で緩和され、基
板側への転位の進行を防ぐことができた。 By making the second surface layer a quaternary layer, the stress introduced by alloying that occurs in the first surface layer is alleviated by the quaternary layer, which has a larger Peierls force than InP, and prevents the progression of dislocations toward the substrate. could be prevented.
第４図に半導体レーザのプロセス工程を示す。
実施例では、このプロセスの中で、本発明をｐ型
電極の形成に適用した例である。第２図に示す様
に、ｐ型電極は、表面から見て、Au、Crの２層
膜を真空中で蒸着することで形成した。この後、
接触抵抗が10-4Ω・cm2以下の良好なオーム性を示
すように、H2或はN2中で熱処理を行つた。 FIG. 4 shows the process steps for a semiconductor laser.
In this example, the present invention is applied to the formation of a p-type electrode in this process. As shown in FIG. 2, the p-type electrode was formed by depositing a two-layer film of Au and Cr in vacuum when viewed from the surface. After this,
Heat treatment was performed in H 2 or N 2 so that the contact resistance showed good ohmic properties of 10 −4 Ω·cm 2 or less.
表面層In1-xGaxAsyP1-yの組成が、ｙ＝0.35（ｙ
＝2.2x）について熱処理を行い、Ｉ−Ｖ特性の変
化を見た結果を第５図に示す。これによればＴ〜
350℃以上の熱処理によつて素子のＩ−Ｖ特性に
再結合電流の増大が見られ、素子劣化が生じるこ
とがわかつた。また、320℃以下の熱処理では、
接触抵抗が高いという問題があつた。 The composition of the surface layer In 1-x GaxAs y P 1-y is y=0.35 (y
Figure 5 shows the results of the heat treatment and the changes in the IV characteristics. According to this, T~
It was found that heat treatment at 350° C. or higher causes an increase in recombination current in the IV characteristics of the device, leading to device deterioration. In addition, heat treatment below 320℃
There was a problem with high contact resistance.
InP、InGaAsP，GaAsについてAuとの反応を
調べた結果、ほぼ、In、Gaの組成比に従い反応
が生じており、InGaAsPがAuと反応し、InPが
Auと反応しない温度、ｘ＝0.25の場合には例え
ば340℃の熱処理で良好なオーム接触を有する素
子が得られた。なお熱処理時間は10〜30分間で熱
処理を行つた。 As a result of investigating the reaction of InP, InGaAsP, and GaAs with Au, the reaction occurred almost according to the composition ratio of In and Ga, with InGaAsP reacting with Au and InP reacting with Au.
In the case of x=0.25, which is a temperature at which no reaction occurs with Au, an element having good ohmic contact was obtained by heat treatment at 340° C., for example. The heat treatment time was 10 to 30 minutes.
なお、電極の反応の程度が軽微である場合に
は、大電流素子である半導体レーザでは、初期特
性上問題は少ない。この様な場合には、360℃，
370℃の温度においても、素子作製は可能であつ
た。 Note that if the degree of reaction of the electrode is slight, there are few problems in terms of initial characteristics in a semiconductor laser which is a large current element. In such cases, 360℃,
Device fabrication was possible even at a temperature of 370°C.
InGaAsP／InPの信頼性の高く、安定なオーム
接触が得られる条件が明確となつた。
The conditions for obtaining highly reliable and stable ohmic contact with InGaAsP/InP have been clarified.
この結果、再現性良く、信頼性の高い半導体レ
ーザ素子が得られた。 As a result, a semiconductor laser device with good reproducibility and high reliability was obtained.
この発明は、レーザのみならず、LED、APD
等、他の発光デバイス、InP系FET等の高速デバ
イスにも適用が可能である。 This invention is applicable not only to lasers but also to LEDs, APDs, etc.
It can also be applied to other light-emitting devices, such as InP-based FETs, and other high-speed devices.
第１図は従来の半導体レーザ装置の断面図、第
２図は本発明の半導体レーザ装置の断面図、第３
図はAu−InGaAsP系の反応温度とGaモル比の関
係を示す図、第４図は半導体レーザの製造工程を
示す図、第５図は半導体レーザの電流−電圧特性
を示す図である。
１…InP基板、２…InGaAsP活性層、３…InP
クラツド層、４…InGaAsP表面層、４１…
InGaAsP第１表面層、４２…InGaAsP第２表面
層。
FIG. 1 is a sectional view of a conventional semiconductor laser device, FIG. 2 is a sectional view of a semiconductor laser device of the present invention, and FIG.
The figure shows the relationship between reaction temperature and Ga molar ratio in the Au-InGaAsP system, FIG. 4 shows the manufacturing process of a semiconductor laser, and FIG. 5 shows the current-voltage characteristics of the semiconductor laser. 1...InP substrate, 2...InGaAsP active layer, 3...InP
Cladding layer, 4...InGaAsP surface layer, 41...
InGaAsP first surface layer, 42...InGaAsP second surface layer.
Claims (1)
なくとも有する半導体装置において、少なくとも
当該金属層下のInGaAsP層は該金属層側より
In1-xGaxAsyP1-yおよびIn1-x′Gax′Asy′P1-y′
（但し、ｘ＞x′≠０）の二層を少なくとも有する
ことを特徴とする半導体装置。 ２ 特許請求の範囲第１項記載の半導体装置にお
いて、ｘ＞x′＋0.05なることを特徴とする半導体
装置。[Claims] 1. In a semiconductor device having at least a region in which a metal layer is formed on an InGaAsP layer, at least the InGaAsP layer below the metal layer is formed from the metal layer side.
In 1-x GaxAs y P 1-y and In 1-x ′Gax′As y ′P 1-y ′
A semiconductor device comprising at least two layers (where x>x'≠0). 2. A semiconductor device according to claim 1, characterized in that x>x'+0.05.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157831A JPS6050981A (en) | 1983-08-31 | 1983-08-31 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157831A JPS6050981A (en) | 1983-08-31 | 1983-08-31 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6050981A JPS6050981A (en) | 1985-03-22 |
| JPH0430757B2 true JPH0430757B2 (en) | 1992-05-22 |
Family
ID=15658278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58157831A Granted JPS6050981A (en) | 1983-08-31 | 1983-08-31 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6050981A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2594032B2 (en) * | 1985-08-08 | 1997-03-26 | 三洋電機株式会社 | Light emitting element |
-
1983
- 1983-08-31 JP JP58157831A patent/JPS6050981A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6050981A (en) | 1985-03-22 |
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