JPH0430575A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify the peripheral circuits of cells by comprising a depletion type insulated gate type transistor of which drain and source are connected between control gate and selection gate. CONSTITUTION:A power supply voltage Vcc is applied to a control gate 46 of cell transistor ST and it is also applied to the gate of the depletion type transistor DT. Thereby, the power supply voltage Vcc is transferred to the selection gate 48 of the cell transistor ST through the depletion type transistor DT. Moreover, a read voltage is applied to the drain 42 of the cell transistor ST. In addition, a write voltage Vpp is applied to the control gate 46 of the cell transistor ST and OV is applied to the gate of depletion type transistor DT. Thereby, a voltage of about 2V is transferred to the selection gate 48 of the cell transistor ST through the depletion type transistor DT. Moreover, the power supply voltage Vcc is applied to the drarin 42 of the cell transistor ST.

Description

Detailed Description of the Invention [Objective of the Invention (Industrial Field of Application) The present invention relates to a semiconductor integrated circuit, and particularly to a selection gate formed on the side wall of a control gate and a floating gate with a side insulating film interposed therebetween. The present invention relates to a nonvolatile memory cell having a nonvolatile memory cell and a nonvolatile semiconductor memory using the same.

(Prior Art) Recently, as a type of EEFROM (electrically erasable and rewritable read-only memory) cell, a flash ΦEEFROM cell (Flash-EEPRO), which is suitable for bulk erasing, has been introduced.
M Ce1l ) has been proposed, and its cross-sectional structure is shown in FIG.

In FIG. 4, 41 is a semiconductor substrate of the first conductivity type, 42
and 43 are selectively provided on the surface of this semiconductor substrate 41, and are a first impurity region (drain) and a second impurity region (source) of a second conductivity type opposite to that of the semiconductor substrate 41.
, 44 is a first gate insulating film formed on the surface of the semiconductor substrate, and 45 is a first gate electrode (floating gate) provided between the drain and source on the semiconductor substrate via the first gate insulating film 44. ), 46 is a second gate electrode (control gate) provided on the floating gate via an interlayer insulating film 47; 48 is a second gate electrode (control gate) provided on the source side side wall of the floating gate 45 and control gate 46 via a side insulating film 49; Further, it is a third gate electrode (selection gate) provided on the semiconductor substrate with the second gate insulating film 50 interposed therebetween.

In this way, the EEPRO has a selection gate 48 on the source side.
An example of the applied voltage in each operation mode of the M cell is shown in the table below.

FIG. 5 shows the circuit connections of a part of the EEFROM cell array shown in FIG.
= M CMN are EEFROM cells arranged in matrix, Xo-Xd are control gate lines in the row direction, ZQ""'ZM
are selection gate lines in the row direction, BLO to BLN are bit lines in the column direction, C8o to C8N are column selection gates, yo-yN are column selection control lines, and D0 to D7 are data lines commonly connected to multiple columns ( sense line).

FIG. 6 shows a conventional E using the memory cell array of FIG.
A part of the circuit block of EFROM is shown. Here, 51 is a write intermediate potential generation circuit, 52 is a mode switching circuit, 53 is a mode setting signal generation circuit, 54 is a row deco/do circuit, 55 is a read intermediate potential generation circuit, 56 is a column decode circuit, and 57 is a It is a memory cell array.

In the conventional EEFROM as described above, when reading a selected EEFROM cell in the memory cell array 57, the same power supply voltage Vcc is applied to its selection gate and control gate, and its drain is connected to a sense line. Read intermediate potential generation circuit 5
A read voltage of 1V is applied through the column select gate selected from 5. At this time, the unselected EEFRO
For the M cell, Ov is applied to its selection gate and control gate, and no voltage is applied to its drain (floating state).

Furthermore, when writing (programming) a selected EEFROM cell, the intermediate potential (2V) generated by the write intermediate potential generation circuit 51 is applied to the selection gate, and the external power supply voltage or internal boost voltage is applied to the control gate. A write voltage Vpp (12V) is applied,
A power supply voltage Vcc (5V) is applied to its drain from the sense line via a selected column selection gate. At this time, OV is applied to the selection gate and control gate of the unselected EEFROM cell, and no voltage is applied to the drain.

Furthermore, when erasing an EEPROM cell in bulk, for example, 0 is applied to its selection gate and control gate, and a write voltage Vl) is applied to its drain from the sense line via the column selection gate.

As mentioned above, in the conventional EEFROM, the voltage applied to the selection gate of the selected EEFROM cell is 5V during read/write/erase.
It is necessary to use three different voltages such as /2V and 10V, and a write intermediate potential generation circuit 51 is required. It was necessary to provide the decode circuit 54 with two output circuits: a control gate output circuit and a selection gate output circuit. Therefore, EEFROM
The cell's peripheral circuitry was becoming more complex.

(Issue 8 to be solved by the invention) As mentioned above, in the conventional EEFROM, three types of voltage including an intermediate potential must be used as the voltage applied to the selection gate of the EEPROM cell, which makes the peripheral circuit complicated. There is a problem.

The present invention has been made to solve the above-mentioned problems, and its purpose is to eliminate the need for a special circuit that generates an intermediate potential for writing to a nonvolatile memory cell, and to eliminate the need for a special circuit that generates an intermediate potential for writing to a nonvolatile memory cell. It is an object of the present invention to provide a semiconductor integrated circuit that can easily supply a necessary bias state at times and simplify cell peripheral circuits.

[Configuration of the Invention] (Means for Solving the Problems) A semiconductor integrated circuit of the present invention includes a drain and a source,
a floating gate and a control gate, a selection gate provided on side walls of the floating gate and control gate with a side insulating film interposed therebetween, and on a semiconductor substrate with a gate insulating film interposed therebetween;
The present invention is characterized in that it has a nonvolatile memory cell including a depletion type insulated gate transistor whose drain and source are connected between the control gate and the selection gate.

Further, the semiconductor integrated circuit of the present invention includes a drain and a source, a floating gate and a control gate, a side insulating film on the side walls of the floating gate and the control gate, and a gate insulating film on the semiconductor substrate. It has a memory cell array in which non-volatile memory cells are arranged in rows and columns, each having a selection gate provided therein.
It is characterized by comprising depletion type insulated gate transistors whose sources are connected between the control gate line and the selection gate line of each row, and whose gates are commonly connected.

(Function) According to the nonvolatile memory cell provided in the semiconductor integrated circuit of the present invention, the gate voltage of the depletion type transistor is changed to the power supply voltage V ccloVloV (no intermediate potential required) in response to reading/writing/erasing of the cell transistor. ), the control gate voltage of the cell transistor is transmitted to the selection gate via the depletion type transistor, and a desired voltage is applied to the selection gate.

That is, when reading out the cell transistor,
A power supply voltage Vec is applied to the control gate, a power supply voltage Vcc is applied to the gate of the depletion type transistor, the power supply voltage Vcc is transmitted to the selection gate through this depletion type transistor, and a read voltage is applied to its drain.

In addition, when writing to a cell transistor, a write voltage vpp is applied to its control gate, Ov is applied to the gate of a depletion type transistor, approximately 2V is transmitted to the selection gate through this depletion type transistor, and the power supply voltage is applied to its drain. Vcc is applied.

Furthermore, when erasing a cell transistor, Ov is applied to its control gate, Ov is applied to the gate of the depletion type transistor, OV is transmitted to the selection gate through this depletion type transistor, and the write voltage vpp is applied to its drain. applied.

Therefore, there is no need for a special circuit to generate an intermediate potential for writing to the nonvolatile memory cell, and it is possible to easily supply the necessary bias state when reading and writing to the cell. , it becomes possible to simplify the cell peripheral circuitry.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit of an EEPROM cell used for storing, for example, a 1-bit flag in a semiconductor integrated circuit. This EEFROM cell has a drain 42 and a source 4 similar to the EEPROM cell described above with reference to FIG.
3. In addition to the cell transistor ST having a floating gate 45, a control gate 46, and a selection gate 48,
A MOS type depletion type (normally on type) transistor DT is provided between the control gate 46 and the selection gate 48, the drain and source of which are connected.

The structure of this EEPROM cell is such that on a semiconductor substrate on which a cell transistor ST having a structure similar to that of the EEFROM cell described above with reference to FIG.
A third impurity region (drain) and a fourth impurity region (source) of conductivity type are provided, and the third impurity region (drain) and fourth impurity region (source) are formed on the semiconductor substrate.
A fifth gate electrode (gate) capable of controlling the channel resistance between the two electrodes is provided with a third gate insulating film interposed therebetween.

The third impurity region (drain) and the fourth impurity region (source) are electrically connected to the second gate electrode (control gate 46) and third gate electrode (selection gate 48). In this case, the third impurity region (
(drain), a fourth impurity region (source), and a fifth gate electrode (gate) are formed to form a depletion type transistor DT.

When reading from the EEFROM cell, the control gate 461 of the cell transistor ST is connected to the power supply voltage V
cc is applied, and the dable solution type transistor D
A power supply voltage Vce is strongly applied to the gate of T. As a result, the power supply voltage Vce is transmitted to the select gate 48 of the cell transistor ST through the dable solution transistor DT. Also, a read voltage (approximately IV) is applied to the drain 42 of the cell transistor ST.

Furthermore, writing to the EEPROM cell (at this time, a write voltage Vpp is applied to the cell control gate 46 of the cell transistor ST, and a voltage Vpp is applied to the gate 1 of the dablenation type transistor DT. As a result, selection gate 4 of cell transistor ST
Approximately 2V is transmitted to 8 through the dable solution type transistor DT. Further, the drain 42 of the cell transistor ST is supplied with the power supply voltage Vcc.

In addition, during the operation of the EEPROM cell, a voltage of 0 is applied to the control gate 46 of the cell transistor ST and the gate of the dable solution transistor DT, and to the drain 42 of the cell transistor ST,
A write voltage vpp is applied. As a result, electrons are erased from the floating gate 45 of the cell transistor ST.

According to the EEPROM cell described above, by simply setting the gate voltage of the depletion type transistor DT to the power supply voltage Vcc10V10V in response to read/write/erase of the cell transistor ST, the cell transistor S
The voltage on the control gate 46 of T is transmitted to the selection gate 48 via the depletion type transistor DT, and a desired voltage is applied to the selection gate 48. Therefore, it is possible to supply the bias state necessary for reading and writing to the EEFROM cell without requiring a special circuit that generates an intermediate potential for writing. This makes it possible to simplify the peripheral circuitry of the device.

FIG. 2 shows a part of a circuit block of an EEPROM according to an embodiment of the present invention, and FIG. 3 shows a part of the memory cell array in FIG. 2 and its circuit connections.

The EEPROM shown in FIG. 2 differs from the conventional EEFROM described above with reference to FIG. 6 in that the write intermediate potential generation circuit is omitted, and the driving method (voltage supply The same reference numerals as in FIG. 6 are given to corresponding parts as in FIG. 6. The memory cell array 57'' is configured as shown in FIG.
Compared to the conventional memory cell array 57 described above with reference to the figure, one depletion type transistor DT is provided in each row of the memory cell array 57', and the drain and source of the depression type transistor DT in each row is The gate is connected between the control gate line and the selection gate line of each row, and is commonly connected to the gate of the davation type transistor DT of each row or to the gate input line 2, and the gate input line 2 is connected to the power supply. Voltage Vcc/O
The difference is that a circuit for switching and supplying V is provided, and the rest is the same, so the same reference numerals as in FIG. 5 are given.

In the EEFROM as described above, a selected EEFROM cell (for example, MC0) in the memory cell array 57°
When reading pressure for N), the control gate line X of the selected row. The power supply voltage VCC is applied to the gates of the depletion type transistors DT in each row through the gate input line 2. As a result, the power supply voltage Vec is transmitted to the selection gate of the EEFROM cell in the selected row through the depletion type transistor DT. Also, the E of the selected column
The sense line read voltage (approximately IV) is connected to the drain of the EFROM cell by the column selection gate C8N and the bit line B.
It is applied via LN. At this time, 0■ is applied to the control gate lines (other than Xo) of the unselected rows, and this Ov is transmitted to the selection gate lines (other than zo) of the unselected rows through the depletion type transistor DT, and the column selection of the unselected columns is performed. No voltage is applied to the drains connected to the gates (other than C8N) and bit lines (other than BLN).

Therefore, reading is performed from the selected EEFROM cell MC0N, and reading from the other unselected EEFROM cells MC0N is performed.
No reading is performed from the M cell.

In addition, the selected EEFR in the memory cell array 57''
When writing to an OM cell (for example, MC0N), a write voltage Vpp is applied to the control gate line x0 of the selected row.
(12V) is applied to the gates of the depletion type transistors DT in each row through the gate input line 2.
or is applied. This will cause the selected row's EEPR
Approximately 2V is transmitted to the selection gate of the OM cell through the depletion type transistor DT. In addition, the drain of the EEPROM cell in the selected column is connected to the power supply voltage Vcc.
(5V) is applied from the sense line through the column select gate C3N and the bit line B L N.

At this time, the control gate lines (other than Xo) of unselected rows are
is applied, and this Ov is transmitted to the selection gate line (other than Zo) of the unselected row through the depletion type transistor DT, and is connected to the column selection gate line (other than C5N) of the unselected column and the bit line (other than BLN). No voltage is applied to the drain. Therefore, the selected EEPR
Writing is performed to the OM cell M CON, and no writing is performed to other unselected EEPROM cells.

All EEFROMs in the memory cell array 57''
When erasing cells (-batch erasing), the gate power line 2 and the control gate line X of each row. -xM is applied with OV, a write voltage Vpp is applied to the column selection control line Y o -YN and the sense line, and the EEFROM of each column is
A column selection gate C8 is connected to the drain of the cell from the sense line.
Write voltage Vpp is applied via o to C3N and bit lines BLo to BLN. Therefore, all selected E
Electrons are erased from the floating gate of the EFROM cell.

In addition, some EEPROMs in the memory cell array 57''
When erasing cells (for example, byte erasing), column selection gates C80 to C8N and bit lines BL
A switching transistor (not shown) is inserted between the gate input line 2 and the control gate line X of each row. Ov is applied to -xM, and write voltage Vl is applied to column selection control line Yo-YN and sense line.
) l) is applied, some of the switching transistors (not shown) are selected, and the drain of the EEPROM cell in the selected column is thereby written from the sense line through the column selection gate and the bit line. A voltage vpp is applied. Therefore, electrons are erased from the floating gates of the EEPROM cells in the selected column.

According to the EEPROM as described above, row decoding during reading and writing only needs to be performed on the control gate of the cell transistor ST.

In addition, in response to reading/writing of the EEFROM cell in the selected row, the gate voltage of the depletion type transistor DT in the selected row is set to the power supply voltage Vcc/OV.
By simply doing so, the control gate voltage of the cell transistor ST is transmitted to the selection gate via the depletion type transistor DT, and a desired voltage is applied to the selection gate.

Therefore, there is no need for a special circuit that generates an intermediate potential for writing, and it is possible to easily supply the bias state necessary for reading and writing to EEFROM cells, such as row decoding circuits, etc. This makes it possible to simplify the cell peripheral circuitry.

[Effects of the Invention] As described above, according to the semiconductor integrated circuit of the present invention, there is no need for a special circuit that generates an intermediate potential for writing to a nonvolatile memory cell, and moreover, there is no need for a special circuit that generates an intermediate potential for writing to a nonvolatile memory cell, and moreover, It becomes possible to easily supply the necessary bias state to the cells, and it is possible to simplify the cell peripheral circuitry.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a nonvolatile memory cell provided in a semiconductor integrated circuit of the present invention, and FIG. 2 is a block circuit diagram showing an EEPROM according to an embodiment of the semiconductor integrated circuit of the present invention. , FIG. 3 is a circuit diagram showing a part of the memory cell array in FIG. 2, FIG. 4 is a cross-sectional view showing a conventional EEFROM cell, and FIG. 5 shows a part of the EEFROM cell array in FIG. 4. Circuit Diagram: FIG. 6 is a professional circuit diagram showing a conventional EEFROM using the memory cell array of FIG. 42... Drain of cell transistor, 43... Source of cell transistor, 44... First gate insulating film of cell transistor, 45... First gate electrode (floating gate) of cell transistor, 46...・Second gate electrode (control gate) of cell transistor, 48...Third gate electrode (selection gate) of cell transistor, 49・
... Side insulating film of cell transistor, 50... Second gate insulating film of cell transistor, 52... Mode switching circuit, 53... Mode setting signal generation circuit, 54.
...Row decode circuit, 55...Read intermediate potential generation circuit, 56...Column decode circuit, 57"...Memory cell array, MC0°~MCMN...EEPROM cell, x0~XM...Control gate line , zo-zM...Selection gate line, 2...Gate input line, B Lo'=B
LN'' bit line, CS o ~ CS N - column selection gate, yo-yN... column selection control line, D0 ~ D7
...data line (sense line), ST...cell transistor, DT...depression type (normally)
・On type) transistor.

Claims (2)

[Claims] (1) A drain and a source, a floating gate and a control gate, and a selection gate provided on the side walls of the floating gate and control gate with a side insulating film interposed therebetween and on a semiconductor substrate with a gate insulating film interposed therebetween; A semiconductor integrated circuit comprising a nonvolatile memory cell comprising a depletion type insulated gate transistor whose drain and source are connected between the control gate and the selection gate. (2) A drain and a source, a floating gate and a control gate, and a selection gate provided on the side walls of the floating gate and control gate via a side insulating film and on the semiconductor substrate via a gate insulating film. The memory cell array has a memory cell array in which nonvolatile memory cells are arranged in rows and columns, and one memory cell array is provided in each row of the memory cell array, and the control gate line and the selection gate line of each row are connected between the drain and source of each memory cell array. What is claimed is: 1. A semiconductor integrated circuit comprising a depletion type insulated gate transistor connected between the transistors and the respective gates of which are connected in common.