JPH04304645A - Method for mounting semiconductor element - Google Patents
Method for mounting semiconductor elementInfo
- Publication number
- JPH04304645A JPH04304645A JP6866791A JP6866791A JPH04304645A JP H04304645 A JPH04304645 A JP H04304645A JP 6866791 A JP6866791 A JP 6866791A JP 6866791 A JP6866791 A JP 6866791A JP H04304645 A JPH04304645 A JP H04304645A
- Authority
- JP
- Japan
- Prior art keywords
- conductive filler
- circuit board
- semiconductor element
- recess
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000011231 conductive filler Substances 0.000 claims abstract description 40
- 239000000853 adhesive Substances 0.000 claims abstract description 24
- 230000001070 adhesive effect Effects 0.000 claims abstract description 24
- 239000004020 conductor Substances 0.000 claims 1
- 239000000945 filler Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は回路基板上への半導体素
子(IC)の実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a semiconductor element (IC) on a circuit board.
【0002】0002
【従来の技術】従来、このような分野の技術としては、
例えば、特開昭62−244142号に記載されるよう
なものがあった。図4はかかる従来の半導体素子の実装
断面図である。この図に示すように、1はICチップと
の電気的接続をとるためのITO電極2が形成されたガ
ラス基板、3はICチップとガラス基板1とを固定接着
するための接着剤、4はICチップとITO電極2との
電気的接続に寄与し接着剤中に含まれる導電性フィラー
であり、ここで、接着剤3と導電性フィラー4とで異方
性導電接着剤5を構成している。6はICチップ、7は
ICチップ6上に形成されたAl電極、8はAl電極上
に形成されたAuバンプ、9はICチップ上の回路配線
を、例えば、湿度等から保護し、また、外部との電気的
接触を防ぐための絶縁層である。[Prior Art] Conventionally, technologies in this field include:
For example, there was one described in Japanese Patent Application Laid-Open No. 62-244142. FIG. 4 is a cross-sectional view of such a conventional semiconductor device. As shown in this figure, 1 is a glass substrate on which an ITO electrode 2 is formed for electrical connection with the IC chip, 3 is an adhesive for fixing the IC chip and the glass substrate 1, and 4 is an adhesive. It is a conductive filler contained in the adhesive that contributes to the electrical connection between the IC chip and the ITO electrode 2. Here, the adhesive 3 and the conductive filler 4 constitute the anisotropic conductive adhesive 5. There is. 6 is an IC chip, 7 is an Al electrode formed on the IC chip 6, 8 is an Au bump formed on the Al electrode, 9 is for protecting the circuit wiring on the IC chip from humidity, etc.; This is an insulating layer to prevent electrical contact with the outside.
【0003】以上のような半導体素子の実装工程を図3
を参照しながら説明する。まず、図3(a)に示すよう
に、ガラス基板からなる回路基板1上に異方性導電接着
剤5を形成する。通常この工程は、予め所定の分散量で
分散された導電性フィラー4含んだ異方性導電接着剤5
を回路基板1上に仮接着させる。次いで、図3(b)に
示すように、回路基板1上へAuバンプ8が形成された
ICチップ6を位置合わせする。FIG. 3 shows the mounting process of the semiconductor element as described above.
This will be explained with reference to. First, as shown in FIG. 3(a), an anisotropic conductive adhesive 5 is formed on a circuit board 1 made of a glass substrate. Normally, this step involves an anisotropic conductive adhesive 5 containing a conductive filler 4 dispersed in a predetermined amount in advance.
is temporarily adhered onto the circuit board 1. Next, as shown in FIG. 3(b), the IC chip 6 on which the Au bumps 8 are formed is aligned onto the circuit board 1.
【0004】次に、図3(c)に示すように、ICチッ
プ6をツールにて加熱圧着し工程が完了する。Next, as shown in FIG. 3(c), the IC chip 6 is heat-pressed using a tool to complete the process.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記し
た従来の半導体素子の実装工程では、微細なICチップ
6の電極の接続において、電気的接続が行われたか否は
異方性導電接着剤5中に分散される導電性フィラー4の
分散量に左右されるという問題点があった。本発明は、
上記問題点を除去し、導電性フィラーを介して電気的接
続を行う半導体素子の実装方法において、電気的接続不
良をなくし、電気的接続の信頼性に優れた半導体素子の
実装方法を提供することを目的とする。[Problems to be Solved by the Invention] However, in the above-mentioned conventional semiconductor element mounting process, when connecting the electrodes of the minute IC chip 6, whether or not an electrical connection has been made is determined by the presence of the anisotropic conductive adhesive 5. There was a problem that it depended on the amount of conductive filler 4 to be dispersed. The present invention
To provide a method for mounting a semiconductor element which eliminates the above-mentioned problems, eliminates electrical connection defects, and has excellent electrical connection reliability in a semiconductor element mounting method in which electrical connection is made through a conductive filler. With the goal.
【0006】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するために、回路基板上への導電性フィラーを介した
半導体素子の実装方法において、回路基板上に凹部形状
をした電極部以外の部位に絶縁性膜を形成する工程と、
該凹部に導電性フィラーを入れる工程と、該導電性フィ
ラーが入った凹部に接着剤を入れる工程と、前記導電性
フィラーを介して半導体素子を回路基板上へ実装する工
程とを施すようにしたものである。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for mounting a semiconductor element onto a circuit board via a conductive filler, in which an electrode portion other than a concave-shaped electrode portion is formed on the circuit board. a step of forming an insulating film on the part;
The method includes a step of placing a conductive filler in the recess, a step of putting an adhesive into the recess containing the conductive filler, and a step of mounting the semiconductor element on the circuit board via the conductive filler. It is something.
【0007】また、回路基板上への導電性フィラーを介
した半導体素子の実装方法において、回路基板上の電極
部に凹部を形成する工程と、その形成された凹部に導電
性フィラーを入れる工程と、該凹部に接着剤を入れる工
程と、該導電性フィラーを介して回路基板上に半導体素
子を実装する工程とを施すようにしたものである。[0007] Furthermore, a method for mounting a semiconductor element on a circuit board via a conductive filler includes a step of forming a recess in an electrode portion on the circuit board, and a step of inserting a conductive filler into the formed recess. , a step of putting an adhesive into the recess, and a step of mounting a semiconductor element on the circuit board via the conductive filler.
【0008】[0008]
【作用】本発明によれば、電極部を凹部形状とし、その
中へ導電性フィラーと接着剤を入れ、導電性フィラーを
介して半導体素子を回路基板上へ実装するようにしたの
で、導電性フィラーを回路基板上の電極部(透明電極)
に集中することができ、半導体素子(ICチップ)の電
極部と回路基板の電極部間での導電性フィラーの逸脱に
よる電気的接続不良をなくすことができる。また、電極
間のショートを防ぐことができる。[Operation] According to the present invention, the electrode part is formed into a recessed part, a conductive filler and an adhesive are put in the recessed part, and the semiconductor element is mounted on the circuit board via the conductive filler. Place the filler on the electrode part (transparent electrode) on the circuit board.
It is possible to eliminate electrical connection failures due to deviation of the conductive filler between the electrode portions of the semiconductor element (IC chip) and the electrode portions of the circuit board. Furthermore, short circuits between electrodes can be prevented.
【0009】[0009]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例を示す半
導体素子の実装工程断面図である。まず、図1(a)に
示すように、透明電極11が形成された透明な回路基板
10上に、凹部13形状をした電極部以外の部位に、例
えば、SiO2 のような絶縁性透明膜12を数千Å〜
数μmの厚さで形成する。形成方法はスパッタ、P−C
VD等のような装置で成膜後、ホトリソによりパターン
形成してもよいし、厚膜印刷法のような方法で形成して
もよい。ここで、絶縁性透明膜12の膜厚をaとする。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device mounting process showing an embodiment of the present invention. First, as shown in FIG. 1A, on a transparent circuit board 10 on which a transparent electrode 11 is formed, an insulating transparent film 12 such as SiO several thousand Å~
It is formed with a thickness of several μm. Formation method is sputtering, P-C
After forming a film using a device such as VD, a pattern may be formed by photolithography, or a method such as a thick film printing method may be used. Here, the film thickness of the insulating transparent film 12 is assumed to be a.
【0010】次に、図1(b)に示すように、直径数千
Å〜数μmの導電性フィラー14を透明電極11と絶縁
性透明膜12によって形成された凹部13に入れる。こ
の時、絶縁性透明膜12の膜厚aは、凹部13に入れた
導電性フィラー14の高さbより小さい、つまりb>a
の関係を満たさなくてはならない。次いで、図1(c)
に示すように、透明電極11の凹部13の導電性フィラ
ー14上に紫外線硬化型接着剤15を入れる。Next, as shown in FIG. 1B, a conductive filler 14 having a diameter of several thousand Å to several μm is placed in the recess 13 formed by the transparent electrode 11 and the insulating transparent film 12. At this time, the thickness a of the insulating transparent film 12 is smaller than the height b of the conductive filler 14 placed in the recess 13, that is, b>a
must satisfy the following relationship. Next, Figure 1(c)
As shown in FIG. 2, an ultraviolet curing adhesive 15 is placed on the conductive filler 14 in the recess 13 of the transparent electrode 11.
【0011】次に、図1(d)に示すように、ICチッ
プ16と回路基板10を周知の方法にて位置合わせをし
、ICチップ電極17が紫外線硬化型接着剤15と導電
性フィラー14上にくるようにする。次いで、図1(e
)に示すように、加圧するとともに、回路基板10側の
光源18から紫外線を照射することにより、半導体素子
の実装工程が完了する。Next, as shown in FIG. 1(d), the IC chip 16 and the circuit board 10 are aligned using a well-known method, and the IC chip electrode 17 is bonded to the ultraviolet curing adhesive 15 and the conductive filler 14. Make sure it's on top. Next, Figure 1(e
), the semiconductor element mounting process is completed by applying pressure and irradiating ultraviolet light from the light source 18 on the circuit board 10 side.
【0012】このように構成することにより、図2に示
すように導電性フィラー14を介して、ICチップ電極
17と透明電極11とは確実な電気的接続を行うことが
でき、回路基板10上へのICチップ16の実装を行う
ことができる。次に、本発明の他の実施例について図を
参照しながら説明する。図5は本発明の他の実施例を示
す半導体素子の実装工程断面図である。With this configuration, the IC chip electrode 17 and the transparent electrode 11 can be reliably electrically connected through the conductive filler 14 as shown in FIG. The IC chip 16 can be mounted on. Next, other embodiments of the present invention will be described with reference to the drawings. FIG. 5 is a cross-sectional view of a semiconductor device mounting process showing another embodiment of the present invention.
【0013】まず、図5(a)に示すように、回路基板
20上に透明電極21を形成する。電極はスパッタリン
グ、蒸着、CVD等の装置によって成膜を行ない、ホト
リソ工程によりICの電極があたる部分に凹部22(穴
を含む)を形成してもよいし、厚膜印刷により形成して
もよい。厚さは数千Å〜数μmである。ここで、透明電
極21の膜厚をaとする。First, as shown in FIG. 5(a), a transparent electrode 21 is formed on a circuit board 20. The electrodes may be formed by a device such as sputtering, vapor deposition, or CVD, and the recesses 22 (including holes) may be formed in the portions of the IC that are in contact with the electrodes by a photolithography process, or may be formed by thick film printing. . The thickness is several thousand Å to several μm. Here, the film thickness of the transparent electrode 21 is assumed to be a.
【0014】次に、図5(b)に示すように、直径数千
Å〜数μmの導電性フィラー23を透明電極21中に形
成された凹部22に入れる。この時の凹部22に入った
状態の導電性フィラーの高さbは透明電極の膜厚aより
高くなくてはならない。つまり、b>aの関係を満たさ
なくてはならない。次に、図5(c)に示すように、透
明電極21と導電性フィラー23に紫外線硬化型接着剤
24をかける。Next, as shown in FIG. 5(b), a conductive filler 23 having a diameter of several thousand Å to several μm is placed in the recess 22 formed in the transparent electrode 21. At this time, the height b of the conductive filler in the recess 22 must be higher than the film thickness a of the transparent electrode. In other words, the relationship b>a must be satisfied. Next, as shown in FIG. 5(c), an ultraviolet curing adhesive 24 is applied to the transparent electrode 21 and the conductive filler 23.
【0015】次に、図5(d)に示すように、ICチッ
プ25と回路基板20を周知の方法にて位置合わせをし
て、ICチップ電極26が紫外線硬化型接着剤24、導
電性フィラー23上にくるようにして、加圧するととも
に、回路基板20側の光源27から紫外線を照射するこ
とにより、半導体素子の実装工程が完了する。このよう
に構成することにより、図6に示すように、導電性フィ
ラー23を介して、ICチップ電極26と透明電極21
とは確実な電気的接続を行うことができ、回路基板20
へのICチップ25の実装を行うことができる。なお、
図6(a)は半導体素子の実装断面図、図6(b)はそ
の半導体素子の実装平面図である。Next, as shown in FIG. 5(d), the IC chip 25 and the circuit board 20 are aligned using a well-known method, and the IC chip electrode 26 is coated with the ultraviolet curing adhesive 24 and the conductive filler. The mounting process of the semiconductor element is completed by placing the semiconductor element on top of the semiconductor element 23 and applying pressure and irradiating ultraviolet rays from the light source 27 on the circuit board 20 side. With this configuration, as shown in FIG. 6, the IC chip electrode 26 and the transparent electrode 21 are connected via the conductive filler 23.
A reliable electrical connection can be made with the circuit board 20.
The IC chip 25 can be mounted on. In addition,
FIG. 6(a) is a cross-sectional view of the semiconductor element, and FIG. 6(b) is a plan view of the semiconductor element.
【0016】また、上記した各実施例における紫外線硬
化型接着剤に代えて、例えば、熱を加えると硬化する熱
硬化型の接着剤等を用いても同様の効果を奏することが
できる。この時の接着剤の硬化方法は使用する接着剤に
適したものを用いればよい。更に、上記した回路基板1
0,20、電極11,21、絶縁性膜12は透明である
必要がない場合もある。また、導電性フィラーの直径を
より微細化にすることにより、微細電極の接続が可能と
なる。Furthermore, in place of the ultraviolet curable adhesive in each of the above-described embodiments, the same effect can be obtained by using, for example, a thermosetting adhesive that hardens when heat is applied. At this time, any method suitable for the adhesive used may be used for curing the adhesive. Furthermore, the circuit board 1 described above
In some cases, the electrodes 11, 21, and the insulating film 12 do not need to be transparent. Further, by making the diameter of the conductive filler finer, it becomes possible to connect fine electrodes.
【0017】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【0018】[0018]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、次のような効果を奏することができる。電極部
を凹部形状とし、その中へ導電性フィラーと接着剤を入
れ、導電性フィラーを介して半導体素子を回路基板上へ
実装するようにしたので、導電性フィラーを回路基板上
の電極部(透明電極)に集中することができ、半導体素
子(ICチップ)の電極部と回路基板の電極部間での導
電性フィラーの逸脱による電気的接続不良をなくすこと
ができる。また、電極間のショートを防ぐことができる
。As described in detail above, according to the present invention, the following effects can be achieved. The electrode part is shaped like a concave part, a conductive filler and an adhesive are put into the concave part, and the semiconductor element is mounted on the circuit board via the conductive filler. (transparent electrode), and it is possible to eliminate electrical connection failures due to deviation of the conductive filler between the electrode part of the semiconductor element (IC chip) and the electrode part of the circuit board. Furthermore, short circuits between electrodes can be prevented.
【図1】本発明の実施例を示す半導体素子の実装工程断
面図である。FIG. 1 is a cross-sectional view of a semiconductor device mounting process showing an embodiment of the present invention.
【図2】本発明の実施例を示す半導体素子の実装断面図
である。FIG. 2 is a cross-sectional view of a semiconductor device packaged according to an embodiment of the present invention.
【図3】従来の半導体素子の実装工程断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device mounting process.
【図4】従来の半導体素子の実装断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor device mounted thereon.
【図5】本発明の他の実施例を示す半導体素子の実装工
程断面図である。FIG. 5 is a cross-sectional view of a semiconductor device mounting process showing another embodiment of the present invention.
【図6】本発明の他の実施例を示す半導体素子の実装状
態を示す図である。FIG. 6 is a diagram showing a mounting state of a semiconductor element showing another embodiment of the present invention.
10,20 回路基板
11,21 透明電極
12 絶縁性透明膜
13,22 凹部
14,23 導電性フィラー
15,24 紫外線硬化型接着剤16,25
ICチップ
17,26 ICチップ電極
18,27 光源10, 20 Circuit board 11, 21 Transparent electrode 12 Insulating transparent film 13, 22 Recess 14, 23 Conductive filler 15, 24 Ultraviolet curing adhesive 16, 25
IC chip 17, 26 IC chip electrode 18, 27 Light source
Claims (4)
た半導体素子の実装方法において、(a)回路基板上に
凹部形状をした電極部以外の部位に絶縁性膜を形成する
工程と、(b)該凹部に導電性フィラーを入れる工程と
、(c)該導電性フィラーが入った凹部に接着剤を入れ
る工程と、(d)前記導電性フィラーを介して半導体素
子を回路基板上へ実装する工程とを施すことを特徴とす
る半導体素子の実装方法。1. A method for mounting a semiconductor element on a circuit board via a conductive filler, comprising the steps of: (a) forming an insulating film on a portion of the circuit board other than the recessed electrode portion; b) putting a conductive filler into the recess, (c) putting an adhesive into the recess containing the conductive filler, and (d) mounting a semiconductor element onto a circuit board via the conductive filler. 1. A method for mounting a semiconductor device, comprising the steps of:
において、前記絶縁性膜の膜厚aは凹部に入った導電性
フィラーの高さbよりも低くしたことを特徴とする半導
体素子の実装方法。2. The semiconductor device mounting method according to claim 1, wherein the thickness a of the insulating film is lower than the height b of the conductive filler entered into the recess. Method.
た半導体素子の実装方法において、(a)回路基板上の
電極部に凹部を形成する工程と、(b)その形成された
凹部に導電性フィラーを入れる工程と、(c)該凹部に
接着剤を入れる工程と、(d)該導電性フィラーを介し
て回路基板上に半導体素子を実装する工程とを施すこと
を特徴とする半導体素子の実装方法。3. A method for mounting a semiconductor element on a circuit board via a conductive filler, which includes the steps of (a) forming a recess in an electrode portion on the circuit board; and (b) adding conductive material to the formed recess. A semiconductor device comprising: (c) putting an adhesive into the recess; and (d) mounting a semiconductor element on a circuit board via the conductive filler. How to implement.
において、前記電極部の高さaは凹部に入った導電性フ
ィラーの高さbよりも低くしたことを特徴とする半導体
素子の実装方法。4. The method for mounting a semiconductor device according to claim 3, wherein the height a of the electrode portion is lower than the height b of the conductive filler that has entered the recess. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6866791A JPH04304645A (en) | 1991-04-02 | 1991-04-02 | Method for mounting semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6866791A JPH04304645A (en) | 1991-04-02 | 1991-04-02 | Method for mounting semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04304645A true JPH04304645A (en) | 1992-10-28 |
Family
ID=13380297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6866791A Withdrawn JPH04304645A (en) | 1991-04-02 | 1991-04-02 | Method for mounting semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04304645A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08236577A (en) * | 1995-02-28 | 1996-09-13 | Nec Corp | Face-down mounting method |
JP2006093420A (en) * | 2004-09-24 | 2006-04-06 | Oki Electric Ind Co Ltd | Mounting method of semiconductor device |
JP2007208568A (en) * | 2006-01-31 | 2007-08-16 | Nippon Dempa Kogyo Co Ltd | Surface mount crystal oscillator |
JP2021177503A (en) * | 2020-05-07 | 2021-11-11 | 国立大学法人信州大学 | Method for manufacturing bonded structure, chip, substrate, paste containing conductive filler and bonded structure |
-
1991
- 1991-04-02 JP JP6866791A patent/JPH04304645A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08236577A (en) * | 1995-02-28 | 1996-09-13 | Nec Corp | Face-down mounting method |
JP2006093420A (en) * | 2004-09-24 | 2006-04-06 | Oki Electric Ind Co Ltd | Mounting method of semiconductor device |
JP2007208568A (en) * | 2006-01-31 | 2007-08-16 | Nippon Dempa Kogyo Co Ltd | Surface mount crystal oscillator |
JP2021177503A (en) * | 2020-05-07 | 2021-11-11 | 国立大学法人信州大学 | Method for manufacturing bonded structure, chip, substrate, paste containing conductive filler and bonded structure |
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Legal Events
Date | Code | Title | Description |
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A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980711 |