JPH0430421A - Selective metal growth method - Google Patents
Selective metal growth methodInfo
- Publication number
- JPH0430421A JPH0430421A JP13416490A JP13416490A JPH0430421A JP H0430421 A JPH0430421 A JP H0430421A JP 13416490 A JP13416490 A JP 13416490A JP 13416490 A JP13416490 A JP 13416490A JP H0430421 A JPH0430421 A JP H0430421A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- side wall
- selective
- growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 title claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910003074 TiCl4 Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 210000000481 breast Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路の電極形成のためのコンタクトホー
ルや、多層配線におけるビヤホール内への選択的メタル
成長法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for selectively growing metal into contact holes for forming electrodes of integrated circuits and via holes in multilayer wiring.
〔発明の概要］
本発明は、コンタクトホールやビヤホール内にメタルを
選択的に成長させるに際し、コンタクトホールの側壁に
は選択成長の種となるべき非晶質シリコン膜（以下ａ−
Ｓｉ膜という）を形成し、コンタクトホールの底部には
窒化チタン膜（以下ＴｉＮ膜という）等の耐熱性膜を形
成した後、メタルをコンタクトホール内に選択的に成長
させる選択メタル成長法である。コンタクトホールの側
壁にａＳｉ膜を形成してメタルの選択成長の種とし、か
つ底部の耐熱性膜によって下地の材料との反応を防止す
ることができる。[Summary of the Invention] When selectively growing metal in a contact hole or a via hole, the present invention provides an amorphous silicon film (hereinafter referred to as a-
This is a selective metal growth method in which a heat-resistant film such as a titanium nitride film (hereinafter referred to as TiN film) is formed at the bottom of the contact hole, and then metal is selectively grown inside the contact hole. . An aSi film is formed on the side wall of the contact hole to serve as a seed for selective metal growth, and a heat-resistant film on the bottom can prevent reaction with the underlying material.
〔従来の技術］
集積回路の電極形成のコンタクトホールや、多層配線の
ビヤホール内に、メタルを選択的に埋め込んで平坦化を
行う方法が用いられている。コンタクトホール内に選択
的にメタルを埋め込むときの材料として、通常ＳｉＨ４
還元により、高速でメタルを成長できるタングステン（
以下−という）をコンタクトホール内に選択的に成長さ
せる技術、いわゆる選択Ｗ−ＣＶＤ法が用いられる。す
なわち、最近の高密度集積回路のコンタクトホールの穴
の直径に対する深さ、すなわちアスペクト比がますます
大きくなって来つつあるが、選択Ｗ−ＣＶＤ法はアスペ
クト比に関係なくコンタクトホールを埋め込むため有望
である。[Prior Art] A method is used in which metal is selectively buried in contact holes for forming electrodes of integrated circuits or via holes in multilayer wiring for planarization. SiH4 is usually used as a material for selectively filling metal into contact holes.
Tungsten (
A so-called selective W-CVD method, which is a technique for selectively growing a layer (hereinafter referred to as -) in a contact hole, is used. In other words, although the depth to diameter of contact holes in recent high-density integrated circuits, that is, the aspect ratio, is becoming larger and larger, the selective W-CVD method is promising because it buries contact holes regardless of the aspect ratio. It is.
しかし、デバイスに応用した場合、再現性よく、かつリ
ーク電流の少ないオーミックコンタクトを実現すること
が困難になってきている。一つには、下地のシリコンの
表面の拡散層あるいはコンタクト部とシリサイド化反応
を起こして信軌性を低下させるためである。この反応を
防止するために、例えば第２図に示すような耐熱性膜を
有するコンタクトホールの形成方法が提案されていた（
特開平２−１６７５５号公報）。まず、シリコン基板１
の表面にＳｉＯ□のような絶縁膜２に、コンタクトホー
ル３を形成する。次に、コンタクトホールの底部４にチ
タンシリサイド膜６（以下Ｔｉ５ｉｚ膜という）を形成
し、さらにＴｉＮ膜７を形成し、その上にタングステン
膜８（以下−膜という）を形成する。However, when applied to devices, it has become difficult to realize ohmic contacts with good reproducibility and low leakage current. One reason is that a silicidation reaction occurs with the diffusion layer or the contact portion on the surface of the underlying silicon, resulting in a decrease in the reliability. In order to prevent this reaction, a method of forming a contact hole with a heat-resistant film as shown in Fig. 2 has been proposed (
JP-A-2-16755). First, silicon substrate 1
A contact hole 3 is formed in an insulating film 2 such as SiO□ on the surface. Next, a titanium silicide film 6 (hereinafter referred to as Ti5iz film) is formed at the bottom 4 of the contact hole, a TiN film 7 is further formed, and a tungsten film 8 (hereinafter referred to as - film) is formed thereon.
この−膜の上にポリシリコンを全面被着してコンタクト
ホール内のみポリシリコンを残すようにする。Polysilicon is deposited on the entire surface of this film, leaving polysilicon only in the contact holes.
また、第３図に示すような選択成長の種を有するコンタ
クトホールが提案されていた（特開昭６２−１４１７３
９号公報）。前述のコンタクトホール形成と同様にして
形成されたコンタクトホール３の側壁５にのみ、ポリシ
リコン膜９を形成し、さらに側壁に一膜８を形成する。In addition, a contact hole having a selective growth seed as shown in Fig. 3 was proposed (Japanese Patent Application Laid-Open No. 62-14173
Publication No. 9). A polysilicon film 9 is formed only on the side wall 5 of the contact hole 3 formed in the same manner as in the formation of the contact hole described above, and a film 8 is further formed on the side wall.
側壁にのみポリシリコン膜やり膜を残すには、異方性エ
ツチング法を用いる。この側壁の讐膜を選択成長の種と
して埋め込み用の−を選択的に成長させることができる
。Anisotropic etching is used to leave the polysilicon film only on the side walls. This side wall membrane can be used as a selective growth seed to selectively grow the embedding material.
前述のコンタクトホールの底部に耐熱性膜としてＴｉＮ
膜を用いたとき、選択的に埋め込むべき−の選択成長性
が阻害されるおそれがあった。また、ポリシリコンのよ
うな選択成長の種をコンタクトホール内の全面に形成す
れば選択成長は改善されるが、耐熱性を満足することが
できない。TiN is placed as a heat-resistant film on the bottom of the contact hole mentioned above.
When a membrane is used, there is a risk that the selective growth of the material to be selectively embedded may be inhibited. Furthermore, if selective growth seeds such as polysilicon are formed over the entire surface of the contact hole, selective growth can be improved, but heat resistance cannot be satisfied.
本発明の目的は、選択成長性と耐熱性の向上を同時に満
足するコンタクトホールへのメタルの成長を実現するこ
とにある。An object of the present invention is to realize metal growth in contact holes that satisfies selective growth properties and improved heat resistance at the same time.
前記課題を解決するために、コンタクトホールの側壁に
選択成長の種となるべき膜を形成し、コンタクトホール
の底部に耐熱性膜となるべき膜を形成した後、コンタク
トホール内へメタルを選択的に成長させて埋め込めば、
両者を同時に満足することができる。In order to solve the above problem, after forming a film to serve as a selective growth seed on the side wall of the contact hole and forming a film to serve as a heat-resistant film at the bottom of the contact hole, metal is selectively deposited into the contact hole. If you grow it and embed it in
Both can be satisfied at the same time.
耐熱性膜は、メタルの選択成長を阻害するおそれが大き
いので、側壁にのみ選択成長の種を形成しておけばよい
。そのために、まずコンタクトホール内に選択成長の種
となるべき非晶質シリコン膜（以下ａ−５ｔ膜という）
を形成し、しかる後、耐熱性膜としてのＴｉＮ膜を形成
すれば、側壁に被着したＴｉＮ膜は粗であるために、プ
ラズマエツチング法によってエツチングすれば除去され
て、側壁のみにａ−Ｓｉ膜が露出して、胸の選択成長の
種とすることができて、かつ耐熱性の向上をはかること
ができる。Since the heat-resistant film is highly likely to inhibit the selective growth of metal, it is sufficient to form seeds for selective growth only on the sidewalls. For this purpose, first, an amorphous silicon film (hereinafter referred to as an A-5T film) that should be a seed for selective growth is formed in the contact hole.
After that, if a TiN film is formed as a heat-resistant film, the TiN film deposited on the side wall is rough and can be removed by plasma etching, leaving a-Si on only the side wall. The membrane is exposed and can be used as a seed for selective breast growth and can improve heat resistance.
本発明の実施例を第１図ａないし第１図ｄを用いて説明
する。Embodiments of the present invention will be described using FIGS. 1a to 1d.
まず、第１図ａに示すように、シリコン基板１１の表面
に、ＳｉＯ□等の絶縁膜１２を形成して所定寸法のコン
タクトホール１３を開口する。しかる後、全面にコンタ
クト抵抗を下げるため、例えば燐（Ｐ）をドープしたａ
−５ｉ膜１６を形成する。また、ａ−Ｓｉ膜１６の形成
には、高周波バイアス印加によって側壁１５のａ−３ｉ
膜１６を緻密化するために、高周波バイアス印加型ＥＣ
Ｒプラズマ装置を用いるのがよい。First, as shown in FIG. 1A, an insulating film 12 such as SiO□ is formed on the surface of a silicon substrate 11, and a contact hole 13 of a predetermined size is opened. After that, in order to lower the contact resistance, the entire surface is doped with phosphorus (P), for example.
-5i film 16 is formed. Further, in forming the a-Si film 16, the a-3i of the side wall 15 is
In order to densify the film 16, a high frequency bias application type EC is used.
It is preferable to use an R plasma device.
条件として、ソースガスに５ｉＨａ／ＰＨ３を用い、減
圧下で高周波バイアスパワー３００−を印加して、マイ
クロ波パワー８００−１磁場の強さ８７５ガウスのＥＣ
Ｒプラズマ装置によって形成する。The conditions were to use 5iHa/PH3 as the source gas, apply a high frequency bias power of 300- under reduced pressure, and apply an EC of microwave power of 800-1 and magnetic field strength of 875 Gauss.
It is formed using an R plasma device.
次に、第１図すに示すように、ＴｔＮ膜１７をａ−Ｓｉ
膜１６の上に形成する。形成方法は、高周波バイアスを
印加しないＥＣＲプラズマ装置によって形成する。この
ときのソースガスにはＴｉＣｌ４／ＮＦ１３を用い、高
周波バイアスを印加しないこと以外は前述の条件と同様
である。Next, as shown in FIG. 1, the TtN film 17 is
Formed on the membrane 16. The formation method is an ECR plasma device that does not apply a high frequency bias. The conditions are the same as those described above except that TiCl4/NF13 is used as the source gas at this time and no high frequency bias is applied.
次に、第１図Ｃに示すように、同じ高周波バイアス印加
型ＥＣＲプラズマ装置を用いるか、他のプラズマ装置を
用いるかして、粗の部分のＴｉＮ、すなわち側壁のＴｉ
Ｎ膜１７ａをプラズマエツチングによって除去する。ホ
ール底部１４と、上面のＴｉＮ膜１７は、緻密であるた
め、ＣＦ４のような弗素主体のプラズマエツチングでは
除去されない。工・ンチング時間は、側壁１５の計Ｓｉ
膜１６が除去されない程度の時間内であればよい。Next, as shown in FIG.
The N film 17a is removed by plasma etching. Since the hole bottom 14 and the TiN film 17 on the top surface are dense, they cannot be removed by plasma etching mainly composed of fluorine such as CF4. The machining/nchching time is based on the total Si of the side wall 15.
It is sufficient that the time is such that the film 16 is not removed.
次に、第１図ｄに示すように、選択ＩＬ−ＣＶ Ｄ法に
よって、−１８を形成する。このとき、コンタクトホー
ル底部１４のＴｉＮ膜１７の上にはＷｌＢが成長しにく
いが、側壁１５のａ−Ｓｉ膜１６を成長の種としてＷｌ
Ｂが成長するので、コンタクトホール１３の中を埋め込
むことができる。この後に、上部のａ−５ｉ膜１６やＴ
ｉＮ膜１７を異方性エツチング法等によって除去して後
、スパッタリング法等によって上部配線を形成すること
ができる。Next, as shown in FIG. 1d, -18 is formed by selective IL-CVD method. At this time, WlB is difficult to grow on the TiN film 17 at the bottom of the contact hole 14, but WlB is grown using the a-Si film 16 on the sidewall 15 as a growth seed.
Since B grows, the inside of the contact hole 13 can be filled. After this, the upper a-5i film 16 and T
After removing the iN film 17 by an anisotropic etching method or the like, an upper wiring can be formed by a sputtering method or the like.
本発明の実施例においては、シリコン基板上のコンタク
トホールについて説明したが、シリコン以外の化合物半
導体基板上のコンタクトホールあるいはＡＩのような配
線上の接続のためのビヤホール等においても同様に適用
可能である。In the embodiments of the present invention, a contact hole on a silicon substrate has been described, but it can be similarly applied to a contact hole on a compound semiconductor substrate other than silicon or a via hole for connection on wiring such as AI. be.
また、コンタクトホール底部に、ａ−５ｉ膜を残したま
まＴｉＮ膜を形成したが、第１図ａの状態からａ−Ｓｉ
膜をエッチバックして、側壁のみに残し、底部にはＴｉ
Ｎ膜が下地と接するようにすれば、選択−を形成後のア
ニール後に、残ったａ−５ｉと選択−とがシリサイド反
応を起こしてジャンクションリークが増大するような現
象を解決できるので、より望ましい方法である。In addition, a TiN film was formed at the bottom of the contact hole while leaving the a-5i film, but from the state shown in Figure 1a, the a-Si
Etch back the film, leaving only the sidewalls and the bottom with Ti.
It is more desirable if the N film is in contact with the underlying layer, since it is possible to solve the phenomenon in which the remaining a-5i and the selected layer cause a silicide reaction after annealing after forming the selected layer, increasing junction leakage. It's a method.
本発明の実施例を用いて選択メタル成長を行えば、コン
タクトホール側壁に選択成長の種を有し、コンタクトホ
ール底部に耐熱性膜を有するので、メタルを埋め込むた
めの選択成長性と耐熱性同上を同時に実現することがで
きる。If selective metal growth is performed using the embodiment of the present invention, the sidewall of the contact hole has seeds for selective growth, and the bottom of the contact hole has a heat-resistant film. can be realized simultaneously.
第１図ａないし第１図ｄは本発明の選択メタル成長の工
程図、第２図は従来の耐熱性膜を有するコンタクトホー
ルの断面図、第３図は従来の選択成長の種を有するコン
タクトホールの断面図である。
１．１１
２．１２
３．１３
４．１４
５．１５・・
１６−−−−・−・・
・−−−−−−シリコン基板
絶縁膜
・−コンタクトホール
・・・−底部
−・側壁
ＴｉＳｉ２膜
・−ａ−Ｓｉ膜
７．１７
ＴｉＮ
膜
７ａ
側壁のＴｉＮ
膜
一膜
１日
ポリシリコン膜
１３コンタクトホーンレ
１４底部1a to 1d are process diagrams for selective metal growth of the present invention, FIG. 2 is a sectional view of a contact hole having a conventional heat-resistant film, and FIG. 3 is a contact hole having a conventional selective growth seed. FIG. 3 is a cross-sectional view of a hole. 1.11 2.12 3.13 4.14 5.15... 16------... ・----- Silicon substrate insulating film - Contact hole - Bottom - Side wall TiSi2 Film/-a-Si film 7.17 TiN film 7a Sidewall TiN film 1 film 1 day Polysilicon film 13 Contact horn layer 14 bottom
Claims (1)
タクトホール内に選択的にメタルを成長させる方法にお
いて、前記コンタクトホールの側壁に選択成長の種とな
るべき非晶質シリコン膜を形成する工程と、前記コンタ
クトホールの底部に耐熱性膜を形成する工程と、前記コ
ンタクトホール内に選択的にメタルを成長させる工程と
からなる選択メタル成長法。A method of opening a contact hole in an insulating film on a substrate and selectively growing metal in the contact hole includes a step of forming an amorphous silicon film to serve as a seed for selective growth on the side wall of the contact hole. . A selective metal growth method comprising the steps of: forming a heat-resistant film at the bottom of the contact hole; and selectively growing metal within the contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13416490A JPH0430421A (en) | 1990-05-25 | 1990-05-25 | Selective metal growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13416490A JPH0430421A (en) | 1990-05-25 | 1990-05-25 | Selective metal growth method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430421A true JPH0430421A (en) | 1992-02-03 |
Family
ID=15121952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13416490A Pending JPH0430421A (en) | 1990-05-25 | 1990-05-25 | Selective metal growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430421A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5627102A (en) * | 1993-03-23 | 1997-05-06 | Kawasaki Steel Corporation | Method for making metal interconnection with chlorine plasma etch |
| EP0848421A2 (en) * | 1996-12-16 | 1998-06-17 | Applied Materials, Inc. | Selective physical vapor deposition conductor fill in IC structures |
| KR100238698B1 (en) * | 1991-06-24 | 2000-01-15 | 이데이 노부유끼 | Method of forming multilayer interconnection structure |
| US6559061B2 (en) | 1998-07-31 | 2003-05-06 | Applied Materials, Inc. | Method and apparatus for forming improved metal interconnects |
| KR20030050846A (en) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor |
-
1990
- 1990-05-25 JP JP13416490A patent/JPH0430421A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100238698B1 (en) * | 1991-06-24 | 2000-01-15 | 이데이 노부유끼 | Method of forming multilayer interconnection structure |
| US5627102A (en) * | 1993-03-23 | 1997-05-06 | Kawasaki Steel Corporation | Method for making metal interconnection with chlorine plasma etch |
| US6063703A (en) * | 1993-03-23 | 2000-05-16 | Kawasaki Steel Corporation | Method for making metal interconnection |
| KR100320364B1 (en) * | 1993-03-23 | 2002-04-22 | 가와사키 마이크로 엘렉트로닉스 가부시키가이샤 | Metal wiring and its formation method |
| EP0848421A2 (en) * | 1996-12-16 | 1998-06-17 | Applied Materials, Inc. | Selective physical vapor deposition conductor fill in IC structures |
| EP0848421A3 (en) * | 1996-12-16 | 1998-09-30 | Applied Materials, Inc. | Selective physical vapor deposition conductor fill in IC structures |
| US6559061B2 (en) | 1998-07-31 | 2003-05-06 | Applied Materials, Inc. | Method and apparatus for forming improved metal interconnects |
| US6709987B2 (en) | 1998-07-31 | 2004-03-23 | Applied Materials, Inc. | Method and apparatus for forming improved metal interconnects |
| US6992012B2 (en) | 1998-07-31 | 2006-01-31 | Applied Materials, Inc. | Method and apparatus for forming improved metal interconnects |
| KR20030050846A (en) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor |
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