JPH04303890A - Video-graphic displaying system - Google Patents

Abstract

PURPOSE: To provide a video graphics display system which is inexpensive. CONSTITUTION: This video display system includes a graphics processor and a video RAM(VRAM) memory, which includes a 1st part 60 for storing video information and a 2nd part 66 for storing non-video information such as a program, a message buffer, and a font table. The 2nd part 66 includes dispersed memory areas formed of row parts 73, 74, and 75 which are not used for the video information. A system includes a multiplexing device for specifying the addresses of the 2nd memory part with successive addresses.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to a processing device adapted to control the operation of a video graphics display system, a video random access memory device adapted to store video data to be displayed, and a video random access memory device adapted to store video data to be displayed. The present invention relates to a video graphics display system including a monitoring device adapted to provide a visual display of data.

0002

[Prior art] Video graphics, display,
Today's computer systems that use monitors require a high degree of processing power to control the display, such as when windowed or other complex displays are provided. Accordingly, graphics processors have become available for the purpose of offloading the main system processor from the large amount of information processing required for information to be displayed on a monitor screen. Such computer systems also commonly utilize commercially available video random access memory (VRAM) integrated circuit chips. Each such chip includes dynamic random access memory (DRAM) and shift registers. The entire data string is latched into this shift register, thus freeing up the DRAM column for read/write independent of the shift register. Shift registers can be used to clock out data. This shift register can be clocked out at high (video) speeds to refresh the monitor screen. Among the available VRAM devices are 1 megabit devices with a 512 row by 512 column arrangement that can store 4 bits in each column location. VRA of other sizes
M devices, such as 256 kilobyte devices, are also available. In addition to VRAM memory devices for video information, graphics processors also require storage memory for program information and for storing message buffers, font tables, and the like. Providing storage memory for a graphics processor adds significant cost to video graphics display systems.

0003

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an inexpensive video graphics display system.

0004

[Means for Solving the Problems] Therefore, according to the present invention,
a processing unit configured to control the operation of the video graphics display system; a video random access memory unit configured to store video data to be displayed; and a video random access memory device configured to provide a visual display of the stored data. a memory controller coupled to the processing unit and the memory device, the memory adapted to store video data to be displayed on the monitor device; accessing the memory device in a first mode for accessing a first portion of the device and accessing a second portion of the memory device adapted to store non-video data in a second mode; the second portion includes a memory controller adapted to address and storage locations disposed within a plurality of storage areas distributed within the memory device; A video graphics display system is provided, wherein the second portion of the memory device is addressed by sequential addresses.

Video graphics display systems in accordance with the present invention can achieve reduced cost because the need for additional RAM is reduced or eliminated through efficient utilization of BRAM memory.

Embodiments of the present invention will now be described with reference to the accompanying drawings.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a block diagram of a video graphics display system 10 is shown. Video graphics display system 10 includes a host central processing unit (CPU) 12 and system memory 14, both coupled to a system bus 16. The system bus 16 is a bus interface unit 18
It is connected to the 16-bit local bus 20 via. Also, the local bus 20 has a graphics processor 2.
2. Local memory 24 (which may include RAM and ROM) and VRAM control circuit for storing program and data information VRAM control circuit 26
is connected. This VRAM control circuit 26 is connected to a VRAM (video random access memory) memory circuit 30 via a bus 28. VRAM memory circuit 30
has an output bus 32 which has three output lines 3 for RGB signals connected to a color monitor screen 38.
RAMDAC type digital-to-analog converter 3 with 6
Connected to 4.

[0008] The memory circuit 30 is NEC UPD412.
64 VRAM chips. The exact number and connection of these chips will depend on the particular application and type of monitor screen. Since this point is not directly relevant to the present invention, it will not be discussed in detail here. V used in the preferred embodiment
Preferably, the RAM chips are 1 megabit devices.

Graphics processor 22 may be, for example, a Texas Instruments TMS34010 graphics processor. Using such graphics processors, the display pitch, i.e., the difference in memory addresses between two pixels appearing in vertically adjacent positions on the screen, is used to support the XY addressing of pixels on the screen. It has to be the power of 2.

In the preferred embodiment video graphics display system 10, a line on monitor screen 38 (FIG. 1) is comprised of 640 pixels. In the redesigned embodiment, the monitor screen line consists of 768 pixels. The next power greater than 640 is 1024, so there are 386 (extra) locations per row of VRAM 30 that are not used for video information. Similarly, in the redesigned embodiment, there are 256 unused positions in each row. Referring to FIG. 2, row no. 1.No. 2.No. 3
Three rows of VRAM locations 50, 52, 54 are shown schematically. Thus, the BRAM memory map includes an area 60 for storing video information and an area 62 that is not used for storing video information in this embodiment. Region 62 is shown to include regions 64 and 66. Area 6
4 is row number. Area 70 containing bit positions 640 to 767 in 1 and corresponding areas 71, 72, etc. of subsequent lines, and area 66 includes area 73 containing bit positions 768 to 1023 and corresponding areas 74, 75, etc. of subsequent lines. . It will be appreciated that region 66 includes regions 73, 74, and 75 in first, second, and third rows, respectively, forming storage areas distributed throughout the memory map. The fact that the storage areas are distributed means that the first address 1792 of the second row area 74
address gap (from 1023 to 1791) before
follows the final address 1023 in the first row area 73, and a similar address gap exists between the storage area 74 and the storage area 75.

To briefly explain FIG. 3, two 1
Row No. of Megabit VRAM Memory Devices 80, 82
．． The physical layout of one location is shown. Here device 80 stores even numbered pixel locations and device 82 stores odd numbered pixel locations. This arrangement is required because the 1 megabit device used has 512 column locations. Thus, one VRAM row 50 (FIG. 2), etc., is distributed across two VRAM devices 80, 82, shown in FIG. 3, in the preferred embodiment. As shown in FIG. 3, a VRAM memory device 80
There is a video storage area consisting of area 84 in VRAM memory device 80 and area 86 in device 82, and an unused (surplus) video storage area consisting of area 88 in VRAM memory device 80 and area 90 in device 82. Since multiplexing of accesses to the two physical devices 80, 82 is readily possible, and to avoid unnecessarily complicating the description of this embodiment, these VRAM rows are arranged as shown in the memory map of FIG. Assume that

Referring to FIG. 4, VRAM control circuit 26
A block diagram is shown. This 16-bit multiplexed local bus 20 is connected to an address demultiplexer 100. The address demultiplexer 100 has 32
It is connected to mode decoder 102 via bit bus 104 . Mode decoder 102 is connected to multiplexer 105 including RAS/CAS multiplexer 106 . R.A.
S/CAS multiplexer 106 is connected via bus 108 to mode multiplexer 110, which forms part of multiplexer 105. Mode multiplexer 110
receives control input from mode decoder 102 via line 112. The output of mode multiplexer 110 is bus 2
8 to the VRAM memory unit 30. Row address strobe signal R active at low level
AS/, column address strobe signal CAS/ is connected to line 114 (
address demultiplexer 100, RAS/C
AS multiplexer 106 and VRAM memory unit 30.

Referring to FIGS. 5 and 6, multiplexers RAS/CAS multiplexers 106, 110 (FIG.
) is shown. Bus 104 of address demultiplexer 100 addresses columns and rows of the VRAM memory shown in FIG.
carries (among other things) address bits A0-A8 at RAS (row addr
ess strobe) address bit A9-
A17 (in practice, each VRAM memory chip 80,8
2). In the preferred embodiment, the RAS time occurs early in the addressing operation and the CAS time occurs late in the addressing operation.

It should be appreciated that there are two switching modules corresponding to the arrangement of FIG. 5 and seven switching modules corresponding to the arrangement of FIG. 6. First figure 5
Looking at RAS/CAS multiplexer 106, line 1
It includes switches SW8A, SW8B controlled by the RAS/signal and CAS/signal on 14. switch SW
8A has a terminal 120 connected to receive address bit A17 from bus 104 and a terminal 122 connected to receive address bit A8 from bus 104. Terminal 124 connects wire 126 that forms part of bus 108.
is connected to terminal 128 of switch SW8C, which forms part of mode multiplexer 110. Switch SW8B connects terminal 130 connected to receive address bit A15 from bus 104 and +5 volt supply terminal 1.
34 and a terminal 132 connected to the terminal 34. Through line 138 forming part of bus 108 line 136 connects switch S
Connected to terminal 140 of W8C. Switch SW8C has a terminal 142 to which signal RA8 on line 144 forming part of bus 28 is applied. switch S
W8C is activated under the control of a mode signal applied on line 112.

It should be appreciated that another switching module is provided which is similar to the switching module shown in FIG. 5 but has the connections and notation shown in parentheses in FIG. This further switching module thus has switches SW7A, SW7B, SW7C, input lines connected to receive address bits A16, A7, A14, and an output line providing signal RA7.

Referring now to FIG. 6, RAS/CAS
Multiplexer 106 includes switches SW6A and SW forming part of RAS/CAS multiplexer 106.
6B. These switches are line 1
14 by signals RAS/ and CAS/. Switch SW6A receives address bit A1 from bus 104.
Terminal 150 connected to receive address bit A6 from bus 104 and terminal 15 connected to receive address bit A6 from bus 104.
2. Terminal 154 is connected via line 156, which forms part of bus 108, to terminal 158 of switch SW6C, which forms part of mode multiplexer 110. Switch SW6B has a terminal 160 connected to receive address bit A13 from bus 104 and a terminal 162 connected to receive address bit A6 from bus 104. Terminal 168 of switch SW6C
A terminal 164 is connected to the terminal 164 via a line 166. Switch SW6C has a terminal 170 to which signal RA6 on line 172 forming part of bus 28 is applied. Switch SW6C is activated under the control of a mode signal applied on line 112.

It should be appreciated that six additional switching modules are provided, similar to those shown in FIG. 6, but with connections and names shown in parentheses in FIG. For example, the notation SW6A (5A:OA) is 6 above.
each separate switching module SW5A,
SW4A, SW3A, SW2A, SW1A and SW0
Indicates that A is included.

The above device operates in two modes: a normal mode in which the VRAM memory unit 30 is addressed for obtaining video information, and a normal mode in which the VRAM memory unit 30 is addressed for obtaining non-video information such as program storage, message buffers, font tables, etc. It should be appreciated that unit 30 can operate in a selected one of the following modes: continuous mode in which it is addressed;

Referring now to FIG. 7, the normal operating mode (
Normal mode). FIG. 7 illustrates VRAM addressing in normal mode. A typical address utilized by display system 10 is illustrated in FIG. 7 as address 200. Such an address contains N+1 bits 0,...,N, of which 9 bits 0 to 8 are column address 20.
2, and the 9 bits from 9 to 17 are row address 20.
Represents 4. The higher order bits 206 are sent to mode decoder 10
2. The total number of address bits will of course depend on the total memory capacity required for the particular application. R.A.S.
RAS (Row Address Strobe) initiated by / signal
The time occurs early in the addressing operation and is C
The AS (column address strobe) time occurs late in the address cycle. Assuming mode decoder 102 provides a signal indicating a normal address mode, this signal is applied to 105 via line 112. Multiplexer 105
is R in conjunction with mode multiplexer 110 as described above.
Includes an AS/CAS multiplexer 106. Looking at Figures 5 and 6, in normal operation mode, SW
The nine switches from 8C to SW0C have their switch arms connected to the upper terminals 128 and 1 shown in FIGS.
58 etc.

During the first half of normal mode addressing operation, the RAS/ signal is active so that switches SW8A, SW8B or SW0A, SW0B connect their switch arms to upper terminals 120, 130, 150, 160. be. These connections allow address bits A9 to A17 to be sent to the VRAM via bus 28 by multiplexer 105 (FIG. 7).
It can be seen that it is sent to memory unit 30 as a row address. Later in normal mode addressing operation, the CAS signal becomes active, so that switches SW8A, SW8B or SW0A, SW0B connect their switch arms to lower terminals 122, 132, 152.
, 162. These connections cause nine address bits A0 to A8 to be set to V by multiplexer 105.
It can be seen that it is applied to the RAM memory unit 30 as a column address. Thus, in normal mode operation of the preferred embodiment, region 60 (FIG.
) is addressed. Because the first 64 of each row
This is because only 0 pixels are used as video information. In the embodiment related to the design change described above, the areas 60 and 64
is addressed to obtain video information using the first 768 pixel locations.

The continuous operation mode will be explained with reference to FIG. FIG. 8 illustrates VRAM addressing in continuous mode. In this case mode decoder 102 provides a signal on line 112 indicating continuous addressing mode. In continuous addressing mode, switches SW8C to SW0C (see FIGS. 5 and 6) have their switch arms connected to lower terminals 140, 168, etc.

During the first half of a continuous mode addressing operation, the RAS/ signal is activated so that switches SW8A, SW8B or SW0A, SW0B (
5, 6) connect those switch arms to the upper terminal 12.
Connect to 0, 130, 150, 160. These connections allow nine address bits A7 to A15, indicated by reference numeral 222 in FIG. 8, to be sent as a row address to VRAM memory unit 30 via bus 28 via multiplexer 105 (FIG. 8). I understand. Later in a continuous mode addressing operation, the CAS/ signal is activated, which causes switches SW8A and SW8B to
SW0A, SW0B connect their switch arms to lower terminals 122, 132, 152, 162. These connections connect multiplexer 105 to +5 volt power supply 1.
Address bits A0 to A6 are received at address locations A7, A8 along with two high level bits (ie, bits of value "1") derived from 34 (FIG. 5). In this manner, a 9-bit address 224 (FIG. 8) is provided to VRAM memory unit 30 via multiplexer 105 and bus 28.

In summary, selection between normal memory mode operation and continuous memory mode operation is performed by appropriately decoding high order address bits within mode decoder 102. In normal memory mode operation, it is region 60 (FIG. 2) (combined regions 60, 64 in the redesigned embodiment) that is selected for access. In continuous memory mode operation, address bit 222 for row selection is moved two bits to the right, and address bit 222 for column selection is moved to the right by two bits.
4 holds those two highest positions at a high level "1". This restricts access to the rightmost section or region 66 (FIG. 2) of VRAM memory unit 30. Referring to FIG. 8, in continuous mode, bits A0 through A15 of address bits 200 are utilized for address definition, and that consecutive addresses in this address area address successive bit locations accessed within memory area 66. I understand. This allows these regions to operate as one continuous memory region even though they are formed as distributed regions within the map of the VRAM memory unit 30.

Referring now to FIG. 9, a memory map 300 of VRAM memory is shown in one embodiment of the present invention. This embodiment employs a plurality of separate VRAM devices (not shown), FIG. 9, that store information for two 640 x 480 pixel screen images that can be displayed on monitor 38 (FIG. 1). is exemplified. That is, area 302 stores video information for the first screen image, and area 304 stores video information for the second screen image. Note that in this example application, while graphics processor 22 is processing information for one screen image, the other screen image may be displayed on monitor 38 (FIG. 1). Region 306 forms a contiguously addressable contiguous memory region and provides 256 kilobytes of additional memory for graphics processor 22. Area 308 is an unused (surplus) memory area, and area 310 forms another unused memory area. Alternative configurations are also possible. For example, if the size of contiguous memory area 306 is reduced to no more than the first 960 rows, then 960
Area 3 will represent the remaining rows from 1023 to 1023
10 can be used as additional storage area using normal mode.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video graphics display system.

FIG. 2 is a diagram illustrating storage areas in a VRAM memory map.

FIG. 3 is a diagram illustrating the usage of individual VRAM memory device chips in a VRAM memory.

FIG. 4 is a block diagram showing a VRAM control unit included in the system of FIG. 1;

FIG. 5 is a diagram showing two multiplexers shown in FIG. 4;

FIG. 6 is a diagram showing two multiplexers shown in FIG. 4;

FIG. 7 is a diagram to aid in understanding VRAM memory addressing operations.

FIG. 8 is a diagram to aid in understanding VRAM memory addressing operations.

FIG. 9 is a memory map illustrating VRAM memory usage when using a system according to the present invention in one exemplary application.

[Explanation of symbols]

22 Graphics processing device
26 Memory control device 30 Video random access memory 38
Monitor 60 First part of memory
66 Second part of memory

Claims (1)

[Claims] 1. A processing device adapted to control the operation of a video graphics display system, a video random access memory device adapted to store video data to be displayed, and a visual representation of the stored data. a monitor device adapted to provide a display, a memory controller coupled to the processing unit and the memory device for storing video data to be displayed on the monitor device; accessing a first portion of the memory device adapted to store non-video data in a first mode; and accessing a second portion of the memory device configured to store non-video data in a second mode; the second portion includes a memory controller adapted to address the memory device; and the second portion includes a storage location located in a plurality of storage areas distributed within the memory device;
A video graphics display system further characterized in that the memory controller is adapted to sequentially address the second portion of the memory device.