JPH04303788A - Person detector - Google Patents

Abstract

PURPOSE:To obtain a person detector capable of surely eliminating error signal due to dielectric breakdown and the like between electrodes. CONSTITUTION:If a reference signal for a detection space between a pair of electrodes of a sensor Cx is supplied to a charging circuit including this, a signal delayed for the reference signal is formed in accordance with the change in the electrostatic capacity of the sensor Cx. This delay time is compared with a first threshold value in a first comparison means M1, the comparison result according to the delay time is output to a judgment means M3 and the existence of man is judged. Simultaneously, the delay signal is compared with the level of a second threshold value in a second comparison means M2 and the comparison result is output to an elimination means M4. By this, if the delay signal does not reach the second threshold value, the comparison result of the first comparison means M1 is eliminated from the judgment of existence of man at the judgment means M3.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a person detection device for detecting the presence or absence of a person, and more particularly to a person detection device that determines the presence or absence of a person based on a change in capacitance between at least a pair of electrodes facing each other across a space for accommodating a person. This relates to a person detection device.

0002

[Prior Art] For example, in vehicles, there are seat belt devices that automatically operate when a person gets on the vehicle, power windows or auto-lock devices that automatically close when the person gets out of the vehicle, etc. Control is required depending on the presence or absence or presence or absence of a part of the body of a person (hereinafter simply referred to as the presence or absence of a person). Therefore, a means to detect the presence or absence of personnel is required, for example,
As described in Japanese Patent No. 82 and Japanese Patent Application Laid-Open No. 62-138780, a conductor provided on the seat and the vehicle body are used as electrodes, and a capacitor is formed between the electrodes and the cabin space for accommodating personnel. A device has been proposed that detects changes in capacitance depending on the presence or absence of .

Furthermore, Japanese Patent Application Laid-Open No. 1-113692 discloses that a duty ratio is determined between a pulse signal of a predetermined frequency and a delayed pulse signal delayed according to a change in capacitance of a detection means to obtain a predetermined value. A person detection device is disclosed that determines the presence or absence of a person by comparison. According to this,
When comparing the duty ratio and the reference value, a noise signal that is asynchronous to the two pulse signals that are synchronized can be easily identified, so that such noise signals can be discriminated and compared.

0004

[Problem to be Solved by the Invention] In such a person detection device, not only erroneous signals due to noise etc. but also a pair of electrodes such as an electrode provided on a seat and a vehicle body are used, and a capacitor is formed by these. In this case, if the insulation resistance between the two decreases or dielectric breakdown occurs, an erroneous signal will be generated, making it impossible to accurately determine the presence or absence of personnel. Therefore, an object of the present invention is to provide a person detection device that can reliably remove false signals.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a person detection device that has at least one pair of electrodes and detects a person according to a change in capacitance between these electrodes. , is equipped with the following means. That is, the detection means M supplies a reference signal of a predetermined frequency pulse to a pair of electrodes shown in FIG. 1, charges and discharges them every cycle, and forms a delayed signal.
0, and a first comparing means M that compares the delayed signal of the detecting means with a first threshold value and outputs a comparison result according to the delay time.
1, and the delayed signal is set to a second threshold value greater than the first threshold value.
a second comparing means M2 that compares the size with a threshold value and outputs a comparison result; a determining means M3 that determines the presence or absence of personnel according to the comparison result of the first comparing means M1; and a second comparing means M
an exclusion means M4 for excluding the comparison result of the first comparison means M1 from the determination of the presence or absence of personnel by the determination means M3 when it is determined that the delayed signal is smaller than the second threshold value based on the output of the first comparison means M1; It is equipped with the following.

[0006] Furthermore, in a person detection device that has at least one pair of electrodes and detects a person according to a change in capacitance between the electrodes, a reference signal of a predetermined frequency pulse is supplied to the pair of electrodes. a detection means that charges and discharges every cycle to form a delayed signal; a comparison means that compares the delayed signal of the detection means with a predetermined threshold value and outputs a comparison result according to the delay time;
determination means for determining the presence or absence of personnel according to the comparison result of the comparison means, the determination means only based on the comparison result with the predetermined threshold value formed at the beginning of each cycle of the reference signal. It is best to configure it so that it responds.

[0007]Furthermore, in the person detection device which has at least one pair of electrodes and detects a person according to a change in capacitance between the electrodes, a reference signal of a predetermined frequency pulse is supplied to the pair of electrodes. a detection means that charges and discharges every cycle to form a delayed signal; a comparison means that compares the delayed signal of the detection means with a predetermined threshold value and outputs a comparison result according to the delay time;
a conversion means for converting a comparison result with the predetermined threshold value into a digital quantity; and an addition for adding the digital quantity for a predetermined number of pulses of the reference signal a first predetermined number of times or more and calculating an average value. averaging means; determining means for determining the presence or absence of personnel according to the calculation result of the averaging means; and addition for prohibiting addition processing in the averaging means when the digital quantity for the predetermined number of pulses includes an abnormal value. When the number of times the addition is prohibited by the prohibition means and the addition prohibition means exceeds the number obtained by subtracting the first predetermined number of times during addition processing of the second predetermined number of times or more, the calculation result of the arithmetic averaging means. The apparatus may further include an output prohibition means for prohibiting output of the information to the determination means.

[0008]

[Operation] In the person detection device of the present invention having the above-described structure, a capacitor is formed by a pair of electrodes to constitute a sensor Cx shown in FIG. 1, and a charging circuit is constituted together with a resistor R1. The capacitance of the sensor Cx changes depending on the presence or absence of the person 1, and when a reference signal is supplied from the detection means M0 to the charging circuit, the charging speed changes depending on the change in the capacitance of the sensor Cx. That is, a signal delayed with respect to the reference signal is formed in the charging circuit, and this delayed signal is compared with a first threshold value in the first comparing means M1, and the comparison result according to the delay time is sent to the determining means. Output to M3. At the same time, the second
The comparison means M2 compares the delayed signal with a second threshold value, and the comparison result is outputted to the removal means M4. When the removal means M4 determines that the delayed signal has not reached the second threshold, the comparison result of the first comparison means M1 at that time is removed from the determination of the presence or absence of personnel by the determination means M3. be done. Therefore, in the determining means M3, only the delayed signal exceeding the second threshold is detected as the first signal.
The presence or absence of personnel is determined based on the comparison result according to the delay time.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the person detection device of the present invention will be described below with reference to the drawings. As shown in Figure 1, sensor Cx
is a capacitor formed between the vehicle body 2, the electrode 4 provided on the seat 3, and the cabin space between the two,
Together with the resistor R1, it constitutes a charging circuit. And Figure 2
As shown in FIG. 2, it includes two integrated circuits: a detection circuit IC1 and a determination circuit IC2. The detection circuit IC1 is a circuit that detects a capacitance change of the sensor Cx and constitutes the detection means referred to in the present invention, and also controls starting and stopping of the determination circuit IC2, and is constituted by a gate array. On the other hand, the determination circuit IC2 is a circuit that determines the presence or absence of personnel based on the output of the detection circuit IC1, and has a microcomputer and constitutes the determining means according to the present invention. Below, sensor C
A charging circuit including x, a detection circuit IC1, and a determination circuit IC
2 will be explained in order for each configuration and operation.

The sensor Cx constitutes a capacitor as described above, and is connected to the detection circuit IC1 via the resistor R1 having a predetermined resistance value.
is connected to the output port SEO. The connection point between the sensor Cx and the resistor R1 is connected to the inverting input terminal of the first comparator CMP1 via the resistor R11, and also connected to the inverting input terminal of the first comparator CMP1.
12 to the inverting input terminal of the second comparator CMP2.

On the other hand, the constant voltage VCC is divided by resistors R2 and R3 to set a first threshold value VTH1, which is configured to be input to the non-inverting input terminal of the first comparator CMP1. Similarly, the constant voltage VCC is divided by resistors R4 and R5, and the second threshold value VT
H2 is set and is configured to be input to the non-inverting input terminal of the second comparator CMP2. The first comparator CMP1 is for detecting personnel, the second comparator CMP2 is for detecting dielectric breakdown, and the second threshold value VT
H2 is set to a higher level than the first threshold VTH1 (i.e., VTH2>VTH1)
. The first and second comparators CMP1 and CMP2 each have an output terminal connected to the input port S of the detection circuit IC1.
Connected to EI and SEH. These constitute the first comparing means and the second comparing means according to the present invention.

The operation of the circuit from the sensor Cx to the detection circuit IC1 will be explained with reference to the timing charts of FIGS. 3 and 4. In addition, (a) to (d) of FIGS. 3 and 4
shows the waveform of the signal at each point a to d in the circuit. First, when the reference signal (a) of a predetermined frequency pulse signal is output from the output port SEO of the detection circuit IC1, the signal (b) is generated by the charging circuit consisting of the resistor R1 and the sensor Cx. This signal (b) is compared with a first threshold value VTH1 set by resistors R2 and R3 in the first comparator CMP1, and the signal (c) is transferred from the output terminal to the input port SEI of the detection circuit IC1. is output to. Phase difference T0 between this signal (c) and reference signal (a)
is proportional to the product of the capacitance of the sensor Cx and the resistance value of the resistor R1, but since the resistor R1 is a fixed resistance with a predetermined resistance value,
The phase difference T0 will be proportional to the capacitance of the sensor Cx. Then, as described later, a signal (
The exclusive OR (EX-OR) of a) and signal (c) is determined. As a result, as shown in FIG. 3, the phase difference T0
A signal (x) with a pulse width corresponding to 1 is obtained, which is digitally processed and output to the determination circuit IC2.

On the other hand, the signal (b) is sent to the second comparator C.
MP2 is also supplied, and the second threshold value VTH2 (>VT
H1). Let the resistance value of sensor Cx be Rx,
If this is sufficiently larger than the resistance value of resistor R1 (also denoted by R1), the peak value of signal (b) will be approximately constant voltage V
Becomes CC. Therefore, the signal shown in FIG. 3(d) is output from the output terminal to the input port SEH of the detection circuit IC1. However, as the resistance value Rx decreases, VCC・Rx
Resistance R at the peak value determined by /(Rx+R1)
The value of 1 can no longer be ignored, and the peak value will decrease. Therefore, when Rx<R1·R5/R4, the signal (d) is maintained at a high (H) level as shown in FIG. Then, depending on the change in the resistance value of the resistor Rx, one of the signals (d) in FIGS. 3 and 4 is supplied to the input port SEH of the detection circuit IC1, and is set in the detection circuit IC1 as described later. Dielectric breakdown is detected according to the specified check timing.

In addition to the input/output ports described above, the detection circuit IC1 includes a port VCC for inputting a constant voltage VCC and a port GND for grounding, a plurality of ports connected to the determination circuit IC2, a port XI1 connected to the oscillation element OS1, XO
1. Output port INE is judgment circuit IC2
It outputs an enable signal that instructs input permission, that is, an input permission signal to the resistors R6 and R7 connected in parallel.
One end of these is connected to the input port IN2 of the determination circuit IC2, and the other end is connected to the input port CE, which is a chip enable terminal. This input permission signal is transmitted from the output port INE of the detection circuit IC1 at a predetermined period t.
1, and in response to this input permission signal, the detection data in the detection circuit IC1 is serially transferred from the output port SOT to the input port IN3 of the judgment circuit IC2 according to the timing clock of the judgment circuit IC2.

Furthermore, a detection circuit IC1 is connected to the input port SL.
A signal instructing an output data set is inputted to the input port SCL, an output clock signal is inputted to the input port SCL, and an execution result of the input permission signal to the determination circuit IC2 is inputted to the input port END. It is composed of
Processed as described below. The input port INP is connected to the output port OT4 of the determination circuit IC2, and the presence/absence signal of the determination result is input thereto. Note that the port RS1 is connected to the power supply circuit PC, and a reset signal is input thereto. The detection circuit IC1 is connected from an output port OTP to an external system 5 such as a display device via an output circuit OC.

The determination circuit IC2 is constituted by a microcomputer, and has built-in read-on memory, random access memory, etc. (not shown). Output port OT1, O
T2, OT3 and OT4 are connected to input ports SL, SCL, END and INP of the detection circuit IC1, respectively. The port VCC is connected to the power supply circuit PC and has a constant voltage V
CC is supplied, and port GND is grounded. Port RST is connected to power supply circuit PC and receives a reset signal. The input port IN1 is connected to the input circuit SC and also to the output side connection point of the resistors R6 and R7. Furthermore, a port XI2 connected to the oscillation element OS2,
Equipped with XO2.

The power supply circuit PC is connected to a power supply B via a diode D1, and also connected to diodes D2 and D3, an ignition switch IG, and an accessory switch A.
It is connected to power supply B via CC. Further, the ignition switch IG and the accessory switch ACC are connected to the input circuit SC via diodes D4 and D5.

FIGS. 5 to 7 are timing charts in this embodiment. FIG. 5 shows when the output to the external system 5 is stopped, and FIG. 6 shows when the output to the external system 5 is shifted from the stopped state to the output operation. FIG. 7 is a timing chart when the state of output to the external system 5 is shifted from the operating state to the state where the output is stopped. In FIG. 5, the detection circuit I
When C1 is in a standby state, the input permission signal changes from low (L) level to high (H) level,
When inputted to the judgment circuit IC2 from the output port INE,
The determination circuit IC2 enters a wake-up state, that is, an operable state.

After the clock becomes stable, the determination circuit IC2 inputs capacitance data corresponding to the output of the sensor Cx from the detection circuit IC1, and determines the presence or absence of personnel based on this capacitance data. In FIG. 5, since the output to the external system 5 is stopped, there is no output of the determination result of the presence or absence of personnel (the output of the presence or absence of personnel is OFF), and the determination circuit IC2 returns to the standby state. In addition, serial input in the figure is input port I.
This is the input of capacity data to N3. Since the output signal from the output port INE of the detection circuit IC1 is supplied to the determination circuit IC2 at predetermined time intervals t1, there is no need for time management regarding data processing in the determination circuit IC2, and therefore, in the standby state, as shown in FIG. As such, current consumption is kept low.

When the state of output to the external system 5 as shown in FIG. 6 is shifted to output operation, the output port I
When there is an input from NE, the determination circuit IC2 enters the wake-up state as described above. After the clock has stabilized after a slight delay, when it is detected that the ignition switch IG or the accessory switch ACC is turned on based on the input signal to the input port IN1, an output is generated to display the result of determining whether there is anyone present. The operation starts (person presence/absence output is ON). In the wake-up state, the signal of the input port IN1 (indicated by Acc/IG in FIGS. 5 to 7) is constantly monitored according to the output of the output port INE,
When the level is high (H), even after there is a serial input to the input port IN3 and the presence or absence of personnel is determined,
The determination result of the presence or absence of personnel is continuously output.

As shown in FIG. 7, if the input signal from the output port INE becomes a high (H) level when the result of determining the presence or absence of personnel is in the output state (ON), the input signal from the input port IN becomes high (H) level.
The presence or absence of personnel is determined in accordance with the serial input of capacity data to No. 3. Then, when the accessory switch ACC and the ignition switch IG are both turned off,
Since the input signal to the input port IN1 changes from the high (H) level to the low (L) level, the output of the determination result of the presence or absence of personnel is stopped, the system enters a standby state, and thereafter operates in the same manner as in FIG. 5.

Next, the operation within the determination circuit IC2 will be explained according to the flowchart of FIG. In FIG. 8, when a high (H) level signal is input to port CE, the determination circuit IC
2 starts operating, and in step 101, it is first determined whether or not it is in a cold start state. If the judgment circuit IC2 is in a cold start state before operation, step 10
Initialization is performed in step 2, and various clocks are cleared and various data are set to initial values. Next, the process proceeds to step 103, where the signal from the input circuit SC is input to the input port IN1, and the signal from the input circuit SC is input to the input port IN2.
An input permission signal from the output port INE of the detection circuit IC1 is input to the output port INE of the detection circuit IC1. Subsequently, in step 104, data is output from the output port OT4 that outputs the presence/absence signal of a person, and is supplied to the input port INP of the detection circuit IC1.

Then, in step 105, a watchdog is performed to check for abnormalities in the system, and step 1
After the state of the random access memory (not shown) is checked by a RAM check in step 06, the state of the input signal to the input port IN2 is determined in step 107. If the input signal is at a high (H) level, the capacitance data is serially input from the output port SOT of the detection circuit IC1 to the input port IN3 in step 108.
At step 9, the presence or absence of personnel is determined, and the process proceeds to step 110. On the other hand, if it is determined in step 107 that the input signal to the input port IN2 is at a low (L) level, the process directly proceeds to step 110.

In step 110, the input port I
The state of the input signal to N1 is determined, and if it is at a high (H) level, the output data of the output port OT4 is set and the process returns to step 103. On the other hand, when it is determined that the input signal to the input port IN1 is at the low (L) level, the output data of the output port OT4 is reset in step 112, and then the standby state is entered in step 113.

Next, the process of determining the presence or absence of personnel executed in step 109 will be described with reference to FIG. First, in step 201, it is determined whether the flag FI is set. This flag FI is set (1) when the capacitance data is transferred from the detection circuit IC1 to the determination circuit IC2, and the state of the flag FI is 0.
Determined every 5 seconds. If the flag FI is not set, the process returns to the main routine, but if it is set, the process proceeds to steps 202 to 204, where the previous value Da of the capacity data stored in the old capacity data storage register and the new capacity data storage register are stored. It is determined whether the difference from the stored current value Db is greater than or equal to a predetermined value. That is, in step 202, the difference between the previous value Da and the current value Db is calculated and stored as the change amount Dc in the capacitance change amount storage register. At step 203, the current value Db is stored as the previous value Da in the old capacity data storage register, and after the data is updated, the absolute value of the amount of change Dc is compared with a predetermined value X at step 204.

When the absolute value of the amount of change Dc is greater than or equal to the predetermined value X, the process proceeds to step 205, where it is determined whether a flag FJ indicating the presence or absence of personnel has not been set. When the flag FJ is set (1), it indicates "personnel present", and when it is not set (0), it indicates "no personnel". When it is determined in step 205 that the flag FJ is not set, the process proceeds to step 206, and the flag FJ is determined to be not set.
It is determined whether or not T1 is set, and if it is set, the process proceeds to step 207 and flag FJ is set. Here, the flag FT1 is set (1) when the timer TM1, which operates in response to a change from "no personnel" to "persons present", overflows. Similarly, the flag FT2 is set (1) when the timer TM2, which operates in response to a change from "staffed" to "staffed", overflows.

In step 206, if the flag FT1 is set, that is, if a predetermined period of time or more has passed after the change from "no personnel" to "persons present", the process proceeds to step 207, where the flag FJ is set, This will indicate "staff available". On the other hand, if it is determined in step 206 that the flag FT1 is not set, the process directly returns to the main routine. Meanwhile step 204
When it is determined that the absolute value |Dc| of the variation amount Dc is less than the predetermined value X, the process proceeds to step 208, where it is determined whether the flag FJ is set,
If the flag FT2 is set, the process proceeds to step 209, where it is determined whether the flag FT2 is set. If the flag FT2 is not set, the process returns to the main routine, but if the flag FT2 is set, that is, if a predetermined period of time has elapsed after changing from "staffed" to "unstaffed", the process proceeds to step 210. , flag FJ is reset (0) to indicate "no personnel".

Then, after the determination in step 205 or step 208 is NO, after the flag FJ is set in step 207, or after the flag FJ is reset in step 210, steps 211 to 21 are performed.
The process advances to step 4, where the timers TM1 and TM2 are reset, flags FT1 and FT2 are reset, and the process returns to the main routine. As described above, when the state changes from "staffed" to "staffed" or from "staffed" to "staffed", that state is maintained for the predetermined time set by timer TM1 or TM2. .

FIG. 10 is a timing chart showing an example of the operation of determining the presence or absence of personnel in this embodiment.
When the amount of change Dc exceeds a predetermined value
J is set to indicate "personnel available". Then, when the amount of change Dc falls below the predetermined value X at time t3, the timer TM2 starts, and the predetermined time T2 (>T1)
At t4, which has passed and overflowed, the flag FT2 is set, and accordingly the flag FJ is reset and set to a state indicating "no personnel".

Furthermore, even if the amount of change Dc is on the negative side, t5
When the absolute value exceeds the predetermined value X, the timer TM1 is started, and at t6 when the predetermined time T1 has elapsed, the flag FT1 is set, and accordingly the flag FJ is set. When the determination of setting and resetting the flag FJ is completed in this way, the timers TM1 and TM2 and the flags FT1 and FT2 are reset, and the system enters a standby state.

FIG. 11 is a block diagram showing the main internal configuration of the detection circuit IC1, and FIGS. 12 to 15 are a
2 is a timing chart of signals at each point indicated by symbols such as . The detection circuit IC1 has a frequency dividing circuit 10 connected to the oscillation circuit 9 and a timing generation circuit 11 connected thereto. The frequency dividing circuit 10 has a 22-stage frequency dividing function, and outputs a frequency signal whose frequency is divided by a maximum of 1/222 with respect to a clock signal of a predetermined frequency outputted from the oscillation circuit 9. Based on these frequency signals, various timing signals are supplied from the timing generation circuit 11 to each circuit. These frequency dividing circuit 10 and timing generating circuit 11 are constructed of flip-flops as is well known. In addition, T0 to T1 in FIG.
1 indicates that each terminal is connected to a terminal with the same symbol, and does not mean that independent terminals are provided.

A count clock generation circuit 1 outputs capacitance data based on the output clock signal of the oscillation circuit 9.
2. A data counting circuit 13 that counts capacity data 16 times and outputs an average value; a data adding and averaging circuit 14 (hereinafter referred to as adding and averaging circuit 14) that adds the output data of 4 times of this data counting circuit 13 and outputs the average value; ), and has a data output circuit 15 that serially transfers the output data of the averaging circuit 14 in 16 bits from the output port SOT to the determination circuit IC2. Further, a data error check circuit 16 that determines whether the detection signal is correct or not, a data addition number check counter 17 (hereinafter referred to as addition number counter 17), a reset input filter 18 that responds to the reset signal of the judgment circuit IC2, and a signal to the judgment circuit IC2. It includes a data output check circuit 19 that outputs an input permission signal, etc., a dielectric breakdown detection circuit 20 that detects dielectric breakdown, and a dielectric breakdown detection frequency check counter 21 (hereinafter referred to as dielectric breakdown counter 21). Below, these circuits will be explained in order.

[0033] The count clock generation circuit 12 uses the clock signal inputted from the terminal T0 to generate only the first pulse of the output signal (x) of the exclusive OR circuit EOR for each cycle of the reference signal (a). It's something to count,
This pulse is latched by a flip-flop (not shown) and reset immediately before the next input by a reset signal input from terminal T2. That is, there is a delay at the point where each pulse of the reference signal (a) changes, resulting in the signal (x) shown in FIGS. 3 and 13, but only the first pulse of each is counted and may be mixed thereafter. Noise signals and the like are ignored, and a reset signal from the terminal T2 performs a reset in preparation for the next input. Thus, the signal (m) shown in FIG. 13 is supplied to the data count circuit 13. In FIG. 13, the broken lines between the pulses of the signal (m) are shown with the pulses omitted.

The data count circuit 13 is a well-known count circuit composed of flip-flops, and receives the reference signal (a).
The output signal (m) from the count clock generation circuit 12 for 16 out of 32 pulses is counted to obtain a 1/16 average value. That is, as is well known, the lower four digits of the Q output of the flip-flop are discarded and the average value is calculated. The input signal (k) at the terminal T7 is for resetting the counter, and the data count circuit 13 is reset every 32 pulses of the reference signal (a). Note that the output signal from the terminal T10 is an overflow signal.

Next, the averaging circuit 14 has a built-in adder (not shown), and adds the output data from the data count circuit 13 to the previous data every time the signal (g) shown in FIG. 12 is clocked. At the same time, the 1/4 average value of the addition results is determined. An addition counter 17, which will be described later, is connected to the averaging circuit 14, and a signal (g) at the terminal T3 is inputted as a clock signal to the adder via the addition counter 17. Further, the number of additions is counted by the number of additions counter 17, and the number of additions is 4.
The operation of the adder of the averaging circuit 14 is controlled to stop when the number of times reaches the maximum number of times. Further, addition is prohibited via the addition counter 17 in accordance with the detection results of the data error check circuit 16 and the dielectric breakdown detection circuit 20. Then, the signal (n) is input as a reset signal to the averaging circuit 14 via the terminal T8, and is reset every time addition or addition inhibition is executed eight times, and the 1/4 average value of the addition results is output as data. It is output to the circuit 15.

The addition number counter 17 receives the reference signal (a)
It is determined whether or not a normal block has been counted four times until 8 blocks are counted, each block consisting of 16 pulses, and the determination result, the signal from the data error check circuit 16, and the dielectric breakdown detection circuit Depending on the signal from terminal T3, it is selected whether or not to output the signal (g) input from terminal T3 as the clock signal of averaging circuit 14. Therefore, the signals from the data error check circuit 16 and the dielectric breakdown detection circuit 20 are normal (for example, high (H)).
) level), the number of self counters,
That is, when the number of additions is less than 4, the signal (g) is output, and when it is 4 or more, its own counter is reset. At the same time, a signal indicating normality (for example, high (H) level) is output to the data output circuit 15 if the number of additions is 4 or more, and a signal indicating an error (for example, low (L) level) is output.

The data error check circuit 16 is a circuit that checks whether the detected data is correct or not and whether there is an overflow of the data, and a reset signal (k) is inputted from the terminal T7. First, the reference signal (a) and the exclusive OR circuit EO
It is determined whether the two signals are synchronized depending on whether the rising and falling timings of the R output signal (x) match. This determination is made every time the 16 pulses rise and fall, that is, every time the signal (x) becomes low (L) level.
It is reset by . If it is determined that the synchronization is not synchronized even once during this period, the addition number counter 17 is set so that the 16-pulse signal is excluded from the subsequent addition process.
For example, a signal indicating an error (for example, low (L) level) is output. That is, the output signal (v) changes as shown in FIG.

Further, when the Q16 (216) output, that is, an overflow signal is obtained from the adder built in the data count circuit 13, it is input to the data error check circuit 16 via the terminal T10, and the overflow signal is Accordingly, a signal (low (L) level) indicating an error is output to the addition number counter 17. When a signal indicating these errors is output (low (L) level), the signal (g) is not output from the addition number counter 17 and the addition of data in the averaging circuit 14 is prohibited. be done.

The dielectric breakdown detection circuit 20 checks dielectric breakdown at the timing of the signal (f) input from the terminal T9, and when dielectric breakdown occurs, the output signal (u) changes as shown in FIG. (L) level), this is supplied to the dielectric breakdown counter 21, and the number of times dielectric breakdown is detected is counted. The signal (u) is also output to the addition counter 17, so that the addition of data in the averaging circuit 14 is prohibited at the time of dielectric breakdown. Note that the detection result of the dielectric breakdown detection circuit 20 is also reset at a predetermined timing by the signal (k) at the terminal T7.

The dielectric breakdown counter 21 counts the number of dielectric breakdowns detected by the dielectric breakdown detection circuit 20. If dielectric breakdown is detected four times out of eight addition processes, it is determined that dielectric breakdown has occurred, and the data is The state of the output supplied to the output circuit 15 is configured to change in the same manner as the signal indicating the error described above. Therefore, this dielectric breakdown counter 21
In response to a signal indicating dielectric breakdown from the data output circuit 15
It is processed to be output as dielectric breakdown. The specific circuit from the above-mentioned addition counter 17 to the dielectric breakdown counter 21 is as shown in FIG.

The data output circuit 15 has a built-in shift register (not shown), and inputs data from the judgment circuit IC2 to the input port SL.
When a signal instructing to load the data of the addition result to the output shift register is inputted via the circuit, the data of the addition/average circuit 14 is loaded into the shift register all at once in response to this signal. It is configured. Then, a clock signal for operating the shift register is input from the judgment circuit IC2 via the input port SCL, and the loaded data described above is serially output from the output port SOT to the judgment circuit IC2 at each timing of this clock signal. It is configured to

Further, an addition counter 17 and a dielectric breakdown counter 21 are connected to the data output circuit 15, and these output a signal (high (H) level or low (L) level) indicating the presence or absence of a data error and dielectric breakdown. level) is input. Furthermore, an input permission signal is input to the data output circuit 15 from the terminal T11. This input permission signal is output from the data output check circuit 19 (described later) to the determination circuit IC2 via the port INE, and is a signal indicating whether or not the output timing is appropriate. If malfunctioning data is imported,
For example, it is set to a low (L) level, and if the output timing is appropriate, it is set to a high (H) level, for example. Then, the states of these signals are serially transferred to the determination circuit IC2 together with the output data of the data addition circuit 14.

The data output check circuit 19 is a judgment circuit I.
This is to check whether the data has been correctly taken in to the microcomputer of C2. When the input permission signal is outputted via the output port INE and inputted to the judgment circuit IC2, the result is that the data is inputted via the input port END. , it is checked whether the input/output is executed within a predetermined time. That is, the data output check circuit 19 has a terminal T4.
, T5, T7 to the signals (i), (j), (
k) is input, the signal (i) is output as is to the judgment circuit IC2 as an input permission signal, and the signal (j) is used to check whether the data has been correctly taken in to the judgment circuit IC2. , is reset by signal (k). On the other hand, the microcomputer of the judgment circuit IC2 is configured so that data is captured only when a high (H) level input permission signal is input, thereby preventing inappropriate data from being captured into the microcomputer. Ru.

In the data output check circuit 19, even after the input permission signal is output from the input port INE to the determination circuit IC2, the signal indicating the end of input is not output from the input port even after a certain period of time Te shown in FIG. If the signal is not input to END, that is, if it is output at the timing of the signal (i) and the input end signal is not input by the timing of the signal (j), the determination circuit IC2 is determined to be malfunctioning and is reset. As a result, the detection circuit IC in the mutual check function
A check is made on the first side.

The reset input filter 18 is connected to the frequency divider circuit 1.
Ring counter 1 driven by a signal divided by 1/24 of 0
8a, and filter processing is performed on a reset signal input via port RS1. That is, the judgment circuit I
The output when resetting the detection circuit IC1 on the C2 side is input to the port RS1, but at this time, the configuration is such that it is filtered and input so that the reset is not caused by small noise. Note that the reset signal input to port RST is set so that it can be reset in accordance with a general reset operation.

[0046] Thus, the detection circuit IC1 having the above configuration
In this case, 32 pulses are output from the output port SEO.
Sixteen pulses of the periodic signal are output to the sensor Cx as a reference signal. This reference signal is shown in Figure 12 as a signal (
a), and is shown enlarged in FIGS. 3, 4, and 13 to 15. Then, as mentioned above, the sensor Cx
The first comparator CMP1
When the detection signal (c) outputted from is inputted to the input port SEI, it is converted into capacitance data by the count clock generation circuit 12, and counted 16 times by the data count circuit 13, and the average value is determined. That is, the 1/16 average value of the capacitance data counted here becomes the data detected in the above-mentioned one cycle. This one cycle of data detection is repeated eight times, and four of these are detected by the averaging circuit 14.
are added at the timing of the signal (g) in FIG. 12, and a 1/4 average value is obtained.
5 and is serially transferred in 16 bits to the determination circuit IC2 via the output port SOT. The operation of each circuit will be explained below.

First, in the detection circuit IC1, as shown in FIG. ) is determined and the signal (x) is obtained. While this signal (x) is at the low (L) level, it is logically summed with the output clock signal of the oscillation circuit 9, and the resulting signal (m) is used as the clock input of the data count circuit 13.

In the data count circuit 13, the reference signal (
Data for 32 rising and falling times of a) are added to obtain 15-bit data. Of this 15-bit data, the upper 11 bits (16 times average value) are output to the averaging circuit 14. In the averaging circuit 14, the timing of the signal (g) is determined as normal data if both the signal (u) and the signal (v) are at high (H) level, according to the judgment result of the addition counter 17 as to whether the data is normal or not. When the number of additions reaches 4, the subsequent data is ignored and data of 1/4 average value of the addition result is output to the data output circuit 15, indicating that the data is normal. A signal (high (H) level) is output to the data output circuit 15.

Then, the data output circuit 15 outputs the above 1/4 in response to the clock input from the output port OT2 of the determination circuit IC2 to the input port SCL of the detection circuit IC1.
The average capacitance data is transferred from the output port SOT to the judgment circuit I.
It is serially transferred to input port IN3 of C2. That is,
The data is serially transferred from the data output circuit 15 to the determination circuit IC2 using a 16-bit signal. 11 bits out of 16 bits of this serial transfer signal are capacitance data,
Three bits are set according to signals from the addition number counter 17, the dielectric breakdown counter 21, and the terminal T11, respectively.

In the data error check circuit 16, as shown in FIG.
Concerning c), a check is performed at the timing of the signal (h), and if it is detected that noise or the like is mixed in, the operation is performed so that the data is not added. That is, if there is even one error, the data error check circuit 16 removes it and no addition process is performed. Then, if the number of times that addition is prohibited during the 8-time addition process is 4 or more times,
In other words, if the number of additions in the averaging circuit 14 is less than four, it is determined that an error has occurred. Further, as shown in FIG. 15, the dielectric breakdown detection circuit 20 checks the input signal (e) to the input port SEH at the timing of the signal (f). Then, the dielectric breakdown counter 21 counts the number of dielectric breakdown detections, and when the number of detections exceeds four out of eight addition processes, it is determined that a dielectric breakdown state has occurred.

As described above, in this embodiment, the capacity data is averaged 16 times, and if there is even one error in the average, addition is prohibited, and the averaged 16 times is further averaged.
The final capacity data is obtained by adding and averaging a predetermined number of times (four times in this embodiment). At this time, the number of times the first predetermined number of times is subtracted from the second predetermined number of times of 2 or more (in this example, 4 out of 8 times)
(times) When addition is prohibited and data cannot be obtained, it is determined as an error. Furthermore, when the dielectric breakdown state exceeds a predetermined number of times (four times), it is similarly determined that an error has occurred. Thus, false signals are reliably removed.

The above-mentioned person detection device can be used for various controls such as passenger seat airbag control, audio directionality control, seat position control, etc. in a vehicle, and can also be used to control the number of people entering not only a vehicle but also a theater etc. Can be used for counting.

[0053]

[Effects of the Invention] Since the present invention is constructed as described above, it has the following effects. That is, in the person detection device of the present invention, the delayed signal of the detection means is compared in magnitude with the second threshold, and when it is smaller than the second threshold, the first delayed signal to be provided to the determination means is Since the results of the comparison with the threshold are excluded by the exclusion means, for example, even if dielectric breakdown occurs between the electrodes, false signals caused by this can be reliably removed, allowing accurate personnel presence/absence determination. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment of the person detection device of the present invention.

FIG. 3 is a timing chart of signals of various parts of a detection circuit of an embodiment of the person detection device of the present invention.

FIG. 4 is a timing chart of signals of various parts of the detection circuit of one embodiment of the person detection device of the present invention.

FIG. 5 is a timing chart for explaining the operation of the determination circuit of one embodiment of the person detection device of the present invention.

FIG. 6 is a timing chart for explaining the operation of the determination circuit of one embodiment of the person detection device of the present invention.

FIG. 7 is a timing chart for explaining the operation of the determination circuit of one embodiment of the person detection device of the present invention.

FIG. 8 is a flowchart showing the main routine processing in the determination circuit of one embodiment of the person detection device of the present invention.

FIG. 9 is a flowchart showing the process of determining the presence or absence of a person in the determination circuit of the embodiment of the person detection device of the present invention.

FIG. 10 is a timing chart showing the relationship between capacitance data and flubs in the determination circuit of an embodiment of the person detection device of the present invention.

FIG. 11 is a block diagram showing details of a detection circuit of an embodiment of the person detection device of the present invention.

FIG. 12 is a timing chart of signals of each part of the detection circuit of FIG. 11;

13 is a timing chart of the detection circuit in FIG. 11 during normal operation; FIG.

FIG. 14 is a timing chart when the detection circuit of FIG. 11 is out of synchronization.

15 is a timing chart at the time of dielectric breakdown in the detection circuit of FIG. 11. FIG.

16 is a circuit diagram showing a specific configuration of an addition counter and the like in the detection circuit of FIG. 11. FIG.

[Explanation of symbols]

CX Sensor CMP1 First comparator CMP2 Second comparator IC1 Detection circuit IC2 Judgment circuit 2 Body 3 Sheet 4 Electrode 5 External system 9 Oscillation circuit 10 Frequency divider circuit 11 Timing generation circuit 12 Count clock generation circuit 13 Data count circuit 14 Data addition Average circuit 16 Data error check circuit 15 Data output circuit 17 Data addition number check counter 18 Reset input filter 19 Data output check circuit 20 Dielectric breakdown detection circuit

Claims (1)

[Claims] 1. A person detection device that has at least one pair of electrodes and detects a person according to a change in capacitance between the electrodes, wherein a reference signal of a predetermined frequency pulse is supplied to the pair of electrodes. a detection means that charges and discharges every cycle to form a delayed signal; a first comparison means that compares the delayed signal of the detection means with a first threshold value and outputs a comparison result according to the delay time; a second comparing means for comparing the signal with a second threshold value that is larger than the first threshold value and outputting a comparison result; When it is determined that the delayed signal is smaller than the second threshold based on the output of the determining means and the second comparing means, the comparison result of the first comparing means is used in the determining means. A person detection device characterized by comprising: an exclusion means for excluding a person from determining the presence or absence of a person.