JPH04302443A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To avoid an unwired part or an increase in a chip size in an automatic layout operation by a method wherein at least one out of a bonding pad for power-supply use and a bonding pad for grounding use is arranged in a chip corner part in a semiconductor integrated circuit. CONSTITUTION:Bonding pads 3 for power-supply use and bonding pads 2 for grounding use are provided to all corner parts in a semiconductor integrated circuit chip 1. A second-layer-wiring layer 4 on the outermost circumference of the chip is a wiring layer for grounding use; it is connected to the bonding pads 2 for grounding use in four parts in the chip corner parts. A second-layer wiring layer 5 is wiring layer for power-supply use; it is connected to the bonding pads 3 for power-supply use in four parts in the chip corner parts via contact blocks 6 which connect a first-layer wiring layer 7 and a first-layer wiring layer to the second-layer wiring layer. Thereby, it is possible to avoid an unwired part or an increase in a chip size in an automatic layout operation.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits.

0002

[Prior Art] In conventional semiconductor integrated circuits, the number of terminals is as small as 84 pins at most, and the chip size is 9 mm.
Most were four sides or smaller. Therefore, it has been common for a semiconductor integrated circuit to have one or two sets of power supply and ground, which are placed on opposite sides of the chip.

However, in recent years, the degree of integration of semiconductor integrated circuits has been remarkable, and the scale of semiconductor integrated circuits has continued to increase. With the trend toward higher integration, it has become possible to realize a system on a chip by integrating semiconductor integrated circuits in functional units called large-scale cells on one chip. In particular, CPU
Custom LSI called core method is CPU, ROM
, RAM, I/O ports, serial I/O, timers, etc. by combining large-scale cells prepared by LSI manufacturers, and by combining basic gate cells prepared by LSI manufacturers to create user-specific circuits (hereinafter referred to as By designing a user cell (called a user cell) and combining the user cell with a large-scale cell prepared by an LSI manufacturer, users can freely configure a microcomputer that suits their own purpose. (called a custom microcontroller).

[0004] As semiconductor integrated circuits become more highly integrated, on the other hand, as the chip size and the number of terminals increase, the number of power supplies and grounds on semiconductor integrated circuits also increases, and at least four sets or more are required. 2. Description of the Related Art Semiconductor integrated circuits having multiple power supplies and grounds have become commonplace.

[0005]

In the above-described custom microcontroller, connections between large-scale cells, user cells, and external terminals are usually performed by automatic layout. Due to the corner portion of a semiconductor integrated circuit chip, wiring tends to be concentrated in a narrow area due to the corner portion, which causes problems such as unwiring in automatic layout or an increase in chip size.

Furthermore, the chip corner is a place where stress is concentrated due to the difference in thermal expansion coefficient between the semiconductor integrated circuit chip and the resin constituting the semiconductor integrated circuit package when the ambient temperature in which the semiconductor integrated circuit is used increases or decreases. be. This stress increases as the semiconductor integrated circuit chip size increases, and arranging transistors at the corners of the semiconductor integrated circuit chip has the problem of potentially reducing the reliability of the semiconductor integrated circuit.

An object of the present invention is to provide a semiconductor integrated circuit that solves the above problems.

[0008]

[Means for Solving the Problems] In order to achieve the above object, in a semiconductor integrated circuit according to the present invention, at least one of a power supply bonding pad and a grounding bonding pad is arranged at a corner portion of a semiconductor integrated circuit chip. It is something.

[0009]

[Function] The semiconductor integrated circuit of the present invention is provided with a power supply bonding pad or a ground bonding pad at the semiconductor integrated circuit chip corner to avoid unwired lines or an increase in chip size in automatic layout, and This is intended to improve the reliability of integrated circuits.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

(Embodiment 1) FIG. 1 is a mask layout diagram showing Embodiment 1 of the semiconductor integrated circuit of the present invention.

In FIG. 1, a semiconductor integrated circuit chip 1 has bonding pads 3 for power supply and bonding pads 2 for ground at all corners.

The second wiring layer 4 on the outermost periphery of the chip is a ground wiring layer, and is connected to the ground bonding pads 2 at four corners of the chip. Second
The third wiring layer 5 is a power supply wiring layer, and the first wiring layer 7, the first wiring layer and the second wiring layer are connected to each other at the four chip corner parts. It is connected to a power supply bonding pad 3 via a contact block 6 that connects the layers.

(Embodiment 2) FIG. 2 is a mask layout diagram showing a second embodiment of the semiconductor integrated circuit of the present invention.

In the figure, in this embodiment, a power supply bonding pad 3 and a grounding bonding pad 2 are arranged at each corner of a semiconductor integrated circuit chip 1.

The second wiring layer 4 on the outermost periphery of the chip is a ground wiring layer, and is connected to the ground bonding pads 2 at two diagonal corners of the chip. The second wiring layer 5 is a power supply wiring layer, and as expected,
At the two diagonal corners of the chip, the first
It is connected to the power supply bonding pad 3 via the second wiring layer 7 and the contact block 6 that connects the first wiring layer and the second wiring layer.

[0017]

As explained above, according to the present invention, by arranging at least one of a power supply bonding pad and a ground bonding pad at the chip corner of a semiconductor integrated circuit, unwired or chip It is possible to avoid an increase in size. Moreover, it is no longer necessary to place transistors near the chip corners, which improves the reliability of semiconductor integrated circuits.
It will be advantageous.

[Brief explanation of drawings]

FIG. 1 is a mask layout diagram showing a first embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a mask layout diagram showing a second embodiment of the semiconductor integrated circuit of the present invention.

[Explanation of symbols]

1 Semiconductor integrated circuit chip 2 Bonding pad for ground 3 Bonding pad for power supply 4 Wiring layer for ground constituted by the second wiring layer 5 Wiring layer for power supply constituted by the wiring layer of the second layer 6 Second Contact block 7 connecting the first wiring layer and the first wiring layer First wiring layer

Claims (1)

[Claims] [Claim 1] In the semiconductor integrated circuit chip corner part,
A semiconductor integrated circuit characterized in that at least one of a power supply bonding pad and a grounding bonding pad is arranged.