JPH04302175A - Manufacture of semiconductor acceleration sensor - Google Patents

Abstract

PURPOSE:To manufacture an acceleration sensor which is small, lightweight, and high in accuracy by a method wherein four sacrifice layers are formed on a semiconductor substrate, and the sacrifice layers are removed by etching for the formation of a weight, beams, and a stopper. CONSTITUTION:An N<+>-type buried layer 17 is formed on the surface of a P-type substrate 18, and N-type epitaxial layers 19 and 20 are formed thereon. An N<+>-type diffusion 41 is formed on the prescribed region of the N-type epitaxial layer 19, and an N<+>-type diffusion 21 is formed on the prescribed region of the N-type epitaxial layer 20. A piezoelectric resistive element 13 is formed on the surface of the N-type epitaxial layer 20. A nitride film 15 and a PSG film 23 are formed on the N-type epitaxial layer 20, a nitride film 16 is formed on the surfaces of the nitride film 15 and the PSG film 23, and the PSG film 23, the N<+>-type diffusion layers 21 and 41, and the N<+>-type buried layer 17 are removed by etching through an opening 130 provided to the nitride 16. Therefore, a weight 10 and cantilevers 11 and 37 are constituted through a process carried out from one of the surfaces, so that a mask aligning process usually carried out on both the surfaces can be dispensed with and a semiconductor acceleration sensor can be accurately manufactured.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor acceleration sensor and a method of manufacturing the same, and more particularly to a method of manufacturing a semiconductor acceleration sensor formed by etching a semiconductor substrate from one side.

0002

2. Description of the Related Art A conventional acceleration sensor will be explained based on FIGS. 33 and 34. FIG. 33 is a plan view of the acceleration sensor, and FIG. 34 is a cross-sectional view taken along the line XP-XP in FIG. 33. In FIGS. 33 and 34, 1 is a silicon wafer, which is sandwiched between glass plates 2 and 3. A groove 8 is formed in the silicon wafer 1 by etching. Then, the weight 7, the cantilever beam 4, and the support member 9 are integrally formed by the portions that were not etched. Furthermore, a piezoresistive element 5 is formed on the surface of the cantilever beam 4.

[0003] The weight 7 and the support member 9 are made of a silicon wafer 1.
The thickness of the material is used as is. Therefore, recesses 102 and 103 are formed on the surfaces of the glass plates 2 and 3 facing the weight 7 and the cantilever beam 4 so that the weight 7 can move. A resistor 6 constitutes a bridge circuit (not shown) together with the piezoresistive element 5.

Next, the operation will be explained. When acceleration in the direction of arrow A is applied to the above device, the weight 7 is displaced downward due to the acceleration. As a result, the cantilever beam 4 is distorted, and the piezoresistive element 5 is also distorted. Since the resistance value of the piezoresistive element 5 changes when it is distorted, a potential difference occurs in the bridge circuit described above. A change in resistance value is determined based on this potential difference, and acceleration can be detected from the result.

[0005]

In the above-mentioned apparatus, after the silicon wafer 1 is etched from the back side, the piezoresistive element 5 is formed on the front side. Therefore, masks had to be used on both sides, making it difficult to align the masks accurately. Further, when forming the recesses 102 and 103 in the glass plates 2 and 3, alignment had to be performed. Therefore, there was a problem in that it was difficult to form the device with high precision.

Furthermore, if excessive acceleration is applied due to movement of the apparatus after etching the silicon wafer 1 and before attaching the stopper, there is a risk that the beam 4 will be damaged. Furthermore, the thickness of the silicon wafer 1 is set to the thickness of the weight 7 (approximately 300 [μm]) and is used as is.
Further, since the glass plates 2 and 3 were installed on both sides of the silicon wafer 1 as stoppers for the weight 4, there was a problem in that the apparatus became large and the weight increased.

Furthermore, due to the thickness of the adhesive bonding the glass plates 2 and 3 and the silicon wafer 1, the glass plate 2
, 3 and the weight 4, it is difficult to control the gap between the weight 4, air damping is difficult to act, and the detected value is unstable.

The present invention was made to solve the above problems, and by a process from one surface,
The present invention aims to provide a method for manufacturing a small and lightweight semiconductor acceleration sensor.

[0009]

[Means for Solving the Problems] The present invention includes a first step of forming a first sacrificial layer inside a semiconductor substrate, and a step of forming a first sacrificial layer inside a semiconductor substrate, and reaching a region other than a predetermined region on the side of the first sacrificial layer. A second sacrificial layer is formed from the surface of the semiconductor substrate, and a second sacrificial layer is formed from a position at a predetermined depth from the surface of the semiconductor substrate so as to reach the predetermined region. a third step of forming a fourth sacrificial layer on the surface of the semiconductor substrate; a fourth step of forming a stopper layer on the surface of the fourth sacrificial layer; a fifth step of forming an opening; and a sixth step of etching away the fourth sacrificial layer, the third sacrificial layer, the second sacrificial layer, and the first sacrificial layer from the opening. The method is characterized in that a weight, a beam, and a stopper are formed by cavities formed inside and on the surface of the semiconductor substrate.

0010

According to the present invention, a cavity is formed by etching away the first, second, third, and fourth sacrificial layers. Then, of the semiconductor substrate remaining unetched, the region surrounded by the cavity becomes a weight and a beam, and the semiconductor substrate and the stopper layer around the cavity serve as a stopper for the weight. Therefore, the weight of the device can be reduced compared to the case where the stopper is configured by installing a glass plate or the like.

[0011] Also, first, second, third and fourth sacrificial layers,
and the stopper layer are all formed from one surface side of the semiconductor substrate. Therefore, the mask is placed only on the front side of the semiconductor substrate.

0012

Embodiment A first embodiment of the present invention will be described based on FIGS. 1 to 7. FIG. 1 is a plan view showing the sensor portion of this embodiment, and FIG. 2 is a sectional view taken along line XI-XI in FIG. In FIGS. 1 and 2, 10 is a weight, and 11 and 37 are cantilevers.

A piezoresistive element 13 consisting of a P type diffusion layer 22 and P+ type diffusion layers 38, 39, and 40 is formed on the surfaces of the cantilevers 11 and 37. More specifically, a high concentration P+ type diffusion layer 38 is formed in a region of the piezoresistive element 13 above the weight 10. In addition, the P+ type diffusion layer 39
, 40 are pad portions, and the P+ type diffusion layer 40 is connected to a bridge circuit (not shown).

Reference numeral 18 denotes a P-type substrate. On the surface of the P-type substrate 18, an N-type epitaxial growth layer (hereinafter simply referred to as an N-type epitaxial layer) 19 is formed. An N-type epi layer 20 is formed. Note that a semiconductor substrate is formed by the P-type substrate 18, the N-type epitaxial layer 19, and the N-type epitaxial layer 20. Then, a nitride film 15 is selectively formed on the surface of the N-type epitaxial layer 20 with an oxide film 71 interposed therebetween.
A nitride film 16 is formed on the nitride film 15 as a stopper layer. 42 is an oxide film formed around the cavity 12.

12 is a cavity. The cavity 12 is formed by etching away the sacrificial layer formed inside the semiconductor substrate 18, the N-type epitaxial layer 19, and the N-type epitaxial layer 20, and on the surface of the epitaxial layer 20, as will be described later. The remaining portions that are not etched become the weight 10 and the cantilever beams 11 and 37. Further, the nitride film 16 and the semiconductor substrate 18 constitute upper and lower stoppers for the weight 10.

Next, the operation will be explained. Figure 2 for the above device
When an acceleration in the vertical direction is applied, the weight 10 is displaced in accordance with the acceleration. This displacement causes the beams 11 and 37 to become distorted.
The resistance value of the piezoresistive element 13 changes. therefore,
Acceleration is detected by detecting the resistance value of the piezoresistive element 13 using the aforementioned bridge circuit.

Furthermore, since the P+ type diffusion layer 38 of the piezoresistive element 13 is formed on the surface of the weight 10, it is not distorted by the displacement of the weight 10. Therefore, the impurity concentration in this region can be increased, and the influence of the resistance value of the P+ type diffusion layer 38 on the output can be reduced.

When excessive acceleration is applied to the above device, the weight 10 comes into contact with the nitride film 16 or the semiconductor substrate 18. Therefore, even if a large acceleration is applied, the cantilevers 11 and 37 are prevented from being damaged due to increased strain.

Next, the manufacturing method of this embodiment will be explained based on FIGS. 3 to 7. First, as shown in FIG. 3, an N+ type buried layer 17 as a first sacrificial layer is formed on the surface of a P type semiconductor substrate 18. Then, an N-type epitaxial layer 19 is formed on the surface of the N+-type buried layer 17 and the semiconductor substrate 18. Thereafter, an N+ type diffusion layer 41 is formed from the surface of the N type epitaxial layer 19 to the periphery of the N+ type buried layer 17.

Next, as shown in FIG. 4, an N-type epitaxial layer 19 is formed.
An N-type epitaxial layer 20 is formed on the surface of the substrate. Then, the N+ type diffusion layer 21 is selectively formed on the N+ type diffusion layer 41. Note that the P-type substrate 18, the N-type epitaxial layer 19, and the N-type epitaxial layer 2
0 constitutes a semiconductor substrate. In addition, P type substrate 1
8. N type epitaxial layer 2 in which N+ type diffusion layer 21 is not formed
The N+ type diffusion layer 41 below the N+ type diffusion layer 21 constitutes a third sacrifice layer, and the N+ type diffusion layer 41 under the N+ type diffusion layer 21 and the N+ type diffusion layer 21 constitute a second sacrifice layer. .

As shown in FIG. 5, in order to form the piezoresistive element 13, a region on the N+ type diffusion layer 41,
A P-type diffusion layer 22 is formed on the surface of the N-type epitaxial layer 20 where the N+-type diffusion layer 21 is not formed. Then, P+ type diffusion layers 38, 39, and 40 are formed on the surface of the P type diffusion layer 22. After that, the N type epi layer 20, the N+ type diffusion layer 21, the P
A thin oxide film 71 is formed on the surfaces of the type diffusion layer 22 and the P+ type diffusion layers 38, 39, and 40. After that, the oxide film 71
A vaginalized membrane 15 is deposited on the surface of the N+ type buried layer 17.
Nitride film 15 and oxide film 71 on the region where
selectively etched away.

Next, as shown in FIG. 6, an N-type epitaxial layer 2 is formed.
A PSG film 23 as a fourth sacrificial layer is deposited on the surface of the substrate 0 using the nitride film 15 as a mask. After that, nitride film 1
A nitride film 16 is formed on the surfaces of 5 and PSG film 23.

Next, as shown in FIG. 7, openings 130 are provided at predetermined locations in the nitride film 16. And opening 130
PSG by hydrogen fluoride (HF) buffer solution through
The film 23 is removed by etching. Next, hydrogen fluoride, nitric acid (HNO3), and acetic acid (CH3COOH) were mixed in 1:3
Etching is performed through the opening 130 using a solution mixed at a ratio of: :8. This etching depends on the impurity concentration, and the N+ type diffusion layer 4 has a higher impurity concentration than the N type epitaxial layers 19 and 20 and the P type semiconductor substrate 18.
1, the N+ type diffusion layer 21, and the N+ type buried layer 17 are removed. Through the above etching, a cavity 12 is formed, and the N-type epitaxial layers 19 and 20 surrounded by the cavity 12 are attached to the weight 10.
and cantilever beams 11 and 37. Finally, the inside of the cavity 12 is thermally oxidized to form an oxide film 42.

As explained above, according to this embodiment,
An N+ type buried layer 17 is formed on the surface of the P type substrate 18, and an N+ type buried layer 17 is formed on the surface of the P type substrate 18.
N type epi layers 19 and 20 are formed on the + type buried layer 17 and the P type substrate 18 , an N + type diffusion layer 41 is formed in a predetermined region of the N type epi layer 19 , and an N + type diffusion layer 41 is formed in a predetermined region of the N type epi layer 20 . An N+ type diffusion layer 21 is formed, a piezoresistive element 13 is formed on the surface of the N type epi layer 20, a nitride film 15 and a PSG film 23 are formed on the N type epi layer 20, and the nitride film 15 and PSG film 23 are formed on the N type epi layer 20.
A nitride film 16 was formed on the surface of the SG film 23, and the PSG film 23, N+ type diffusion layers 21 and 41, and N+ type buried layer 17 were etched away through an opening 130 provided in the nitride film 16.

Therefore, the weight 10 and the cantilever beams 11, 37 can be formed by a process from one surface,
There is no need to perform mask alignment from both sides, and the device can be manufactured with high precision. Further, since a stopper can also be formed by the above process, it is possible to prevent damage to the device due to excessive acceleration when moving the device during the manufacturing process, resulting in an effect of improving yield. Further, according to the device of the above embodiment, there is no need to newly install a stopper.
The effect is that the device can be made smaller and lighter. Furthermore, since the highly concentrated diffusion layer 38 is formed in the region 39 of the piezoresistive element 13, the detection accuracy can be improved.

Next, a second embodiment will be explained based on FIGS. 8 to 13. In the first embodiment, the amount of displacement of the weight 10 was detected using the piezoresistive element 13, but in this embodiment, the amount of displacement of the weight is detected based on a change in capacitance.

FIG. 8 is a plan view showing the sensor portion of this embodiment, and FIG. 9 is a sectional view taken along the line XII-XII in FIG. In FIGS. 8 and 9, 24 is a weight, and 25 is a cantilever beam. 31 is a P type substrate, and a P+ type buried layer 26 is formed on the surface of the P type substrate 31. An N-type epitaxial layer 32 is formed on the surface of the P+-type buried layer 26. 33 is a P+ type diffusion layer for defining the side wall of the cavity.

A nitride film 35 is selectively formed on the surfaces of the N-type epitaxial layer 32 and the P+ type diffusion layer 33 via an oxide film 72, and a nitride film 28 is formed on the nitride film 35. A P+ type polysilicon layer 29 is formed on the nitride film 28, and a nitride film 30 is formed on the P+ type polysilicon layer 29. P+ type polysilicon layer 29 is one electrode,
The weight 24 becomes the other electrode and constitutes a capacitor. Note that the nitride films 28 and 30 and the P+ type polysilicon layer 29
The upper stopper 27 as a stopper layer is configured by this.

Next, the operation will be explained. Figure 9 for the above device
When an acceleration in the vertical direction is applied, the weight 24 is displaced in accordance with the acceleration. This displacement changes the capacitance between the P+ type polysilicon layer 29 and the weight 24. Therefore, acceleration is detected by detecting this capacitance.

Further, if excessive acceleration is applied to the above device, the weight 24 comes into contact with the upper stopper 27. Therefore, even when a large acceleration is applied, the cantilever beam 24 is prevented from being damaged due to increased strain.

Next, the manufacturing method of this embodiment will be explained based on FIGS. 10 to 13. First, as shown in FIG. 10, a P+ type buried layer 26 is formed on the surface of a P type semiconductor substrate 31. Then, an N-type epitaxial layer 32 is formed on the surface of the P+-type buried layer 26.

Next, as shown in FIG. 11, the N-type epitaxial layer 3
An annular P+ type diffusion layer 33 is formed so as to reach the P+ type buried layer 26 from the surface of the substrate 2. Thereafter, the P+ type diffusion layer 24 is formed inside the P+ type diffusion layer 33 so as not to contact the P+ type buried layer 26. Then, in a predetermined region between the P+ type diffusion layer 24 and the P+ type diffusion layer 33,
A P+ type diffusion layer 25 shallower than the type diffusion layer 24 is formed. Note that the P type substrate 31, the N type epitaxial layer 32, and the P+ type diffusion layers 24, 25, and 33 constitute a semiconductor substrate. Further, the N type epitaxial layer 32 surrounded by the P+ type diffusion layers 24, 25, and 33 becomes a sacrificial layer 32a as the first, second, and third sacrificial layers.

Next, as shown in FIG. 12, the N-type epitaxial layer 3
2, and a thin oxide film 72 is formed on the surfaces of the P+ type diffusion layers 24, 25, and 33. Thereafter, a vaporizing film 35 is formed on the surface of the oxide film 72, and the nitride film 35 and the oxide film 72 on the sacrificial layer 32a are selectively etched away. Next, P
A PSG film 3 as a third sacrificial layer is formed on the + type diffusion layers 24, 25 and the sacrificial layer 32a using the nitride film 35 as a mask.
Deposit 6. After that, the nitride film 35 and the PSG film 3
A nitride film 28, a P-type polysilicon layer 29, and a nitride film 30 are sequentially deposited on the surface of 6.

Next, as shown in FIG. 13, the nitride film 28,
Openings 131 are provided at predetermined locations in upper stopper 27 made of P-type polysilicon layer 29 and nitride film 30. Then, the PSG film 36 is etched away using a hydrogen fluoride buffer solution through the opening 131. Then, potassium hydroxide is applied to the N-type sacrificial layer 32 through the opening 131.
Remove a by etching. Note that this etching is
Stops in +-shaped area. Then, the inside of the cavity formed by etching is oxidized to form an oxide film 73. Through the above manufacturing process, the device of this example is obtained.

As explained above, according to this embodiment,
A P+ type buried layer 26 is formed on the surface of the P type substrate 31,
An N type epitaxial layer 32 is formed on the P+ type buried layer 26, and an N type epitaxial layer 32 is formed on the P+ type buried layer 26.
P+ type diffusion layers 24, 25, 3 are formed in predetermined regions of the type epitaxial layer 32.
3 is formed, and a nitride film 35 and PS
A G film 36 is formed, a nitride film 28, a P-type polysilicon layer 29, and a nitride film 30 are formed on the surfaces of the nitride film 35 and PSG film 36, and the PSG film 36 and sacrificial layer 32a are etched away through the opening 131. I decided to do so.

Therefore, the same effects as in the first embodiment can be obtained, and a semiconductor acceleration sensor using capacitance can be obtained.

Next, based on FIGS. 14 to 21, the third
An example will be described. The structure of this embodiment is almost the same as that of the second embodiment, but differs in that a through hole is formed in the center of the weight and a support is formed between the upper and lower stoppers. FIG. 14 is a plan view showing the sensor portion of this embodiment, and FIG. 15 is a
FIG. Areas similar to those in the second embodiment are given the same numbers and detailed explanations will be omitted. Figure 14
And in FIG. 15, 76 is a weight, and a through hole 44 is formed in the center. 43 is a support, and a through hole 44
It is formed between the upper stopper 27 and the P+ type buried layer 26 through it.

Next, the operation will be explained. Figure 1 for the above device
When an acceleration of 5 is applied in the vertical direction, the weight 76 is displaced in accordance with the acceleration. This displacement changes the capacitance between P+ type polysilicon layer 29 and weight 76. Therefore, acceleration is detected by detecting this capacitance.

Furthermore, the upper stopper 27 is
Since the P+ type buried layer 26 and the P+ type buried layer 26 are supported, it is possible to form a large cavity inside the device. the result,
The weight 76 can be made larger, and the capacitance of the capacitor composed of the weight 76 and the P-type polysilicon layer 29 can also be increased, improving the accuracy of acceleration detection.

Furthermore, when acceleration in a direction parallel to the paper plane of FIG. 14 as shown by arrows B or C is applied to the above-mentioned device, the weight 76 is supported by the column 43. Therefore, damage to the cantilever beam 25 due to acceleration in the above direction is prevented.

Next, the manufacturing method of this embodiment will be explained based on FIGS. 16 to 20. First, as shown in FIG. 16, a P+ type buried layer 26 and an N type epitaxial layer 32 are formed on the surface of a P type semiconductor substrate 31. Then, P+ type diffusion layers 33, 24, and 25 are sequentially formed in the N type epitaxial layer 32. The above steps are similar to the steps shown in FIGS. 10 and 11 in the second embodiment.

Thereafter, as shown in FIG. 17, a P+ type diffusion layer 94 is formed in the center of the P+ type diffusion layer 24 so as to be in contact with the P+ type buried layer 26.

Next, as shown in FIG. 18, a mask is applied to the P+ type diffusion layer 94 excluding the annular portion, and dry etching is performed to form an annular trench having vertical walls. Then, an oxide film 74 is buried in the etched region.

Next, as shown in FIG. 19, the sacrificial layer 32a
, and a thin oxide film 72 is formed on the surfaces of the P+ type diffusion layers 24, 25, and 33. Thereafter, the nitride film 35 and oxide film 72 are selectively deposited on the sacrificial layer 32a and the oxide film 74, and the nitride film 105 is deposited on the pillars 43.

Subsequently, as shown in FIG. 20, nitride films 35 and 1 are formed on the P+ type diffusion layers 24 and 25 and the sacrificial layer 32a.
05 as a mask, a PSG film 36 is deposited. Thereafter, a nitride film 28, a P-type polysilicon layer 29, and a nitride film 30 are sequentially deposited on the surfaces of the nitride films 35, 95 and the PSG film 36.

Next, as shown in FIG. 21, the nitride film 28,
Openings 131 are provided at predetermined locations in upper stopper 27 made of P-type polysilicon layer 29 and nitride film 30. Then, the PSG film 36 is etched away using a hydrogen fluoride buffer solution through the opening 131. Next, the N-type sacrificial layer 32a is removed by etching with potassium hydroxide (KOH) through the opening 131. Note that this etching stops at the P+ type region. Thereafter, the inside of the cavity formed by etching is oxidized to form an oxide film 79. Through the above manufacturing process, the device of this example is obtained.

As explained above, according to this embodiment,
A P+ type buried layer 26 and an N type epitaxial layer 32 are formed on the surface of the P type substrate.
are formed, and P+ type diffusion layers 24, 25,
33 and 94 and vertically etching the P+ type diffusion layer 44 by dry etching, an oxide film 74 is filled, and a vaginalization film 35, a PSG film 36, and an upper stopper 27 are formed on the N type epitaxial layer. , the PSG 36, the sacrificial layer 32a, and the oxide film 74 were etched to form a through hole 44 and a pillar 43 in the weight 76.

Therefore, the same effect as in the second embodiment can be obtained, and the acceleration perpendicular to the support column 43 causes the beam 2 to
5 can be prevented from being damaged, and the durability of the device can be improved. Moreover, the upper stopper 27 and P+
By forming the pillars 43 between the P-type polysilicon layer 26 and the P-type polysilicon layer 26, the area of the capacitor formed by the weight 24 and the P-type polysilicon layer 29 can be increased. As a result, the electrostatic capacitance of the capacitor increases, and the effect of improving the sensitivity for detecting acceleration can be obtained.

Next, based on FIGS. 22 to 32, the fourth
An example will be described. FIG. 22 is a perspective view of a portion of this embodiment excluding the upper stopper, and FIG. 23 is a sectional view taken along line XIV-XIV in FIG. 22. 22 and 23, 45 is a weight, 46, 47, 48, 49, 50
, and 51 are cantilever beams.

Cantilevers 46, 47, 50, and 51 form a piezoresistive element consisting of P-type epilayers 60, 69. Also, cantilevers 46, 47, and 48 are weights 4
It is electrically connected inside 5. The cantilevers 49, 50, and 51 are also electrically connected. Moreover, the cantilevers 48 and 49 are wiring areas for electrically configuring a bridge circuit, which will be described later.

62, 63, 64, 65, 66 and 67
is a P+ type diffusion layer and constitutes a pad. cantilever beam 4
6, 47, 48, 49, 50, and 51 are P+ type diffusion layers 64, 67, 63, 66, respectively, as described later.
, 62, and 65. In addition, a wiring layer (not shown) provides a P+ type diffusion layer 64 and a P+ type diffusion layer 65.
is connected to the power supply voltage VCC, and the P+ type diffusion layer 62 and P
+ type diffusion layer 67 is connected to ground. The P+ type diffusion layers 63 and 66 are connected to the voltage detection section V. Therefore, cantilevers 46, 47, 48, 49,
50 and 51 constitute a bridge circuit as shown in FIG.

In FIG. 23, 54 is an N-type substrate;
A P-type epitaxial layer 60 is formed on the surface of the N-type substrate 54, and a P-type epitaxial layer 69 is further formed on the surface of the P-type epitaxial layer 60. Note that a semiconductor substrate is formed by the N-type substrate 54, the P-type epitaxial layer 60, and the P-type epitaxial layer 69. A nitride film 89 is selectively formed on the surface of the P-type epitaxial layer 69 via an oxide film 88, and a nitride film 91 as a stopper layer is formed on the nitride film 89.

[0053] 93 is a cavity. Cavity 93 is formed by etching away sacrificial layers formed inside and on the surface of N-type substrate 54, P-type epitaxial layer 60, and P-type epitaxial layer 69, as will be described later. And cavity 93
The P-type epitaxial layers 60 and 69 surrounded by the . 92 is the P-type epitaxial layer 60, 69 and N which are in contact with the cavity 93.
This is an oxide film formed on the shaped substrate 54. In addition, the nitride film 9
1 and the N-type substrate 54 constitute a stopper for the weight 10.

Reference numerals 82 and 84 are P+ type diffusion layers for connecting the cantilevers 47 and 46. And N type diffusion layer 96
, 58, 68, 86, and the N+ type diffusion layers 77, 80 are isolated, and the P type epitaxial layers 60, 69 and the P+
The shape diffusion layers 82, 84, 59, 64, and 67 are electrically isolated.

Next, the operation will be explained. When acceleration is applied to the above device and the weight 45 is displaced downward (arrow D in FIG. Force is added. Further, when the weight 45 is displaced in the direction indicated by the arrow E, a tensile force is applied to the cantilevers 46 and 47, and a compressive force is applied to the cantilevers 50 and 51. Therefore, the resistance values of the cantilevers 46, 47, 50, and 51 as piezoresistive elements change, and the acceleration is detected by the aforementioned bridge circuit.

Next, a method of manufacturing the device of this embodiment will be explained based on FIGS. 25 to 32. First, as shown in FIG. 25, an N+ type buried layer 5 is formed on the surface of an N type substrate 54.
5 (corresponding to the first sacrificial layer) and N+ type buried layer 53
form. Then, a P-type epitaxial layer 60 is formed on the surfaces of the N-type substrate 54, the N+-type buried layer 55, and the N+-type buried layer 53.

Next, as shown in FIG. 26, the P-type epitaxial layer 6
A deep N+ type diffusion layer 61 and a shallow N+ type diffusion layer 52 (
(equivalent to the third sacrificial layer) is formed. Further, a deep N+ type diffusion layer 80 is formed so as to be in contact with the N+ type buried layer 53.

As shown in FIG. 27, a low concentration of N is located adjacent to the N+ type diffusion layer 61 and the N+ type diffusion layer 52.
Form diffusion layers 95 and 68 are formed. Then, an N-type diffusion layer 58 is formed around the N-type diffusion layer 68.

Next, as shown in FIG. 28, P+ type diffusion layers 82 and 83 are formed adjacent to the N+ type diffusion layer 52. Further, deep P+ type diffusion layers 56, 57, and 59 are formed at the boundary between the N type diffusion layer 68 and the N+ type diffusion layer 80.

Next, as shown in FIG. 29, the P-type epitaxial layer 6
Another P-type epitaxial layer 69 is formed on the surface of 0. and,
A P+ type diffusion layer 8 is formed on the P type epi layer 69 on the P+ type diffusion layer 82.
form 4. Similarly, P+ type diffusion layers 83, 56
, 57, 59, P+ type diffusion layers 70, 65,
66 and 67 are formed. Furthermore, P+ type diffusion layers 62, 63, 6 which become pad portions are placed at predetermined positions on the N type diffusion layer 68.
form 4.

As shown in FIG. 30, an N+ type diffusion layer 87 is formed in the P type epitaxial layer on the N+ type diffusion layer 61. continue,
An N-type diffusion layer 96 is formed around the P+-type diffusion layers 70 and 84, and an N-type diffusion layer 86 and an N+-type diffusion layer 77 are formed around the P+-type diffusion layers 62, 63, 64, 65, 66, and 67.
form. Note that the N+ type diffusion layers 61 and 87 constitute a second sacrificial layer.

Next, as shown in FIG. 31, the P-type epitaxial layer 6
A thin oxide film 88 is formed on the surface of 9. Thereafter, a nitride film 89 is selectively deposited on the surface of the oxide film 88 in a region where the N+ type buried layer 55 is not formed. Then, a PSG film 90 as a fourth sacrificial layer is deposited on the surface of the P-type epitaxial layer 69 using the nitride film 89 as a mask. After that, a nitride film 9 is formed on the surface of the nitride film 89 and the PSG film 90.
form 1.

Next, as shown in FIG. 32, openings 132 are provided at predetermined locations in the nitride film 91. And opening 13
2, the PSG film 90 is coated with a hydrogen fluoride buffer solution.
Remove by etching. Next, the N+ type diffusion layers 87, 61, 52 and the N+ type buried layer 55 are etched away through the opening 132 using a mixed solution of hydrogen fluoride, nitric acid, and acetic acid. The remaining portions that were not removed by the above etching are the weight 45 and the cantilever beams 46, 47, 48.
, 49, 50, 51. Finally, the inside of the cavity is oxidized to form an oxide film 92.

As described above, according to this embodiment, the P+ type buried layer 55 is formed on the surface of the N type semiconductor substrate 54, and the N type
A P-type epitaxial layer 60 is formed on the surface of the P+-type semiconductor substrate 54 and the P+-type buried layers 55 and 53, a P-type epitaxial layer 69 is formed on the surface of the P-type epitaxial layer 60, and a p-type epitaxial layer 69 is formed on the surface of the P-type epitaxial layer 69. A vaporization film 89 and a PSG film 90 are formed, a vaporization film 91 is formed on the surfaces of the vaporization film 89 and the PSG film 90, and the N+ type diffusion layer formed on the PSG film 90 and the P-type epitaxial layers 60 and 69 is etched. By removing it, the weight 45 and the cantilever beams 46, 47, 48, 49, 50, 51 are formed, and a bridge circuit is formed by the weight 45 and the P+ type diffusion layer formed in the P type epitaxial layer 60, 69. I did it like that.

Therefore, the same effects as in the first embodiment can be obtained. In addition, cantilevers 46, 47, 50, and 51 as piezoresistive elements were arranged at positions that correspond to the vertices of the rectangle, respectively. Therefore, by detecting the tensile force and compressive force applied to each beam, acceleration in two directions can be detected, and there is no need to form thin piezoresistive elements on the beams, making the device more compact. be able to. Further, by forming the six cantilevers close to each other, an effect of improving sensitivity to acceleration in both directions can be obtained.

[0066]

As explained above, according to the present invention, a first sacrificial layer is formed inside a semiconductor substrate, and a second sacrificial layer and a second sacrificial layer are formed on the semiconductor substrate so as to reach the first sacrificial layer. 3
A sacrificial substrate is formed, a fourth sacrificial layer is formed on the surface of the semiconductor substrate, a stopper layer is formed on the surface of the fourth sacrificial layer, and the fourth, third, and third sacrificial layers are formed through the opening provided in the stopper layer. 2
, a cavity is formed by etching and removing the first sacrificial layer, a weight and a beam are formed by the semiconductor substrate in the area surrounded by the cavity, and a stopper for the weight is formed by the semiconductor substrate and the stopper layer around the cavity. I decided to do so.

Therefore, the device can be formed by a semiconductor process from one surface, and the device can be miniaturized and
The effect of being able to reduce the weight can be obtained. Also,
Since the stopper can also be formed by the above process, it is possible to prevent the device from being damaged due to excessive acceleration during the manufacturing process, and the yield can be improved. Furthermore, since the device can be formed with high precision, the gap between the weight and the stopper can be narrowed, and the effect of stabilizing the detected value due to the effect of air damping can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a sensor of a first embodiment.

FIG. 2 is a sectional view of the first embodiment.

FIG. 3 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 8 is a plan view showing a sensor of a second embodiment.

FIG. 9 is a sectional view of the second embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 12 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 13 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 14 is a plan view showing a sensor of a third embodiment.

FIG. 15 is a sectional view of the third embodiment.

FIG. 16 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 17 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 18 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 19 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 20 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 21 is a sectional view showing the manufacturing process of the third embodiment.

FIG. 22 is a perspective view showing a sensor of a fourth embodiment.

FIG. 23 is a sectional view showing a fourth embodiment.

FIG. 24 is a circuit diagram of a fourth embodiment.

FIG. 25 is a cross-sectional view showing the manufacturing process of the fourth example.

FIG. 26 is a cross-sectional view showing the manufacturing process of the fourth example.

FIG. 27 is a cross-sectional view showing the manufacturing process of the fourth example.

FIG. 28 is a cross-sectional view showing the manufacturing process of the fourth example.

FIG. 29 is a cross-sectional view showing the manufacturing process of the fourth example.

FIG. 30 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 31 is a cross-sectional view showing the manufacturing process of the fourth example.

FIG. 32 is a cross-sectional view showing the manufacturing process of the fourth example.

FIG. 33 is a plan view showing a conventional sensor.

FIG. 34 is a sectional view of a conventional example.

[Explanation of symbols]

10 Weight 11 Cantilever beam 12 Cavity 37 Cantilever beam 18 P type board 19 N type epi layer 20 N type epi layer 16 Vaginalized membrane 17 N+ type buried layer 21 N+ type diffusion layer 41 N+ type diffusion layer 23 PSG film

Claims (1)

[Claims] 1. A first step of forming a first sacrificial layer inside a semiconductor substrate; a second step of forming a second sacrificial layer from a position at a predetermined depth from the surface of the semiconductor substrate so as to reach the predetermined region; a third step of forming a fourth sacrificial layer thereon;
a fourth step of forming a stopper layer on the surface of the fourth sacrificial layer; a fifth step of forming an opening at a predetermined position of the stopper layer; a sixth step of etching away the third sacrificial layer, the second sacrificial layer, and the first sacrificial layer; A method of manufacturing a semiconductor acceleration sensor, comprising forming a stopper.