JPH04296933A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the wiring delay of e carry generating route and to increase the working speed for an arithmetic circuit of an adder containing a carry look-ahead circuit. CONSTITUTION:An arithmetic circuit contains a carry look-ahead circuit 6a and a propagation signal generating circuit 61 which produces a propagation signal to control the propagation of a carry signal in such a ray out where the circuit 6a is set adjacent to the circuit 61. In such a constitution, a wiring is shortened for the propagation signal to be inputted to the circuit 6a so that the wiring delay can be reduced. Thus it is possible to avoid the reduction of the working speed of the arithmetic circuit despite the small width of a layout area of the circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an arithmetic processing function such as a microprocessor, and more particularly to a layout structure of an arithmetic unit equipped with a carry lookahead circuit for anticipating carry output. be.

0002

2. Description of the Related Art First, an example of the technical background for explaining the prior art will be described with reference to FIG. As shown in FIG. 3, when performing arithmetic processing on the outputs of the two memories 1A and 1B, (1) regularity cannot be ensured in the layout design, and (2) from each memory 1A and memory 1B to the arithmetic unit 6, The design needed to solve problems such as an increase in layout area due to longer wiring and a decrease in processing speed due to wiring delays. In order to solve these problems, a plurality of memory cell groups are alternately arranged adjacent to each other in each bit array, and this is configured as one memory cell array, and each bit of the arithmetic unit corresponds to each bit array position of the memory cell. There is one that places the . This technology will be described in further detail below with reference to FIG. 4 showing the layout configuration of this technology.

In FIG. 4, 1 indicates two types of memory cell groups A.
A memory cell array in which 0 to An-1, B0 to Bn-1 are arranged alternately for each bit string, and memory cell groups A0 to An
-1 is a memory cell group B0 to memory cell group B0 to memory 1A shown in FIG.
Bn-1 corresponds to memory 1B shown in FIG. Reference numeral 2 denotes an input circuit corresponding to this memory cell array 1, which is used to input data to the memory cells in the memory cell array 1. Reference numeral 3 denotes an output circuit corresponding to the memory cell array 1, which is used to output data read from the memory cells in the memory cell array 1. 4 and 5 are two types of memory cell groups A0 to An that constitute the memory cell array 1.
-1, B0 to Bn-1, and one address decoder 4
corresponds to one memory cell group A0 to An-1, and the other address decoder 5 corresponds to another memory cell group B0 to Bn-1.
corresponds to each. 6 is an arithmetic circuit, that is, an adder circuit, consisting of full adders FA0 to FAn-1 that calculate the respective outputs of these two types of memory cell groups A0 to An-1 and B0 to Bn-1; 7 is an adder circuit that operates this adder circuit 6 at high speed. This is a carry lookahead circuit for operation.

Next, the operation of this circuit will be explained. Assume now that data is stored in the memory cell array 1. First, the address value AD is input to each address decoder 4 and 5.
When A and ADB are given, these address inputs are each decoded, and n-bit memory cells corresponding to the address value ADA are transferred from the memory cell group A0 to An-1 to the address value A.
The n-bit memory cells corresponding to DB are memory cell group B.
Selected from 0 to Bn-1. Next, when a read signal is applied to the memory cell array 1, the data stored in the selected memory cell is outputted via the output circuit 3.

At this time, the data read from the memory cell selected by the address value ADA and output from the output circuit 3 is read from the memory cell selected by the address value ADB and output from the output circuit 3. The data obtained is set as OB. These output data OA and OB are each outputted to the outside, and at the same time, they are supplied to an adder circuit 6 for calculation, and outputted to the outside as output data OS. However, in order to meet the recent demand for higher speed semiconductor integrated circuits, a carry lookahead circuit 7 is added to the adder circuit 6. The layout of a conventional calculation (addition) circuit will be described below based on the technology of reading two types of data from the memory cell array 1 and performing calculations (additions) using the two types of data as input as described above.

FIG. 4 shows a layout configuration of an adder circuit incorporating a conventional carry lookahead circuit. Here, the adder circuit 6 uses a plurality of full adders corresponding to a plurality of bits, and each full adder will be explained using a Manchester type full adder. In other words, as shown in FIG. 5, this circuit inputs two signals X and Y that are addition and augend signals, and generates a propagation signal that determines whether or not to propagate the carry input Ci, which is a carry signal, to the carry output. A first logic section is made up of an EXOR (exclusive OR) circuit 61 that generates P, and a second logic section is made up of an AND circuit 62 that also receives two signals X and Y and generates a generate signal G for generating a carry output. a third logic section consisting of a selection circuit 63 that selects whether to output the carry input signal Ci as a carry output Co or output the output signal of the AND circuit 62 according to the propagation gate signal P; (sum) and a fourth logic section consisting of an EXOR circuit 64 that generates an output S. At this time, the selection circuit 63 includes an AND circuit 631 and an OR circuit 632.
Consisting of

FIG. 6 shows an example of a parallel addition circuit using a carry lookahead circuit. As shown in the figure, the adder circuit 6 is divided into full adders FA for every 4 bits, and the carry lookahead circuit 6a uses the propagate signal P (P4i to P4i+3) of each full adder FA for 4 bits.
) is input, and the AND output of the propagation gate signal P allows the carry input Ci of the 4 least significant bits or the carry output Co of the full adder FA of the 4 most significant bits to be sent to the multiplexer ( MUX
) 72 to generate a carry signal to the higher order.

In the figure, X4i to X4i+3 represent signals input to each 4-bit full adder FA, and Y4i to Y4i+
Similarly, reference numeral 3 indicates a signal input to each full adder FA. Also, Ci is the carry input of the lower bit, and S
4i to S4i+3 indicate the sum output of each full adder FA.

In the case of the above logic circuit, the conventional layout configuration is as shown in FIG. That is, full adder F
A is each signal X4i to X4i+3, Y4i to Y4i+
3 as an input, and an EXOR circuit 61 as a propagation signal generation circuit that generates a propagation signal P, and an AN that generates a generate signal G for generating a carry output.
A D circuit 62, a selection circuit 63 that generates a carry output signal Co, and an EXOR circuit 64 that generates a sum output signal S are laid out at one end of the memory cell array 1 in this order. And the full adder FA has inputs X4i to X4i+3, Y4i
~Y4i+3 is laid out in parallel, and an adder circuit 6 is formed. In addition, carry lookahead circuit 7
is added to every 4 bits of the full adder, and the layout of the adder circuit 6 is arranged adjacent to the output circuit 3 of the memory as shown in FIG. 4 described above. Therefore, for an area-efficient layout, the layout width of the full adder should be the width of the memory bit string (for example, A0
, B0).

[0010] At this time, the width of the memory cell column is often short, and the width of the full adder that matches this width also becomes narrow, resulting in an elongated layout. However, the wiring length of the propagation signal P, which is the input signal to the carry lookahead circuit 7, on the layout becomes longer as the full adder becomes elongated in layout, and the wiring delay increases. The operating speed of the adder circuit depends on the carry propagation speed, and the propagation signal P, which is the input signal of the carry lookahead circuit to generate the carry signal at high speed,
The delay causes a decrease in the operating speed of the adder circuit.

[0011]

[Problems to be Solved by the Invention] In this way, in the layout of a conventional adder, the circuit that generates the propagation signal and the carry lookahead circuit are configured to be separated from each other. The wiring to input becomes long, causing a delay. As a result, carry propagation delay increases, resulting in problems such as a decrease in the operating speed of the adder.

The present invention has been made to solve the above-mentioned problems, and it is possible to reduce the wiring delay of the carry generation path in an arithmetic circuit such as an adder equipped with a carry lookahead circuit, thereby increasing the speed. The purpose of this invention is to obtain a semiconductor integrated circuit device that makes it possible.

[0013]

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes a carry lookahead circuit for anticipating carry output, and a propagation signal generation circuit for generating a propagation signal for controlling the propagation of the carry signal. The carry lookahead circuit is arranged adjacent to the propagation signal generation circuit.

[0014]

According to the present invention, the wiring of the propagation signal path can be shortened by arranging the propagation signal generation circuit and the carry lookahead circuit adjacent to each other, thereby reducing the wiring delay. As a result, even if the width of the layout area of the arithmetic circuit is narrow, the operating speed of the circuit does not decrease.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a memory circuit incorporating a layout of an adder circuit according to an embodiment of the present invention. In the figure, 1 indicates two types of memory cell groups AO to An-1,
A memory cell array in which B0 to Bn-1 are arranged alternately for each bit string, 2 an input circuit corresponding to this memory cell array 1, 3 an output circuit corresponding to the memory cell array 1,
4 and 5 are address decoders for selecting arbitrary memory cells from the two types of memory cell groups AO to An-1 and B0 to Bn-1 constituting the memory cell array 1, and 6 is the two types of memory cell groups AO. This is an addition circuit consisting of a full adder that adds the outputs of ~An-1 and B0 to Bn-1. Here, the structure of the memory portion is the same as that described in the section of the prior art.

The layout of the adder circuit, which is a feature of the present invention, will be explained in detail below with reference to FIG. Figure 2
1 is a layout configuration diagram of an adder circuit according to the present invention. Here, as each full adder FA constituting the adder circuit 6, a Manchester type one shown in FIG. 5, for example, will be used for explanation. As shown in FIG. 5, this full adder FA is a propagation gate that receives two signals X and Y as input, performs a logical operation on these two signals, and determines whether or not to propagate the carry input Ci to the carry output. A propagation signal generation circuit 61 is a first logic section consisting of an EXOR circuit that generates a signal P, and a generator for generating a carry output by performing a logical operation on these two signals using the same two signals X and Y as input. A generate signal generating section 62, which is a second logic section consisting of an AND circuit that generates a rate signal G, and a propagation signal P, propagates the carry input signal as a carry output Co, or outputs the generate signal G. A third logic section includes a selection circuit 63 for selecting the output signal S, and a fourth logic section 64 includes an EXOR circuit for generating the sum output signal S. A carry look ahead circuit 6a is added for every 4 bits of the full adder FA.

In this embodiment, as shown in FIG. 2, the adder circuit 6 is divided into full adders FA for every 4 bits, and the carry lookahead circuit 6a is similar to the circuit shown in FIG. 6 described above.
The propagate signal P(P
4i to P4i+3) selects the carry input Ci of the least significant bit of the 4 bits or the carry output Co of the full adder FA of the most significant bit of the 4 bits, and generates a carry signal to the upper side. ing. As a layout configuration, the carry lookahead circuit 6
A is arranged adjacent to a propagation signal generation circuit 61 that generates a propagation signal P. That is, the adder circuit 6 is divided into a first block consisting of a propagation signal generation circuit 61 and a second block consisting of a generate signal generator 62, a selection circuit 63, and an output signal generator 64, and the adder circuit 6 A carry lookahead circuit 6a is disposed between the first block and the second block. Note that the same reference numerals in the figures indicate the same or corresponding parts.

As described above, according to the adder circuit configured in the above embodiment, the carry lookahead circuit 6a is replaced by the full adder FA.
By arranging it adjacent to the propagation signal generation circuit 61, the wiring from the propagation signal output of the full adder to the propagation signal input to the carry lookahead circuit 6a becomes short. Therefore, the wiring delay of the carry generation path is reduced, and the speed of the adder circuit can be increased.

In the above embodiment, the output of the memory is used as the input of the adder circuit, but the input is of course not limited to the output of the memory. Further, in the above embodiment, an example of an adder is shown, but the present invention is not limited to this, and the same effect can be obtained by any device using a carry look-ahead circuit such as a subtracter or an ALU. Also, any Manchester-type adder circuit can produce the same effect. In addition, in the above embodiment, the full adder is 4
Although an example has been shown in which the bits of the full adder are divided and a carry lookahead circuit is added, the bits of the full adder may be divided into any number of bits, and the same effect can be obtained by any method.

In short, in the present invention, a first signal consisting of a plurality of bits and a second signal consisting of a plurality of bits are input, and a logic means is provided for each corresponding bit in these first and second signals. , an arithmetic circuit that performs a logical operation on the first and second signals and outputs the arithmetic result, and a carry lookahead circuit that receives signals from each logic means in the arithmetic circuit and operates the arithmetic circuit at high speed. At least a plurality of logic sections in each logic means of the arithmetic circuit are divided into two blocks, and a carry lookahead circuit is arranged between the two divided blocks.

[0021]

[Effects of the Invention] As described above, according to the present invention, the propagation signal generation circuit and the carry lookahead circuit are placed adjacent to each other in the layout of the adder, so the propagation signal wiring is shortened and the wiring delay is reduced. This has the effect of providing a high-speed arithmetic device such as an adder.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a memory circuit incorporating the layout of an adder circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed example of the layout of an adder circuit in the embodiment of FIG. 1;

FIG. 3 is an explanatory diagram showing a technique for calculating the outputs of two memory circuits.

FIG. 4 is a schematic diagram showing a memory circuit incorporating a layout of an adder circuit for explaining the conventional technical background.

FIG. 5 is a configuration diagram showing an example of a normal full adder.

FIG. 6 is a configuration diagram showing an adder circuit including a carry lookahead circuit.

FIG. 7 is a diagram showing details of the layout of the adder circuit in FIG. 4;

[Explanation of symbols]

6 Addition circuit (arithmetic circuit) 6a Carry lookahead circuit 61 Propagate signal generation circuit (EXOR circuit) 6
2 AND circuit 63 selection circuit

Claims (1)

[Claims] 1. An arithmetic circuit comprising a carry lookahead circuit for anticipating a carry output and a propagation circuit for generating a propagation signal for controlling propagation of the carry signal, the carry lookahead circuit comprising: A semiconductor integrated circuit device characterized by having a layout configuration in which the propagation signal generation circuit and the propagation signal generation circuit are arranged adjacent to each other.