JPH04296723A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04296723A JPH04296723A JP3062180A JP6218091A JPH04296723A JP H04296723 A JPH04296723 A JP H04296723A JP 3062180 A JP3062180 A JP 3062180A JP 6218091 A JP6218091 A JP 6218091A JP H04296723 A JPH04296723 A JP H04296723A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- electrode
- crystal driving
- metal bump
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000003825 pressing Methods 0.000 claims abstract description 12
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 39
- 239000000758 substrate Substances 0.000 abstract description 27
- 229910052782 aluminium Inorganic materials 0.000 abstract description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 15
- 238000007747 plating Methods 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 description 39
- 239000002184 metal Substances 0.000 description 39
- 239000002245 particle Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 24
- 239000010408 film Substances 0.000 description 13
- 239000011521 glass Substances 0.000 description 13
- 239000012790 adhesive layer Substances 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 7
- 239000011295 pitch Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910020174 Pb-In Inorganic materials 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009863 impact test Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【0001】〔発明の目的〕[Object of the invention]
【0002】0002
【産業上の利用分野】本発明は、半導体素子の複数の電
極を基板上の電極に、確実に電気的に接続する半導体装
置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a plurality of electrodes of a semiconductor element are reliably electrically connected to electrodes on a substrate.
【0003】0003
【従来の技術】一般に、半導体素子を基板に実装した電
子装置で、半導体素子を実装する方法として、半導体素
子上の金属バンプ電極と基板上の電極とを直接接続する
フェイスダウンボンディング法が知られている。[Prior Art] Generally, in electronic devices in which a semiconductor element is mounted on a substrate, a face-down bonding method is known as a method for mounting the semiconductor element, in which a metal bump electrode on the semiconductor element is directly connected to an electrode on the substrate. ing.
【0004】そして、接続材料として導電性微片が含ま
れた異方性導電膜を用いて電気的に接続することにより
、低コストで高密度実装を実現する方法が、たとえば特
公昭62−6652号公報に記載されている。[0004] A method of realizing high-density packaging at low cost by electrically connecting using an anisotropic conductive film containing conductive particles as a connection material was proposed, for example, in Japanese Patent Publication No. 62-6652. It is stated in the No.
【0005】この特公昭62−6652号公報に記載さ
れている構成は、たとえば図6に示すように、上面にエ
ッチング等で形成された電極である導電リード層1が形
成されたリジットまたはフレキシブルな基板2と、この
基板2の導電リード層1上に配置され、絶縁性を有する
接着剤3中に導電性微片としての導電粒子4が混入分散
され、厚み方向に導電性を有し面方向に絶縁性を有する
異方性導電接着剤層5と、この異方性導電接着剤層5上
に配置固定され、下面に形成されたパッド6が形成され
た半導体素子7とを備えている。そして、基板2と半導
体素子7との間に、異方性導電接着剤層5を介挿させ、
基板2と半導体素子7とを接着するとともに導電リード
層1とパッド6とを導電粒子4により電気的に接続する
。The structure described in Japanese Patent Publication No. 62-6652 is, for example, as shown in FIG. Conductive particles 4 as conductive particles are mixed and dispersed in an insulating adhesive 3 disposed on a substrate 2 and a conductive lead layer 1 of this substrate 2, and have conductivity in the thickness direction and in the surface direction. The semiconductor device 7 includes an anisotropic conductive adhesive layer 5 having an insulating property, and a semiconductor element 7 which is placed and fixed on the anisotropic conductive adhesive layer 5 and has a pad 6 formed on its lower surface. Then, an anisotropic conductive adhesive layer 5 is inserted between the substrate 2 and the semiconductor element 7,
The substrate 2 and the semiconductor element 7 are bonded together, and the conductive lead layer 1 and the pad 6 are electrically connected by the conductive particles 4.
【0006】また、接続の歩留まりを高くするために、
半導体素子7のパッド6上には、多くの場合、金属バン
プ電極8が図7および図8に示すように形成されている
ものの、これら金属バンプ電極8の高さは必ずしも一様
ではない。これらの金属バンプ電極8は通常金属からな
り、メッキ法により形成される場合が多く、たとえば図
5に示すような半導体素子としての出力数160の液晶
駆動用IC11の場合には、電極突起数はたとえば18
4であり、高さ18μmの金属バンプ電極8の高さは、
通常約6μmの高低差がある。[0006] Furthermore, in order to increase the yield of connections,
Although metal bump electrodes 8 are often formed on the pads 6 of the semiconductor element 7 as shown in FIGS. 7 and 8, the heights of these metal bump electrodes 8 are not necessarily uniform. These metal bump electrodes 8 are usually made of metal and are often formed by a plating method. For example, in the case of a liquid crystal driving IC 11 with an output number of 160 as a semiconductor element as shown in FIG. 5, the number of electrode protrusions is For example 18
4, and the height of the metal bump electrode 8 with a height of 18 μm is
There is usually a height difference of about 6 μm.
【0007】[0007]
【発明が解決しようとする課題】したがって、導電粒子
4の粒子径が約2μmから5μmである異方性導電接着
剤層5を用いて接続を行なうと、図9に示すように、高
さの高い金属バンプ電極8においては良好な接続がなさ
れるが、高さの低い金属バンプ電極8の個所においては
、導電粒子4が金属バンプ電極8および配線電極1とは
接触せず、電気的にオープンが発生するということが生
ずる。[Problems to be Solved by the Invention] Therefore, when a connection is made using an anisotropic conductive adhesive layer 5 in which the conductive particles 4 have a particle diameter of about 2 μm to 5 μm, the height increases as shown in FIG. A good connection is made at the high metal bump electrode 8, but at the low height metal bump electrode 8, the conductive particles 4 do not come into contact with the metal bump electrode 8 and the wiring electrode 1, resulting in an electrical open. occurs.
【0008】そこで、図10に示すように、粒子径の大
きい導電粒子を用いれば、高低差のある金属バンプ電極
8のいずれに対しても良好な接続がなされることが考え
られる。導電粒子4に粒子径が約10μm(±1.5μ
m)の異方性導電接着剤層5を用い接続実験を行なった
ところ、電気的にオープンが発生することがなくなった
。なお、導電粒子4の粒子径の範囲は、たとえば、6μ
mから20μmの範囲で効果がある。Therefore, as shown in FIG. 10, if conductive particles with a large particle size are used, it is possible to make a good connection to any of the metal bump electrodes 8 having different heights. The conductive particles 4 have a particle diameter of approximately 10 μm (±1.5 μm).
When a connection experiment was conducted using the anisotropic conductive adhesive layer 5 of m), no electrical open occurred. Note that the particle diameter range of the conductive particles 4 is, for example, 6μ.
It is effective in the range from m to 20 μm.
【0009】しかしながら、半導体素子であるたとえば
液晶駆動用IC7は、液晶デバイスの高精細化の進展と
ともに接続する金属バンプ電極8が増え、接続ピッチも
さらに微細化が進んでいる。[0009] However, in semiconductor elements such as the liquid crystal driving IC 7, as the definition of liquid crystal devices progresses, the number of metal bump electrodes 8 to be connected is increasing, and the connection pitch is also becoming finer.
【0010】したがって、高低差のある金属バンプ電極
8に対して大きい導電粒子4を用いたとき良好な接続が
なされるのであるが、接続ピッチが狭く隣合うバンプ間
隔が小さい半導体素子7の接続に用いると、金属バンプ
電極8間でショートが生じ易くなる。したがって、金属
バンプ電極8がある接続ピッチ以下になると大きい導電
粒子4を用いることができなくなる問題を有している。Therefore, good connections are made when large conductive particles 4 are used for metal bump electrodes 8 with height differences, but it is difficult to connect semiconductor elements 7 with narrow connection pitches and small spacing between adjacent bumps. If used, short circuits are likely to occur between the metal bump electrodes 8. Therefore, there is a problem in that when the metal bump electrodes 8 fall below a certain connection pitch, large conductive particles 4 cannot be used.
【0011】本発明は上記問題点に鑑みなされたもので
、フェイスダウンボンディング法において、微細ピッチ
で高低差のある電極突起に対しても良好な接続がなされ
、隣合う電極間でショートが生じにくい高信頼性・高歩
留まりの半導体素子の製造方法を提供することを目的と
する。The present invention was developed in view of the above-mentioned problems, and in the face-down bonding method, a good connection can be made even to electrode protrusions with fine pitches and height differences, and short circuits are less likely to occur between adjacent electrodes. The purpose is to provide a method for manufacturing semiconductor devices with high reliability and high yield.
【0012】〔発明の構成〕[Configuration of the invention]
【0013】[0013]
【課題を解決するための手段】本発明の半導体素子の製
造方法は、半導体素子上に形成された電極突起を、加圧
面が平坦でかつ190℃以上550℃以下の温度に加熱
された治具で押圧し、この半導体素子内での前記電極突
起の高さを均一化するものである。[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention uses a jig having a flat pressurizing surface and heated to a temperature of 190° C. or more and 550° C. or less. The height of the electrode projections within the semiconductor element is made uniform by pressing the electrode projections.
【0014】[0014]
【作用】本発明は、半導体素子上に形成された電極突起
を、加圧面が平坦で、かつ、接続時に生ずる温度である
190℃以上の温度で、また、半導体素子を破壊しない
温度である550℃以下の温度に加熱された治具で押圧
し、この半導体素子内での前記電極突起の高さを均一化
する。[Function] The present invention allows electrode protrusions formed on a semiconductor element to be pressed at a flat pressure surface and at a temperature of 190°C or higher, which is the temperature that occurs during connection, and at a temperature of 550°C, which is a temperature that does not destroy the semiconductor element. Pressing is performed with a jig heated to a temperature of 0.degree. C. or less to equalize the height of the electrode protrusions within the semiconductor element.
【0015】[0015]
【実施例】以下、本発明の一実施例を図面を参照して説
明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【0016】図1ないし図5において、11は半導体素
子である出力数160の液晶駆動用IC11で、およそ
5mm×9mmのサイズである。そして、液晶駆動用I
C11の表面にはアルミニウム電極12とこのアルミニ
ウム電極12の上面には、たとえば、チタン(Ti)、
ニッケル(Ni)、金(Au)の順序で構成された図示
しないバリアメタル層が形成されている。このバリアメ
タル層の上には、たとえば金(Au) よりなる電極突
起としての金属バンプ電極13がメッキ法などによって
形成されている。In FIGS. 1 to 5, reference numeral 11 denotes a liquid crystal driving IC 11, which is a semiconductor element and has 160 outputs, and has a size of approximately 5 mm×9 mm. And I for liquid crystal drive
On the surface of C11 is an aluminum electrode 12, and on the upper surface of this aluminum electrode 12, for example, titanium (Ti),
A barrier metal layer (not shown) made of nickel (Ni) and gold (Au) in this order is formed. On this barrier metal layer, a metal bump electrode 13 as an electrode projection made of, for example, gold (Au) is formed by a plating method or the like.
【0017】また、たとえば上記出力数160の液晶駆
動用IC11の場合には、金属バンプ電極13は、たと
えば184あり、大きさは約60μm角で、接続ピッチ
は100μmで、金属バンプ電極13の平均高さは18
μmで、通常約6μmの高低差がある。For example, in the case of the liquid crystal driving IC 11 having 160 outputs, the number of metal bump electrodes 13 is, for example, 184, the size is about 60 μm square, the connection pitch is 100 μm, and the average of the metal bump electrodes 13 is approximately 60 μm square. The height is 18
There is usually a height difference of about 6 μm.
【0018】この状態で、図1(a) に示すように加
圧面15が平坦な加熱した加圧治具16で液晶駆動用I
C11の上方から、矢印Pの方向へ、温度400℃〜5
50℃、加圧力50〜150kg/pad、加圧時間1
.0秒の条件で、液晶駆動用IC11上に形成された金
属バンプ電極13を押圧したところ、初期高さの平均値
が18μm、最大値が20μm、最小値が14μmであ
ったものが、加圧後の高さは、図1(b) に示すよう
に、平均値およそ14μm、最大値が14μm、最小値
が13μmとなる。In this state, as shown in FIG. 1(a), a heated pressing jig 16 with a flat pressing surface 15 is used to press the liquid crystal driving I.
From above C11 in the direction of arrow P, temperature 400℃~5
50℃, pressure 50-150kg/pad, pressure time 1
.. When the metal bump electrode 13 formed on the liquid crystal driving IC 11 was pressed for 0 seconds, the average initial height was 18 μm, the maximum value was 20 μm, and the minimum value was 14 μm. As shown in FIG. 1(b), the subsequent height has an average value of approximately 14 μm, a maximum value of 14 μm, and a minimum value of 13 μm.
【0019】なお、上記条件で加圧を加えても液晶駆動
用IC11の動作不良は、まったく生じていない。また
、加圧力は金属バンプ電極13のサイズ、数、硬度さら
に形成された条件によって異なり、適宜決定される。Note that even when pressurization was applied under the above conditions, no malfunction of the liquid crystal driving IC 11 occurred at all. Further, the pressing force varies depending on the size, number, hardness, and conditions under which the metal bump electrodes 13 are formed, and is determined as appropriate.
【0020】また、異方性導電膜を用いた接続の場合、
液晶駆動用IC11接続時の温度が190℃に達するの
で、190℃以上の温度で加圧するとき有効であり、加
圧時の温度は550℃を超えると、金属バンプ電極13
の材質にかかわらず、半導体に損傷が生じる確率が高い
ので550℃以下の温度に制御する必要がある。たとえ
ばメッキ形成された金(Au)製の金属バンプ電極13
の高低を十分に均一化するためには、加圧温度を少なく
とも400℃以上に上げなくてはならない。実験によれ
ば、室温での加圧では150kg/padの加圧力を加
えても2μmしか潰れず、十分な均一化ができず、さら
に、加圧力を増してもこれ以上変形しなかった。[0020] Furthermore, in the case of connection using an anisotropic conductive film,
Since the temperature when the liquid crystal driving IC 11 is connected reaches 190°C, it is effective when applying pressure at a temperature of 190°C or higher. If the temperature during pressurization exceeds 550°C, the metal bump electrode 13
Regardless of the material, there is a high probability that the semiconductor will be damaged, so it is necessary to control the temperature to 550° C. or lower. For example, a metal bump electrode 13 made of plated gold (Au)
In order to sufficiently equalize the height of the pressure, the pressurizing temperature must be raised to at least 400°C or higher. According to experiments, when pressurized at room temperature, even if a pressure of 150 kg/pad was applied, the material could only be crushed by 2 μm, and sufficient uniformity could not be achieved.Furthermore, even if the pressure was increased, no further deformation occurred.
【0021】さらに、加圧治具16は、コストおよび寿
命の点から、高融点金属の合金たとえばモリブデン(M
o)合金を母材とし、加圧面15には、耐衝撃性、耐熱
性の高い材料たとえば人工ダイヤモンドをろう付けした
ものを用いる。さらに、粒子径約2μmから5μmであ
る微細ピッチ接続に適した異方性導電膜を用いる場合、
加圧治具16の加圧面15の平坦度を±0.5μm以内
に押さえることが望ましい。Further, from the viewpoint of cost and life, the pressurizing jig 16 is made of a high-melting point metal alloy such as molybdenum (M
o) The base material is an alloy, and the pressurizing surface 15 is made of a material with high impact resistance and heat resistance, such as artificial diamond, brazed to it. Furthermore, when using an anisotropic conductive film suitable for fine pitch connections with a particle diameter of about 2 μm to 5 μm,
It is desirable to keep the flatness of the pressing surface 15 of the pressing jig 16 within ±0.5 μm.
【0022】また、液晶駆動用IC11の上面には、ア
ルミニウム電極12の上面の一部をも被覆する窒化シリ
コン(SiN) などからなる保護用のパッシベーショ
ン膜14が形成されている。Furthermore, a protective passivation film 14 made of silicon nitride (SiN) or the like is formed on the upper surface of the liquid crystal driving IC 11, which also covers a part of the upper surface of the aluminum electrode 12.
【0023】一方、半導体装置としての液晶表示装置の
ガラス基板21上には、所定位置に配線電極22が形成
されている。この配線電極22は、表面層がアルミニウ
ム(Al)またはアルミニウムを主体とする金属または
金属多層膜からなり、本実施例では、クロム(Cr)お
よびアルミニウムからなり、クロムおよびアルミニウム
の膜厚は、それぞれ70nm、400nmに設定されて
いる。On the other hand, wiring electrodes 22 are formed at predetermined positions on a glass substrate 21 of a liquid crystal display device as a semiconductor device. The wiring electrode 22 has a surface layer made of aluminum (Al) or a metal or metal multilayer film mainly composed of aluminum. In this embodiment, the wiring electrode 22 is made of chromium (Cr) and aluminum, and the film thicknesses of chromium and aluminum are respectively The wavelengths are set to 70 nm and 400 nm.
【0024】さらに、26は異方性導電膜としての異方
性導電接着剤層で、この異方性導電接着剤層26は、た
とえばエポキシ系の熱硬化性樹脂の接着剤27に、たと
えばニッケル製の導電性微片としての導電粒子28が分
散されて包含されている。なお、異方性導電接着剤層2
6の膜厚は約30μmである。また、導電粒子28は完
全に球形でなくてもよく、たとえば毬栗状であっても良
く、直径は、約2μmから5μmに設定されている。Furthermore, 26 is an anisotropic conductive adhesive layer as an anisotropic conductive film, and this anisotropic conductive adhesive layer 26 is made of an adhesive 27 made of, for example, an epoxy thermosetting resin, and is made of, for example, nickel. Conductive particles 28, which are conductive particles made of aluminum, are dispersed and included. Note that the anisotropic conductive adhesive layer 2
The film thickness of No. 6 is approximately 30 μm. Further, the conductive particles 28 do not have to be completely spherical, and may be, for example, chestnut-shaped, and the diameter is set to about 2 μm to 5 μm.
【0025】次に、ガラス基板21上の配線電極22へ
、液晶駆動用IC11の金属バンプ電極13をフェイス
ダウンボンディング法により電気的に接続する方法につ
いて図2ないし図5を用いて説明する。Next, a method for electrically connecting the metal bump electrodes 13 of the liquid crystal driving IC 11 to the wiring electrodes 22 on the glass substrate 21 by face-down bonding will be described with reference to FIGS. 2 to 5.
【0026】まず、異方性導電接着剤層26の外形を液
晶駆動用IC11よりやや大きく金型で打ち抜く。First, the outer shape of the anisotropic conductive adhesive layer 26 is punched out using a die to be slightly larger than the liquid crystal driving IC 11.
【0027】そして、図2に示すように、ガラス基板2
1上に異方性導電接着剤層26を位置させ、図3に示す
ように異方性導電接着剤層26をガラス基板21上に貼
付する。Then, as shown in FIG. 2, a glass substrate 2
An anisotropic conductive adhesive layer 26 is placed on the glass substrate 21, and the anisotropic conductive adhesive layer 26 is attached onto the glass substrate 21 as shown in FIG.
【0028】次に、図4に示す自動ボンディング・ツー
ル31で、液晶駆動用IC11の裏面側より約8kgで
加圧(約50g/パッド)・加熱(ツール温度190℃
)しながら約30秒保持する。この時、ガラス基板21
は、約60℃に加熱した図示しないステージ上に載せて
あり、ガラス基板21の裏面側より加熱されている。Next, using the automatic bonding tool 31 shown in FIG. 4, pressurize (approximately 50 g/pad) and heat (tool temperature 190° C.) with approximately 8 kg from the back side of the liquid crystal driving IC 11.
) and hold for about 30 seconds. At this time, the glass substrate 21
is placed on a stage (not shown) heated to about 60° C., and heated from the back side of the glass substrate 21.
【0029】そうして、ボンディング・ツール31を液
晶駆動用IC11から離せば、図5に示すように、異方
性導電接着剤層26の接着剤27により、ガラス基板2
1に液晶駆動用IC11が接着されるとともに、異方性
導電接着剤層26中の導電粒子28によりガラス基板2
1の配線電極22に液晶駆動用IC11の金属バンプ電
極13が電気的に接続される。Then, when the bonding tool 31 is separated from the liquid crystal driving IC 11, as shown in FIG.
The liquid crystal driving IC 11 is bonded to the glass substrate 2 by the conductive particles 28 in the anisotropic conductive adhesive layer 26.
The metal bump electrode 13 of the liquid crystal driving IC 11 is electrically connected to the first wiring electrode 22 .
【0030】以上の工程は、すべて自動化されており、
液晶駆動用IC11はガラス基板21上に実装される。[0030] All of the above steps are automated,
The liquid crystal driving IC 11 is mounted on a glass substrate 21 .
【0031】なお、上記実施例で用いる接着剤27は、
接続時に190℃、約30秒間保持することにより硬化
が進み、液晶駆動用IC11の表面保護層であるパッシ
ベーション膜14およびガラス基板21に強固に密着す
る。それゆえ、液晶駆動用IC11全体が、ガラス基板
21上に強固に装着され、その後のボンディングによる
樹脂補強の工程も不要となる。[0031] The adhesive 27 used in the above embodiment is as follows:
At the time of connection, the film is held at 190° C. for about 30 seconds to advance curing, and it firmly adheres to the passivation film 14, which is the surface protection layer of the liquid crystal driving IC 11, and the glass substrate 21. Therefore, the entire liquid crystal driving IC 11 is firmly mounted on the glass substrate 21, and the subsequent step of resin reinforcement by bonding is also unnecessary.
【0032】また、−30℃(30分間)/85℃(3
0分間)の500サイクルの熱衝撃試験、温度65℃湿
度95%の1000時間の高温高湿保存試験、85℃で
1000時間の高温保存試験、湿度95%で−10℃か
ら65℃の5サイクルの温湿度サイクル試験、動作試験
、振動試験や衝撃試験等の機械試験など、各種信頼性試
験により本発明による液晶表示装置を評価したところ、
接続箇所に起因するオープン、ショートの発生は、皆無
であった。[0032] Also, -30°C (30 minutes)/85°C (30 minutes)
500 cycles of thermal shock test (0 minutes), 1000 hours of high temperature and high humidity storage test at 65°C and 95% humidity, 1000 hours of high temperature storage test at 85°C, 5 cycles from -10°C to 65°C at 95% humidity The liquid crystal display device according to the present invention was evaluated through various reliability tests such as a temperature/humidity cycle test, an operation test, a mechanical test such as a vibration test, and an impact test.
There were no occurrences of opens or shorts caused by connection points.
【0033】上記実施例として、液晶駆動用IC11の
金属バンプ電極13が金の場合を例にしたが、ニッケル
粒子より柔らかく、ニッケル粒子が良く食い込む金属バ
ンプ電極として、たとえば鉛−錫(PbーSn)系また
は鉛−インジウム(PbーIn)系などの半田バンプ電
極の場合にも適用できる。In the above embodiment, the metal bump electrode 13 of the liquid crystal driving IC 11 is made of gold. However, the metal bump electrode 13, which is softer than nickel particles and into which nickel particles penetrate easily, can be made of, for example, lead-tin (Pb-Sn). ) type or lead-indium (Pb-In) type solder bump electrodes.
【0034】また、アルミニウム電極12上にバリアメ
タルを形成し、メッキ法で形成された金属バンプ電極付
きの半導体素子について説明したが、バリアメタルの構
成は、たとえばプラチナ/チタン(Pt/Ti)であっ
ても良く、また、無くても構わない。さらに、メッキ法
以外、たとえばディップ法、ボールボンディング法によ
りバンプ電極が形成された場合にも適用できる。Furthermore, although a semiconductor element with a metal bump electrode formed by forming a barrier metal on the aluminum electrode 12 by a plating method has been described, the structure of the barrier metal may be platinum/titanium (Pt/Ti), for example. It's okay to have it, and it's okay to not have it. Furthermore, the present invention can also be applied to cases where bump electrodes are formed by methods other than plating methods, such as dipping methods and ball bonding methods.
【0035】また、ガラス基板21上に形成された取り
出し電極の配線電極22をクロム/アルミニウムとした
が、配線電極22が金属または金属多層膜で、その表面
層の材料がアルミニウム、アルミニウム合金以外でも、
たとえばアルミニウム、アルミニウム合金の上に薄い金
属が形成されている場合などでも適用できる。この様な
例として、ガラス基板11上にモリブデン(Mo)、ア
ルミニウム(Al)、モリブデン(Mo)が順次形成さ
れた配線電極22がある。なお、それぞれの膜厚は、た
とえば、70nm、400nm、50nmである。Further, although the wiring electrode 22 of the extraction electrode formed on the glass substrate 21 is made of chromium/aluminum, the wiring electrode 22 may be a metal or a metal multilayer film, and the material of the surface layer may be other than aluminum or aluminum alloy. ,
For example, it can be applied even when a thin metal is formed on aluminum or an aluminum alloy. An example of this is a wiring electrode 22 in which molybdenum (Mo), aluminum (Al), and molybdenum (Mo) are sequentially formed on a glass substrate 11. Note that the respective film thicknesses are, for example, 70 nm, 400 nm, and 50 nm.
【0036】また、上記装置は、高信頼性の接続部を有
するので、液晶駆動用IC11の裏面側から封止樹脂で
覆うことは不要であるが、封止樹脂で覆っても良い。Further, since the above device has a highly reliable connection part, it is not necessary to cover the back side of the liquid crystal driving IC 11 with a sealing resin, but it may be covered with a sealing resin.
【0037】さらに、駆動方式が単純マトリクス方式あ
るいはTFT(薄膜トランジスタ)方式などに限らず、
いずれの方式の液晶表示装置にも適用できる。Furthermore, the driving method is not limited to a simple matrix method or a TFT (thin film transistor) method.
It can be applied to any type of liquid crystal display device.
【0038】なお、上記各実施例では、液晶表示装置を
例にとり説明したが、液晶表示装置に限定されること無
く、ICなどの半導体装置を基板上に実装した電子装置
のすべてに適用可能である。Although the above embodiments have been explained using a liquid crystal display device as an example, the invention is not limited to liquid crystal display devices and can be applied to any electronic device in which a semiconductor device such as an IC is mounted on a substrate. be.
【0039】[0039]
【発明の効果】本発明は、半導体素子上に形成された電
極突起を、加圧面が平坦で、かつ、接続時に生ずる19
0℃以上の温度で、また、半導体素子を破壊しない55
0℃以下の温度に加熱された治具で押圧し、この半導体
素子内での前記電極突起の高さを均一化でき、特に、フ
ェイスダウンボンディング法において、異方性導電膜の
導電粒子を小さくできるので、微細ピッチで高低差のあ
る金属突起に対しても良好な接続がなされ、隣合う電極
突起間でショートが生じにくいより高信頼性、高歩留ま
りの確実な接続が可能となる。[Effects of the Invention] The present invention provides an electrode protrusion formed on a semiconductor element with a flat pressurizing surface and with a 19°
Does not destroy semiconductor elements at temperatures above 0°C55
By pressing with a jig heated to a temperature of 0°C or less, the height of the electrode protrusions within the semiconductor element can be made uniform, and in particular, in the face-down bonding method, the conductive particles of the anisotropic conductive film can be made small. As a result, a good connection can be made even to metal protrusions with fine pitches and height differences, and a reliable connection with high reliability and high yield is possible in which short circuits are less likely to occur between adjacent electrode protrusions.
【図1】(a) 本発明の一実施例の半導体素子の形
成方法を示す断面図である。
(b) 同上形成後の半導体素子を示す断面図である
。FIG. 1(a) is a cross-sectional view showing a method for forming a semiconductor element according to an embodiment of the present invention. (b) It is a sectional view showing a semiconductor element after formation same as the above.
【図2】同上液晶駆動用ICを基板への取り付けの工程
を示す断面図である。FIG. 2 is a sectional view showing the process of attaching the liquid crystal driving IC to the substrate.
【図3】同上液晶駆動用ICを基板への取り付けの図2
の次の工程を示す断面図である。[Figure 3] Diagram 2 of attaching the same liquid crystal driving IC to the board
It is a sectional view showing the next process.
【図4】同上液晶駆動用ICを基板への取り付けの図3
の次の工程を示す断面図である。[Figure 4] Diagram 3 of attaching the same liquid crystal driving IC to the board
It is a sectional view showing the next process.
【図5】同上液晶駆動用ICを基板への取り付けの図4
の次の工程を示す断面図である。[Figure 5] Diagram 4 of attaching the above liquid crystal driving IC to the board
It is a sectional view showing the next process.
【図6】従来例の液晶駆動用ICが基板へ取り付けられ
た状態を示す断面図である。FIG. 6 is a sectional view showing a state in which a conventional liquid crystal driving IC is attached to a substrate.
【図7】同上液晶駆動用ICを基板への取り付けの工程
を示す断面図である。FIG. 7 is a cross-sectional view showing the process of attaching the liquid crystal driving IC to the substrate.
【図8】同上液晶駆動用ICを基板への取り付けの図7
の次の工程を示す断面図である。[Figure 8] Figure 7 of attaching the above liquid crystal driving IC to the board
It is a sectional view showing the next process.
【図9】同上高さの異なる金属バンプ電極で小径の導電
粒子を用いて液晶駆動用ICを基板に取り付けた状態を
示す断面図である。FIG. 9 is a cross-sectional view showing a state in which a liquid crystal driving IC is attached to a substrate using small-diameter conductive particles with metal bump electrodes having different heights.
【図10】同上高さの異なる金属バンプ電極で大径の導
電粒子を用いて液晶駆動用ICを基板に取り付けた状態
を示す断面図である。FIG. 10 is a sectional view showing a state in which a liquid crystal driving IC is attached to a substrate using large-diameter conductive particles using metal bump electrodes having different heights.
11 半導体素子としての液晶駆動用IC13
電極突起としての金属バンプ電極15 加
圧面
16 加圧治具11 Liquid crystal driving IC13 as a semiconductor element
Metal bump electrode 15 as an electrode protrusion Pressure surface 16 Pressure jig
Claims (1)
、加圧面が平坦でかつ190℃以上550℃以下の温度
に加熱された治具で押圧し、この半導体素子内での前記
電極突起の高さを均一化することを特徴とする半導体素
子の製造方法。1. An electrode protrusion formed on a semiconductor element is pressed with a jig having a flat pressing surface and heated to a temperature of 190° C. or more and 550° C. or less, and the electrode protrusion is pressed within the semiconductor element. A method of manufacturing a semiconductor device characterized by making the height uniform.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3062180A JPH04296723A (en) | 1991-03-26 | 1991-03-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3062180A JPH04296723A (en) | 1991-03-26 | 1991-03-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04296723A true JPH04296723A (en) | 1992-10-21 |
Family
ID=13192676
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3062180A Pending JPH04296723A (en) | 1991-03-26 | 1991-03-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04296723A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0729937A (en) * | 1993-06-25 | 1995-01-31 | Canon Inc | Collector electrode and electrode forming method |
JPH11214420A (en) * | 1998-01-28 | 1999-08-06 | Citizen Watch Co Ltd | Semiconductor device and manufacture thereof and mounting structure |
JPH11258620A (en) * | 1998-03-11 | 1999-09-24 | Hitachi Ltd | Liquid crystal display |
JP2000214455A (en) * | 1999-01-26 | 2000-08-04 | Alps Electric Co Ltd | Reflection type liquid crystal display device and its production |
JP2001133801A (en) * | 1999-11-04 | 2001-05-18 | Seiko Epson Corp | Component mounting method and method of manufacturing electro-optical device |
JP2001230273A (en) * | 2000-02-18 | 2001-08-24 | Matsushita Electric Ind Co Ltd | Display panel and method of manufacturing the same |
JP2011061241A (en) * | 2006-04-26 | 2011-03-24 | Hitachi Chem Co Ltd | Adhesive |
JP2019024097A (en) * | 2006-01-16 | 2019-02-14 | 日立化成株式会社 | Conductive adhesive film and solar battery module |
-
1991
- 1991-03-26 JP JP3062180A patent/JPH04296723A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0729937A (en) * | 1993-06-25 | 1995-01-31 | Canon Inc | Collector electrode and electrode forming method |
JPH11214420A (en) * | 1998-01-28 | 1999-08-06 | Citizen Watch Co Ltd | Semiconductor device and manufacture thereof and mounting structure |
JPH11258620A (en) * | 1998-03-11 | 1999-09-24 | Hitachi Ltd | Liquid crystal display |
JP2000214455A (en) * | 1999-01-26 | 2000-08-04 | Alps Electric Co Ltd | Reflection type liquid crystal display device and its production |
JP2001133801A (en) * | 1999-11-04 | 2001-05-18 | Seiko Epson Corp | Component mounting method and method of manufacturing electro-optical device |
JP2001230273A (en) * | 2000-02-18 | 2001-08-24 | Matsushita Electric Ind Co Ltd | Display panel and method of manufacturing the same |
JP2019024097A (en) * | 2006-01-16 | 2019-02-14 | 日立化成株式会社 | Conductive adhesive film and solar battery module |
JP2011061241A (en) * | 2006-04-26 | 2011-03-24 | Hitachi Chem Co Ltd | Adhesive |
JP2011066448A (en) * | 2006-04-26 | 2011-03-31 | Hitachi Chem Co Ltd | Bonding tape and solar cell module using the same |
JP2012216843A (en) * | 2006-04-26 | 2012-11-08 | Hitachi Chem Co Ltd | Adhesive tape and solar cell module using the same |
US8969706B2 (en) | 2006-04-26 | 2015-03-03 | Hitachi Chemical Company, Ltd. | Adhesive tape and solar cell module using the same |
US8969707B2 (en) | 2006-04-26 | 2015-03-03 | Hitachi Chemical Company, Ltd. | Adhesive tape and solar cell module using the same |
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