JPH04291743A - Design backup apparatus for semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design support device for semiconductor integrated circuits, and more particularly to a design support device for digital/analog mixed semiconductor integrated circuits. In recent years, as semiconductor integration technology has improved, LSIs in which digital circuits and analog circuits are mixed on the same semiconductor substrate have come into use. The number of chips mounted can be reduced and the mounting density can be improved.

On the other hand, due to the diversification of user needs and the tendency to shorten product cycles, there is a high demand for layout design flexibility and shortened design and development periods (short delivery times) even in the above-mentioned integrated LSIs. Therefore, there is a demand for the development of an integrated LSI based on a gate array, which is advantageous in terms of design flexibility.

0003

2. Description of the Related Art FIG. 7 is a rough layout design flowchart of a conventional embedded LSI. After determining the cell placement layout based on the logic input and pin information in the library, the wiring layout is determined and data for mask manufacturing is generated. Here, in a mixed LSI, it is necessary to completely separate the power supply pins of the digital circuit and the analog circuit. The arrangement information of these digital power supply pins and analog power supply pins is stored in advance in a library, and this information is determined in advance for each type of package (fixed information).

That is, as shown in FIG. 8, the designer
First, external pins (digital/analog input/output pins and power supply pins) depending on the type of package used.
After inputting the assignment data for digital and analog, and determining the I/O arrangement for digital and analog, determine the internal cell arrangement for each digital and analog, and
Determine the placement of power supply cells for each analog.

If we pay attention to the external pin area of the chip laid out in this way, this area consists of an analog external pin block and a digital external pin block, and each block contains Pins of the same type for digital or analog are laid out consecutively. That is, the power supply pins of the digital circuit and analog circuit are completely separated and laid out.

[0006]

[Problem to be Solved by the Invention] However, in such conventional examples, the placement information of digital power pins and analog power pins is fixed for each package type, which limits the possibility of arranging internal cells and power cells. There was a problem to be solved in terms of further improving the flexibility of arranging cells within the chip.

Accordingly, an object of the present invention is to further improve the flexibility in arranging cells within a chip by providing flexibility in the arrangement of external pins.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention, as shown in FIG. 1, is based on logic design information of a semiconductor integrated circuit and pin information determined for each package. A design support device for a semiconductor integrated circuit that generates chip layout data is characterized by comprising a replacement means 1 for replacing the pin information with pin information of another package or pin information of an imaginary package.

[0009]

[Operation] In the present invention, pin information appropriate for the chip layout is arbitrarily given by the replacement means. Therefore, the possibility of arranging internal cells and power supply cells can be expanded, and the flexibility of arranging cells within a chip can be further improved.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. 2 to 6 are diagrams showing an embodiment of a semiconductor integrated circuit design support apparatus according to the present invention, and FIG. 2 is a layout design flow diagram thereof. In Figure 2, the layout design begins by inputting the library name, external pin assignment data, etc. (steps 10 and 11), and then inputting information necessary for subsequent processing, such as logic design information of the semiconductor integrated circuit and pins fixed to the package. Capture information (type, location, etc.).

[0011] Next, a necessary change instruction is given to the above pin information (step 12), but this change instruction is ``if the above fixed pin information (particularly the position) is not suitable for achieving the overall layout plan.'' ``change the fixed pin information to appropriate content'', and this means ``change the pin information (that is an obstacle to obtaining the desired layout)''.
This corresponds to "replacing the pin information of a fixed package) with the pin information of another package or the pin information of an arbitrarily set fictitious package." Therefore, step 12 functions as a replacement means.

After changing the pin information to the desired content, digital (Digital)
IGITAL) and analog (ANALOG) cells are placed at desired positions. That is, analog/digital I/O placement (step 13), internal cell placement (step 14), power supply cell placement (step 15), and GND and dummy cell placement (step 16).
, spacer cell arrangement (step 17), and so on are executed in sequence, data for mask design is generated, and a series of layout design processes is completed.

FIG. 3 shows an example of a chip layout obtained by the above design process. In Figure 3, white circles are terminals for connection between internal BC/GND power cells and Fixed/GND power cells (both digital and analog, between left and right), and one black circle is for fixed/GND power cells and I/O.
・Between GND power supply cells (both digital and analog)
4-way) connection terminals, two black circles are connection terminals between internal BC/GND power cells and Fixed/GND power cells (digital only, between top and bottom), areas identified by downward left hatching are Fixed/GND Power supply cell (for digital), area identified by many dots is Fixed
- GND power supply cell (for analog use), the area identified by downward hatching to the right represents the internal BC/GND power supply cell (for digital use).

[0014] In this example, separate GND power systems are used for digital and analog applications. That is, it has two types of GND terminals, digital and analog, and connects the GND terminals to I/O and internal cells for each type. In addition, in order to separate the GND power supply to the digital section and analog section, the internal cells of the digital section and analog section are completely separated for each BC column, and the digital section is provided with a digital power supply cell, and the analog section is provided with a power supply cell for digital. Analog power supply cells are arranged.

Furthermore, from the I/O placement results, 2
In order to realize different types of power supply, after arranging the I/O,
As shown in FIG. 2, spacer cells for connection are arranged between I/Os of the same type to avoid short circuits between I/Os of different types. Note that a series of power supply verifications is performed using, for example, the same type of I
/O GND Just check the connection status between the dummy cell and the spacer cell.

As described above, in this embodiment, pin information suitable for achieving a desired layout plan can be arbitrarily provided. For example, 2 shown in FIGS.
Considering one layout plan, four power supplies 21 to 24
The power supply 22 of these belongs to the analog block in the layout of FIG. 5, and belongs to the digital block in the layout of FIG. If the package-fixed pin information corresponds to only one or neither, such a layout plan cannot be achieved.

According to this embodiment, as described above, the pin information can be changed arbitrarily, so that, for example, FIG. 5 or FIG.
Pin information suitable for any layout can be used. Therefore, it is possible to have flexibility in the arrangement of external pins, further improving the flexibility in arranging cells within the chip, and also being able to define the same package in different layouts. .

[0018]

According to the present invention, it is possible to provide flexibility in the arrangement of external pins, and further improve the flexibility in arranging cells within a chip.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a layout processing flow diagram of one embodiment.

FIG. 3 is a chip layout diagram obtained by processing in one embodiment.

FIG. 4 is an image diagram of I/O connections according to an embodiment.

FIG. 5 is a layout plan diagram of one embodiment.

FIG. 6 is another layout plan diagram of one embodiment.

FIG. 7 is a rough layout processing flow diagram of a conventional example.

FIG. 8 is a layout processing flow diagram of a conventional example.

[Explanation of symbols]

1: Substitution means 12: Substitution means

Claims (1)

[Claims] 1. A design support device for a semiconductor integrated circuit that generates chip layout data based on logical design information of a semiconductor integrated circuit and pin information determined for each package, wherein 1. A design support device for a semiconductor integrated circuit, comprising a replacement means for replacing information with pin information of a fictitious package.