JPH0429104B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a DMA (Direct Memory Access) control system, and in particular provides a plurality of DMA request levels on a common bus to control high-level DMA request lines. It is designed to connect channel devices that require high-speed data transfer to the network.

(2) Prior art and problems As shown in Figure 1, when channel devices CH-1, CH-1, etc. have an access request to the main memory device MM, the channel devices can access the main memory device MM without going through the central processing unit CPU. In order to enable devices CH-0, CH-1, etc. to directly access this main memory device MM, a direct memory access control device DMA is provided.
A DMA control method is used in which a channel device selected by DMA gains control of the common bus C-BUS, thereby allowing the channel device to directly access the main memory device MM.

In this case, each channel device CH-0, CH-1
…and direct memory access controller
The DMAs are connected as shown in FIG. In other words, channel device CH-0 has an inverter.
INV-0, AND circuit A-0, JK flip-flop JK-0, and OR circuit OR-0 are provided, and the channel device CH-1 is similarly configured. Then, an access request RQ signal to the main memory device MM from the channel device to which it belongs is transmitted to each J terminal of the JK flip-flop, and each JK
The Q output of the flip-flop is input to an OR circuit, and the other side of the OR circuit receives an access request transmitted from the previous channel device. For example, an access request RQ1 for the main memory device MM generated from the channel device CH-1 is transmitted to the OR circuit OR-1 of the channel device CH-1 via the OR circuit OR-0 of the channel device CH-0. The requested access request will be transmitted. When such an access request is transmitted to the direct memory access controller DMA,
If this DMA does not output a memory access permission signal DMAA to the channel device at that time, it sends this memory access permission signal DMAA to the common signal line. As a result, control of the common bus C-BUS is given to the channel device that has not received the access request RQ from the previous stage and is generating the access request RQ from itself, and that channel device can access the main memory device MM. Can be accessed directly.

For example, in Figure 2, channel device CH-0
When the access request RQ is not output from the OR circuit OR-0 and the access request RQ1 is generated from inside the channel device CH-1 and is applied to the J terminal of the JK flip-flop JK-1, JK-1 outputs "1" from the Q terminal, and this is sent to DMA via OR circuit OR-1.
is applied to At this time, since the DMA has not granted access to anyone else, the access permission signal
Output DMAA. Since the Q terminal output "1" of JK-1 and the output "1" of the inverter INV-1 are applied to the AND circuit A-1 of the channel device CH-1, the AND circuit A-1 is applied by the output of this DMAA. outputs "1", and based on this, the channel device CH-1 acquires control of the common bus C-BUS, so that it can directly access the main memory device MM. But channel device CH-0
In this case, since the Q terminal output of JK-0 is "0", even if this DMAA is output, the AND circuit A-1 continues to output "0", and control of the common bus cannot be obtained. In this way, the control right is granted to a channel device to which no RQ is transmitted from the preceding channel device, and which generates an RQ from its own channel device.

A time chart in this state is shown in FIG.

Now, when the access request RQ shown in Figure 3 is generated from channel device CH-1, the next clock
Access request to DMA on falling CLK
DMARQ is output from JK-1 as shown in . It is transmitted to the DMA request terminal DMARQ. At this time, the DMA confirms that no other channel device has acquired bus control, and outputs an access permission signal DMAA as a response. At the same time, channel device CH-1 confirms that no data transfer is taking place on the bus, and
Data D1 is transferred to the main memory device MM as shown in, for example. When the data transfer is completed, the next access request is issued.

Therefore, as is clear from this time chart, the sum of the time T _{W from when an access request RQ is generated from inside the channel until the channel device acquires bus control and the data transfer time T D is} the data transfer cycle. It becomes _T.S. However, the above T _W is
T _W ≦2T _C , that is, approximately twice T _C is required, and as a result, the data transfer cycle T _S is 1 _μsec .
If T _D is about 1 μs to 2 μs, T _S =3 μs to 4 μs, and on average, T _S = about 3.2 μs is required.

However, in a magnetic disk device that requires high-speed data transfer, T _S is set at 1.4 μs to 2.4 μs, and for this purpose, a very high-speed Tc of about 200 ns must be used.

By the way, if you speed up this Tc and use a short cycle one, when Tc is rising,
Since DMAR is detected and it takes time to determine the response of DMAA to this, the OR circuit is used.
Due to the gate delay of DMARQ, it is not possible to increase the number of connected channel devices, and when Tc is made into a high-speed clock, there is a drawback that the number of connected channel devices is limited.

Therefore, conventionally, in systems where a large number of channel devices are connected and which requires high-speed data transfer, complicated control has been performed using a local burst method as shown in FIG.

In other words, in the local burst method, the fourth
The busy signal Busy shown in the figure is used as a control signal to continuously send data D0, D1, etc. in specific words.

In Figure 4, when an access request RQ is generated from the channel device as shown in
DMA request on common bus on falling edge of MCLK
DMARQ is output. The DMA confirms that no other device has already acquired control of the bus and outputs the permission response DMAA indicated by . A channel device requests access from the previous channel device.
Confirm that RQ is not output and acquire bus control on the falling edge of MCLK. At the same time, a busy signal indicates the data transfer status on the bus.
Confirm that Busy is not “1” and set Busy to “1”
Outputs and performs data transfer as shown in .
At this time, after the first word data transfer, Busy “1”
An example in which the second word of data is transferred is described below, but the number of data transfer words is not particularly defined. When the local burst transfer is completed in this way, the channel device confirms that the internal DMA transfer conditions have been met and sets the next DMARQ as shown in .

This local burst method requires a control signal for the busy signal, and also requires control to count the number of words of transferred data in advance and generate a DMA request when a specific number of words is reached. , the disadvantage is that the overall configuration becomes complicated.

(3) Purpose of the Invention In order to improve the above-mentioned drawbacks, the present invention provides a channel device that requires high-speed data transfer and a channel device that can transfer data at a normal speed.
DMARQ is divided into multiple parts and priority is given to the DMARQ side that requires high-speed data transfer.
It provides a DMA control method.

(4) Structure of the invention In order to accomplish this purpose, the present invention has been developed.
The DMA control method includes a storage device, a direct memory access control means for controlling access requests to the storage device, and a plurality of access request means connected to the direct memory access control means. In the direct memory access control method, the direct memory access control means responds to the access request when the access request occurs, and the direct memory access control means includes a plurality of access request means for the direct memory access control means. In addition to dividing into groups, the direct memory
The access control means is provided with a clock generation source that generates a first clock having a high frequency and a second clock having a frequency lower than the first frequency, and the access control means is provided with a clock generation source that generates a first clock having a high frequency and a second clock having a frequency lower than the first frequency. The second clock is supplied to the other group, and the processing priority for the access request of the first group is set higher than that of the other group.

(5) Examples of the invention The outline of the present invention will be briefly explained with reference to FIG.

In the present invention, the channel devices are divided into a group G0 controlled by a fast cycle clock CLK0 and a group G1 controlled by a normal cycle clock CLK1. Fast cycle clock
Channel device 2, which is controlled by CLK0, has a limited number of connections, but the normal clock CLK1
Since those that can be controlled are separated into group G1, the number of channels connected in group G0 can necessarily be small, so there is no problem. and
DMA1 is connected to the high-level DMA request line so that when direct access request DMAR0 from group G0 conflicts with direct access request DMAR1 from group G1, priority is given to DMAR0 from group G0. Configure it as follows. In this way, channel devices that need to be controlled by high-speed clock CLK0, such as magnetic disk devices, are connected to group G0, and devices for magnetic tape devices, line control devices, etc. that are controlled by normal clock CLK1 are connected to group G0. Can be connected to the G1 side.

An embodiment of the present invention will be described based on FIGS. 5 to 9.

FIG. 5 is a configuration diagram of an embodiment of the present invention, FIG. 6 is an explanatory diagram of its operation, FIG. 7 is a priority circuit section in the DMA, and FIG. 8 is a reset signal P ₁ in FIG. 7.
FIG. 9 is a diagram illustrating the generation state of the reset signal _P1 .

In the figure, 1 is a direct memory access control device DMA used in the present invention, 2 is a channel device controlled by a high-speed clock CLK0,
3 is a channel device controlled by a normal clock CLK1, 10 and 11 are AND circuits, 12 is an inverter, 13 is an OR circuit, 14 to 16 are flip-flops, 17 to 19 are counters, 20 is an inverter, and 21 is an AND circuit. be.

DMA1 consists of a group G0 consisting of a channel device 2 controlled by a high-speed clock CLKO, and a channel device 3 controlled by a normal clock CLK1.
Group G1 consisting of is connected.

Group G0 has a limited number of connections, but a plurality of channel devices are connected as shown in FIG. 2, and since each channel device has the same configuration, channel device 2 is shown as a representative. This channel device 2 is provided with an OR circuit 2-0, a JK flip-flop 2-1, an AND circuit 2-2, an inverter 2-3, and the like. An access request RQ-0 is applied. The operation of this channel device 2 is shown in Figure 2.
-0, Same as CH-1.

A plurality of channel devices are connected to group G1 in a state as shown in FIG. 2, and since each channel device has the same configuration, channel device 3 is shown as a representative. This channel device 3 also
OR circuit 3-0, JK flip-flop 3-1,
An AND circuit 3-2, an inverter 3-3, etc. are provided, and the J terminal of the JK flip-flop 3-1 receives an access request generated from the channel device 3.
RQ-1 is applied. The operation of this channel device 3 is also similar to the channel devices CH-0 and CH-1 shown in FIG.

Next, the operation of the present invention will be explained based on FIG. The high-speed clock CLK0 that controls group G0 in FIG. 5 and the normal clock CLK1 that controls group G1 are generated in the state shown in FIG.

Now, if access request RQ-0 is generated from channel device 2 at timing _T1 as shown in , DMA1 confirms that it is not outputting access permission signals DMAA0 and DMAA1 that give bus control to others. and outputs DMAA0. As a result, the channel device 2 transfers the data D0-1.
Furthermore, as shown at timing _T2 during processing of the access request from the channel device 2, an access request RQ1 is generated from the channel device 3.
Even if the access request RQ-1 is transmitted to the DMA 1, the priority circuit shown in FIG. 7, which will be described later, does not accept the access request RQ-1. And as shown in the timing
Access request RQ-0 from channel device 2 at _T3
occurs, the permission signal for this
DMAA0 is output and data transfer based on this
D0-2 can be performed. And this data transfer D0
-2 ends and there is no access request from group G0, DMA1 outputs an access permission signal DMAA1 to the channel device for which the access request has been made from the timing _T2 , thereby data transfer D1-1 will be carried out.

Next, the priority circuit section provided in the DMA 1 will be explained with reference to FIG.

This priority circuit section includes AND circuits 10 and 11, an inverter 12, an OR circuit 13, and a flip-flop 1.
In the initial state, the output "1" of the flip-flop 16 is applied to the AND circuits 10 and 11. At this time, group G0 requests access.
When RQ-0 is transmitted to DMA1, AND circuit 1
0 outputs "1", the flip-flop 14 outputs "1", and transmits the output "1" of the flip-flop 14 to an access permission determination section (not shown) which operates the counter 17 and generates the access permission signal DMAA0. do. This RQ-0
is being transmitted, the inverter 12 outputs "0" and turns off the AND circuit 11, so even if RQ-1 is transmitted from group G1, the AND circuit 11 continues to output "0". Flip-flop 15 does not output "1". Further, when the AND circuit 10 outputs "1", the OR circuit 13
outputs "1", sets the output of flip-flop 16 to "0", and turns off AND circuits 10 and 11. When RQ0 is transmitted in this way,
Even if RQ-1 is transmitted, priority will be given to RQ-0.

When the address and service-in signal SVi shown in FIG. 8 are output during data transfer, a reset signal is generated by a reset signal generation circuit composed of a counter 19, an inverter 20, and an AND circuit 21 shown in FIG. P1 is generated and applied to the flip-flop 16 reset instruction. As a result, the output of the flip-flop 16 becomes "1" again, and the next access request can be accepted.

Of course, in FIG. 7, when access request RQ-0 is not transmitted from group G0, group G
If the access request RQ-1 is transmitted from the flip-flop 15, the flip-flop 15 outputs "1" and control is performed accordingly. Note that counters 17 and 18 in FIG. 7 are RQ-0 and RQ-0, respectively.
This is for sustaining the outputs of the flip-flops 14 and 15 for a certain period of time in accordance with RQ-1.

(6) Effects of the Invention According to the present invention, devices that require high-speed clock control, such as magnetic disk devices, and devices that can be controlled by normal clock control, such as magnetic tape devices and line control devices, can be separated. It is structured so that access requests are generated separately for each system, and the DMA is structured so that requests controlled by a high-speed clock are processed as high-level access requests. In addition to shortening the time from request to DMA grant, that is, arbitration time, it is possible to improve data transfer functionality because the high-speed data transfer side is controlled with high priority. Moreover, it can also be used for normal clock control.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the DMA control method, Fig. 2 is a block diagram of the conventional DMA control method, Fig. 3 is an explanatory diagram of its operation, Fig. 4 is an explanatory diagram of local burst operation, and Fig. 5 is a diagram of the main FIG. 6 is an explanatory diagram of its operation; FIG. 7 is a diagram illustrating the priority circuit section in the DMA; FIG. 8 is an explanatory diagram of the generation state of the reset signal P1 in FIG. 7; This is a generating circuit for the reset signal P1. In the figure, 1 is a direct memory access control device, 2 is a channel device controlled by a high-speed clock, 3 is a channel device controlled by a normal clock, 2-0 and 3-0 are OR circuits, and 2- 1,3-
1 is a JK flip-flop, 2-2, 3-2 are AND circuits, 2-3, 3-3 are inverters, 10,
11 is an AND circuit, 12 is an inverter, 13 is an OR circuit, 14-16 are flip-flops, 17-
19 is a counter, 20 is an inverter, and 21 is an AND circuit.

Claims (1)

[Scope of Claims] 1. A storage device comprising a storage device, a direct memory access control means for controlling access requests to the storage device, and a plurality of access request means connected to the direct memory access control means. In the direct memory access control method, the direct memory access control means responds to the access request when the request means generates the access request, the access request means for the direct memory access control means. is divided into a plurality of groups, and the direct memory access control means is provided with a clock generation source that generates a first clock having a high frequency and a second clock having a lower frequency than the first frequency, A first clock is supplied to one of the groups and a second clock is supplied to the other group, and the processing priority for the access request of the first group is higher than that of the other group. A direct memory access control method that is characterized by a direct memory access control method.