JPH0429095B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention is in the field of synchronous central processing units for large, high performance, general purpose digital data processing systems. In particular, the present invention relates to a distributor for a central execution pipeline unit of a central processing unit, where machine words are transmitted between central processing units and where the distributor serves as a communication center where the machine words can be marshalled when needed.

Description of the Prior Art Many changes and improvements have been made to the central processing units (CPUs) that make up an element of a data processing system in order to improve their performance.

One such modification is the use of a cache device located in the CPU to minimize the time required to fetch operands and instructions. Furthermore, to improve CPU performance, the CPUs are synchronized. That is, a single clock generates multiple clock pulses that control each step or stage of CPU operation.

Synchronization allows for parallel execution of instructions, repeated execution of instructions, or Enables pipeline execution.

It has several execution units, each capable of executing a subset of the CPU's instruction repertoire, and the execution units are substantially independent of each other.
In a CPU, the CPU's central execution pipeline unit executes instructions that involve fetching the operands or target words, or operands, of each instruction in successive steps, each requiring completion of one clock period during which each instruction progresses. It is desirable to initialize it. Thus, at the end of the last step of the central execution pipeline, either the instruction and its operands or target words are available and ready for execution, or the instruction is executed by the appropriate execution unit.

by one of the plurality of execution units as each instruction finishes passing through the central execution pipeline unit.
Whatever the source, one
These target words need to be transferred to the execution device as quickly as possible.

Since the instruction requires data in the target word to be aligned, alignment of the target word should be done before it is received by the execution unit to which it is addressed.

Additionally, such CPUs require means for transmitting information between units of the CPU in addition to the execution unit, and within the central pipeline execution unit itself, in order to maximize the performance of the CPU as quickly as possible.

SUMMARY OF THE INVENTION This invention provides a synchronous system having an instruction fetching device, a collector device, a cache device, and multiple execution devices.
Provides a distributor for the CPU's central execution pipeline unit.

One of the execution units, the central execution unit, performs so-called elementary operations, many of which can be executed in a single clock period, and whose results are compared to other to enable the device to perform its prescribed functions;
It is often required by other devices.

The distributor includes a pair of A/Q registers in which copies of the contents of the A/Q registers of the central execution pipeline unit and the binary arithmetic execution unit are stored;
One execution unit performs operations that modify its contents in the preferred embodiment.

Additionally, the distributor includes an effective address register in which the effective address of the target or instruction word is stored.

The signals stored in the A/Q registers are applied to a binary selection A/Q switch which provides as its output the contents of one of the two A/Q registers. Two A/
The selection of the Q register is determined by which position of the A/Q switch is enabled by the control signal.

Furthermore, the distributor includes a data register for storing two machine words in two machine word positions, one in an odd numbered position and one in an even numbered position.

In the preferred embodiment, each machine word is 36 bits and can be divided into either 6-bit characters or 9-bit characters.

The alignment function of the distributor is performed by a character alignment switch and a word alignment switch to which the machine words stored in the data registers are applied. Depending on which position of the switch is enabled, the character alignment switch will align the output word with four 9-bit characters or the data register with one of the six 6-bit characters of even-numbered words.

A word alignment switch has as its output a machine word that is either an odd word or an even word stored in a register, depending on which position of the switch is enabled, i.e.
The 18-bit effective address outputs a machine word that is either the top half or the bottom half of the output word, depending on which position of the switch is enabled.

Character and word alignment switch outputs,
Sources such as the output of the collector device and the output of the A/Q switch are fed to the data in switch. The data in switch selects a pair of machine words derived from one of the sources, depending on which position is enabled. If the selected source provides a single word, the second or odd word of the output of the data-in switch is all logic "0"s.

The output of the data in switch is transmitted to the central execution unit and instruction fetch unit. Additionally, the output of the data in switch is also the input to the data register switch. 2nd data register switch
The input to is a pair of machine words from the cache device.

The data register switches are a pair of four-way switches, each switch pair being one machine word wide and either one or both word locations of the data register, depending on which location of the switch is enabled. One of the four machine words added can be applied to the switch to store it in the word position. The machine words stored in the data registers are transmitted to the CPU's execution unit and the paging logic of the central execution pipeline unit, as well as to the character and word alignment switches.

OBJECT OF THE INVENTION Therefore, an object of the invention is to provide a method for transmitting target words of instructions to the execution unit of a CPU.
The object of the present invention is to provide a distribution device for a central execution pipeline device of a CPU.

Another object of the invention is to provide a distributor for a central execution pipeline unit of a CPU that is a communication center for machine language transmitted between units of the CPU.

Yet another object of the invention is to, if required by the instructions to be executed by the execution device,
The object of the present invention is to provide a distributor for a central execution pipeline unit of a CPU that sorts machine words before transmitting them to an execution unit.

DESCRIPTION OF THE INVENTION (DESCRIPTION OF EMBODIMENTS) Referring to the drawings, the main registers of the distributor 10 are data register (RD) 1 which functions as a data input register for the execution unit of the central processing unit.
It is 2. The central processing unit includes as one of its units a central execution pipeline unit (CEPU) of which distributor 10 is a component. In a preferred embodiment,
The execution units of the CPU are the Central Execution Unit (CEU), the Decimal Character Unit (DECCU), and the Virtual Memory, Security, and Maltake Unit (VMSM).

The primary input to data register 12 comes from the CPU's cache unit and consists of two machine words that are applied to, or are input to, data register switch 14.

In the preferred embodiment, the machine word, or word, is 36 ordered bits and can be divided into four 9-bit characters or six 6-bit characters.

A half word is 18 ordered bits.

In the preferred embodiment, data register switch 14 is one of four selection switches in two rows, each set of switches being one word wide. Since data register 12 is two words wide, it can store binary signals representing two machine words. Data register 12 has two machine word locations identified as even word location 16 and odd word location 18.

Other sources of input to data register 12 are
Depending on the CPU collector device and which position of the switch is enabled, BINAUA/
The output of the A/Q switch 20, a two-word wide switch that selects one of the two, transmits a signal representing the two words stored in the Q register 22 or the two words stored in the central A/Q register 24. It is.

2 of the signals to be stored in the data register 12
Two other sources are the outputs of character alignment switch 26 and word direct alignment switch 28.

The signals stored in data register 12 are transmitted to or applied to word direct alignment switch 28 by data bus 30.

In the preferred embodiment, only signals for even numbered words stored in data register 12 are applied to character alignment switch 26. Character alignment switch 26 is, in the preferred embodiment, a one word wide switch with a one of ten selection, and word direct alignment switch 28 is a one word wide switch with a one of four selection.

The second set of input signals applied to word direct alignment switch 28 is the effective address register.
This is a signal stored in the REA32.

This effective address is expanded by the address formation logic of the CPU's CEPU, and the effective address is
It is the effective address of the instruction's target word that is formed and available at the end of the CEPU A cycle.

In the preferred embodiment, this real address is 18
Bit binary numbers, or half words, are used by word direct alignment switch 28 to form the operands of direct operations or instructions.

Output from character alignment switch 26, each of which is one machine word, word direct alignment switch 28 and A/Q switch 20, which is two words.
and the output from the collector is data in switch 3
4, the source of the input signal to a two word wide switch that selects one of five.

The output of data in switch 34, which is two words, is applied to data register switch 12 as its second set of input signals. Next, the two signal sources to data register switch 14 are the cache device and the output of switch 34. Additionally, the output of data in switch 34 is applied to the CPU's instruction fetch unit and central execution unit or transmitted via data bus 36.

The signals stored in the data register 12, ie, the two machine words, are transmitted via the data bus 38 to the four execution units of the central processing unit: the central execution unit (CEU), the binary arithmetic unit (BINAU), the 10 forward character unit (DECCU) and virtual memory,
Security and multi-systems (VMSM) or transmitted.

Additionally, register 12 is a source of data transmitted via bus 38 to other components of the CEPU, such as its paging logic.

As previously discussed, the primary source of input signals, or machine language, to data register 12 is the cache device. Whenever the target word of an instruction is in the cache, ie, whenever the cache is present, the addressed words are transmitted from the cache two words at a time. If a single word is all that is required by the designated execution device that will execute the instruction, then the appropriate control signal is only one of the two target words received from the cache device. The correct switch position of switch 14 is enabled to apply a word of the signal to data register 12 for storage in either its even position 16 or odd position 18.

Typically, if a single word is all that is required for a single precision operation, for example, that word will be stored in both even and odd positions.

If a cache miss occurs, that is, the target word is not in the cache device, the addressed word is obtained from the random access memory of the computer system of which the CPU is a subsystem and is read by the collector device.
Transmitted to the CPU's cache device.

Under these circumstances, to minimize interruption to central processing unit operation, the addressed block of eight such words containing the addressed word to be written to the cache device. Words are transmitted by the collector to the distributor 10 for storage in the data register 12 by enabling one switch position of the data-in switch 34 which causes the signal from the collector device to appear as the output of the data-in switch 34. Ru.

Furthermore, the output of switch 34 is connected to data bus 36.
It can be used for instruction fetching units and central execution units.

Thus, the instruction fetch unit and central execution unit can receive machine language from data bus 36. If the target word is an instruction needed by the instruction fetcher to prevent interruptions in the pipeline, i.e., CEPU operation, this minimizes some delays caused by cache misses. It is important in making Similarly, delays caused by cache misses are minimized if the target word is an operand needed by the central execution unit. Then it can finish working.

Another function of the distributor 10 is to carry out the operations of the A/Q registers in the performance of the execution unit, ie, to maintain a current copy of the execution unit's A/Q registers using the registers.

BINAUA/Q register 22 stores an up-to-date copy of the contents of the A/Q register of the BINAU execution unit whose information is transferred to register 22 from the collector device.

The central A/Q register 24 is the A/Q register of the central execution unit.
Alternatively, it is updated directly from CEU one cycle after the contents of either Q register are changed.

Effective address register REA 32 stores signals representing the effective address as developed by the address formation logic of the CEPU.

In all direct operations, the effective address forms part of the operands of an instruction whose effective address occupies either the upper half, i.e., the high-order bit positions of a machine word, or the lower half, i.e., the low-order bit positions of such a word. do.

To form the required direct operand,
One or the other of the two positions of word direct alignment switch 28 is enabled by an appropriate control signal. So the output word is REA32 in either its upper or lower half.
has an effective address from .

Depending on which position of the switch is enabled by the appropriate control signal, word direct alignment switch 28 provides as its output an even or odd word or direct operand that is stored in register RD12.

When selected by enabling the appropriate positions of switches 34 and 14, switch 2
The output from 8 is stored in either an even or odd position of data register RD12.

Depending on which position of the switch is enabled, the character alignment switch 26 can be
select one of the six 9-bit characters or one of the six 6-bit characters of the machine code and properly arrange the selected character in the output word of switch 26.

All high order bit positions of the output of character alignment switch 26 are forced to logic "0".

The output of character alignment switch 26 is applied to data register switch 14 through data in switch 34 for storage in even word position 16 and odd word position 18.

The target word of an instruction from a cache device for an execution unit other than the central execution unit passes through data register switch 14.

During passage through switch 14, these words are aligned in response to an alignment control signal applied to switch 14. From switch 14, the target word is stored in data register 12. Next, the target word stored in the data register 12 is
During the CEPU E/T cycle, it is transmitted via bus 38 to the designated execution unit. In addition, the target word from the collector in the cache miss is transmitted via bus 36 to the instruction fetch unit and central execution unit.

Under these environments, the reason for direct transmission is that the instruction fetch unit and central execution unit are
It is the most critical device in achieving the maximum function of.

In addition, distributor 10 can transmit operands directly to the central execution unit, or in the case of two-word operations, transmit even or odd words to the central execution unit, so that during successive clock periods it can transmit operands directly to the central execution unit. I can transmit my other one.

The distributor also aligns the characters of the target word for those instructions that modify or act on one character.

In these circumstances, it is necessary to write the correct target word to data register 12 in a word in which the character to be operated on is placed in an even word position of data register 12.

Next, this word is the character alignment switch 2.
Depending on which position of the switch is enabled, switch 26 selects the desired character, either one of six 6-bit characters or one of four 9-bit characters. . The character is correctly ordered in the output word of switch 26.

From the foregoing, it is clear that the distributor of the present invention provides a central communication link that can rapidly communicate information between units of a CPU having multiple execution units, maximizing the functionality of the CPU.

It will be obvious that certain modifications may be made to the described invention without departing from its scope.

[Brief explanation of drawings]

The drawing is a schematic circuit diagram of a distributor according to the invention. 10...Distributor, 12...Data register, 2
0...A/Q switch, 22...BINAU-AQ
Register, 24... Central A/Q register, 26...
...Character alignment switch, 28...Word direct alignment switch, 30...Data bus, 32...Effective address register, 34...Data in switch.

Claims (1)

[Claims] 1. A plurality of different types of instruction execution units (CEUs,
BINAU, DECCU, VMSM), all of whose instruction execution units are controlled to execute instructions concurrently and asynchronously with each other. a switch unit 14, 34 for selecting an operand from one of the operand sources; a register 12 for holding an operand for transfer to said instruction execution unit; said switch unit for transferring an operand to said register. a first circuit coupled to; an alignment circuit 26, 28 for reordering portions of an operand; a second circuit coupling said register to said alignment circuit for transferring at least part of the contents of said register; 3. A distributor comprising: a circuit 30; and a third circuit coupling said alignment circuit to said switch unit for transferring operand portions. 2. A distributor as claimed in claim 1, characterized in that the alignment circuit comprises an element 26 for selecting one of a plurality of characters of the operand.