JPH04289696A - Fluorescent lamp illuminating device with adjustable light intensity - Google Patents

Abstract

PURPOSE:To adjust light intensity smoothly by providing a light intensity adjustment control signal generation circuit, a control voltage generator, and a voltage control oscillator, and using the output of the voltage control oscillator as a clock of the light intensity adjustment control signal generation circuit. CONSTITUTION:A voltage control oscillator VCO90, which is provided for using its frequency-modulated pulse as a clock of a light intensity adjustment control signal generation circuit 30, outputs a output pulse sequence Vf, having a frequency in proportion to an input voltage, to a down counter CO1 for PWM cycle generation of the circuit 30. That is, the output pulse sequence Vf is used as the clock of the counter CO1. On the other hand a zero cross signal Zi is used as a clock of a down counter CO2. A PWM cycle signal Vca, which is output to an inverter 30e, becomes a borrow signal of the counter CO2. Thereby frequency modulation can be set so as a higher frequency at low brightness time and as a lower frequency at high brightness time, and it is possible to M digital style change of brightness unapparent so as light intensity to be adjusted smoothly.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention aims to improve the ratio of on/off periods when illuminating fluorescent tubes such as hot cathode fluorescent tubes and cold cathode fluorescent tubes (both can be used; hereinafter referred to as "lamps"). The present invention relates to a dimmable fluorescent tube lighting device that changes and dims the light, and particularly relates to a dimmable fluorescent tube lighting device that has improved dimming characteristics.

0002

[Background Art] Conventionally, in this type of fluorescent tube lighting device with a dimmable function, the average brightness of the lamp is adjusted by turning the lamp on and off at regular intervals, and adjusting the average brightness by the ratio of the on period to the off period. A duty dimming method is generally used, and for example, there is one shown in FIG. 11 (block diagram showing the configuration of a conventional fluorescent tube lighting device with dimming).

In FIG. 11, 2 is a self-excited inverter (hereinafter referred to as "inverter"). Its structure is, for example, the electrode (called a filament in the case of a hot cathode tube) of the lamp 1 shown in a cold cathode fluorescent tube (of course, a hot cathode tube may also be used).
One end of the lamp 1 is connected to one of the secondary windings of the transformer T1 via the capacitor C1, and the other end of the electrode of the lamp 1 is connected to the other of the secondary windings of the transformer.

Reference numeral 3 denotes a dimming control signal generation circuit, which outputs a pulse signal (dimming control signal, duty control signal) whose duty ratio is controlled at a constant period to drive the switch circuit 4. On/off control.

By turning on and off the switch circuit 4, the DC power source E1 is supplied to the inverter 2, and the transistor circuit 2a of the inverter 2 is turned on and off (oscillation and
stop). By this, the lamp applied voltage is turned on and off, and the change in the lighting/extinguishing ratio is controlled (duty control), thereby controlling the illumination of the lamp 1.

By controlling the switch circuit to turn on and off the inverter supply voltage in this way, the voltage applied to the lamp is turned on and off, so that the lamp turns on and off regardless of the status of the lamp and the inverter. It will be held on.

[0007] In order to widen the dimming range, attempts are made to eliminate jitter in the pulse signal, stabilize the inverter output against load fluctuations due to lamp on/off, and improve lamp characteristics. The limit of the dimming range in such a circuit configuration is several hundredths.

On the other hand, when used as various internal lighting devices in fields such as ships and aviation, a dimming of one thousandth is required, and such fluorescent tube lighting devices with dimming do not meet this requirement. is insufficient.

Therefore, in order to solve such problems, the applicant of the present application has proposed that the dimming characteristics can be improved by more than one order of magnitude to one thousandth of a thousandth, or that the lamp The dimming range can be expanded and stabilized, or by improving the resolution of the duty control signal, smooth dimming can be achieved even at low brightness, or dimming can be controlled digitally. Patent application No. 2002 is filed for a dimmable fluorescent tube lighting device that can stabilize the dimming characteristics by suppressing the flickering of the lamp by suppressing the influence of noise included in the dimming setting signal input to the dimming control generation circuit. -142771
(hereinafter referred to as "prior art").

FIG. 12 is a block circuit diagram of a prior art dimmable fluorescent tube lighting device. FIG. 13 is a diagram for explaining FIG. 12.

In FIG. 12, regarding dimming of the lamp 10 (in this case, a hot cathode is shown), when adjusting the average brightness by the ratio of the lighting period to the lighting period, an inverter driving the lamp 10 is used. When the output voltage of the controller 20 is at zero potential, it is configured to turn on or off, or both.

That is, the inverter output is led from the inverter 20 to which DC power E1 is constantly supplied through the capacitor C1 to both poles on one side of the filament (denoted like this because it is a hot cathode) of the lamp 10. .

Furthermore, a pulse train synchronized with the zero crossing of the inverter output voltage (lamp voltage) is applied to the secondary side auxiliary winding terminal of the transformer T1. A ramp voltage synchronization pulse generation circuit (hereinafter abbreviated as "zero cross detection circuit") 5 is connected to generate a zero cross synchronization pulse that rises or falls at . This zero cross detection circuit 5
The zero-crossing signal Zi is led to a dimming control signal generation circuit 30, which will be described later, and a multiplier circuit 7 which generates and outputs a multiplier pulse signal (pulse of multiplier frequency in synchronization with the pulse train) Yi.

Further, the dimming switch circuit 6 is opened and closed by a duty control signal from the dimming control signal generating circuit 30. For example, it is constituted by a switch mechanism consisting of switch elements Q1 and Q2 consisting of a pair of FETs, etc., and this switch mechanism is connected to both poles of one side and the other of the filament of the lamp 10, thereby controlling the light of the lamp.

Regarding the switch circuit 6 at this time, the switch mechanism is connected to the lamp 10 and is opened and closed by the signal Pia from the dimming control signal generation circuit 30, as shown in FIG. Alternatively, as shown in FIG. 11, the DC power source E1
and the inverter 2, and may be configured to open and close according to the signal from the dimming control signal generation circuit 3; this is a design matter and has special differences. It's not a thing.

Returning to FIG. 12. The dimming control signal generation circuit 30 generates a zero cross signal Zi, a multiplication pulse signal Yi,
and a dimming setting signal Ti, and based on these signals, the lamp 10 is dimmed to either "turn on or turn off" synchronously when the inverter output is at zero potential.
A signal (a pulse width modulation signal having a function as a dimming control signal, hereinafter referred to as "PWM signal") Pia for opening and closing the switch mechanism is output to the switch circuit 6, and the dimming of the lamp 10 is controlled by the duty of turning on and off. It is done by ratio. For this purpose, a lighting/extinguishing period calculation circuit (A/D) 30a that calculates the necessary lamp lighting period and lamp extinguishing period from the dimming setting signal Ti and outputs it as a digital value, a PWM cycle setting switch 30b, and a zero cross signal Zi/ Multiplied pulse signal Yi/signal θ from the lighting/extinguishing period calculation circuit 30a
i. Pulse width modulation means 30c outputs the PWM signal Pia to the switch circuit 60 based on the signal from the PWM cycle setting switch 30b.

By the way, the on/off period calculation circuit 30a
Generally, a configuration is used in which the dimming setting signal Ti is A/D converted and used as a digital value indicating the lamp lighting period. By the way, in the case of FIG. 12, the number of bits of the A/D conversion function matches the number of bits of the pair of down counters, and the PWM cycle setting switch 3
If all 0b are "high" and there is no need to convert the duty ratio, and the dimming setting signal Ti contains noise, the lamp lighting period may increase or decrease, causing flickering in the lamp. be.

Therefore, in order to prevent this, the on/off period calculation circuit 30a converts the dimming setting signal Ti into A/D with the A/D converter α1, and then converts the corresponding conversion data into a digital signal, as shown in FIG. -data (N-bit binary conversion data)
Compare Y with the N-bit binary latch data X after being latched by the data latch α4 of the previous output data (N-bit binary output data) θi to the pulse width modulation means 30c. Therefore, when the difference exceeds a certain value, it is necessary to update the output data θi output to the pulse width modulation means 30c. Here, since the subtracted output data "X-Y" of the subtractor α2 is normally unsigned binary numbers,
) bit (If the down counter CO1 for generating the PWM signal at the next stage is M bits (N>M), the data actually used is the M bits from the top of the output digital value θi. ).

As a result, the data flow is such that after the dimming setting signal Ti is A/D converted by the A/D converter α1, it is guided to the switching element (selector) α5 and the subtractor α2, The signal led to α2 is sent to subtracter α2 / decoder α
3, the output data θi is guided to the selector α5 as a predetermined switch switching signal, and is outputted.
The selector α5 determines whether to output X or Y. On the other hand, the output data θi is also led to a data latch α4 and latched, and then output to a selector α5 and a subtracter α2. In addition, at this time, A
/D conversion start and data latch timing is as follows:
In order to avoid any hindrance to this series of operations, the down counter CO2 for PWM cycle generation is decoded at an appropriate point.
It is assumed that this is occurring.

Returning to FIG. 12 again. Pulse width modulation means 30
c, for example, counts the number according to the digital value, and during this period, the PWM output is performed in order to obtain a signal content that is "H" during the lighting period and "L" during the lighting period.
It consists of a counter C01 for signal generation and a down counter CO2 for PWM cycle generation. At this time, the zero cross signal Zi is inputted to the clock terminal as the clock of the down counter CO2, and the multiplied pulse signal Yi is inputted to the clock terminal as the clock of the down counter CO1. Furthermore, the output data θi from the on/off period calculation circuit 30a is led to a preset terminal of one down counter CO1. Also, the other down counter CO
2 preset terminal has PWM cycle setting switch 30
A signal from b is guided. And down counter CO
The BORROW output of 2 is led to the LOAD (LD) terminal for both preset data. The boro output of the down counter CO1 is fed back to the enable (EN) terminal of the down counter CO1, and at the same time is output as a PWM signal Pia to the dimming switch circuit 6 via the inverter 30d. . It can be configured as follows. Incidentally, switching between lighting and turning off occurs when the output of the inverter 30d is at zero potential.

The dimming control signal generation circuit 30 configured as described above receives a zero cross signal Zi and a multiplied pulse signal Y.
When i is input, the counter operation is as follows.

(a). The PWM period is the down counter C
Produced by O2. This down counter CO2 is
A countdown is executed according to the value set by the PWM cycle setting switch 30b input to the preset data input terminal, and the preset data is loaded using the boro output signal that is output at the end of the count, and then the countdown is performed again. Run countdown. This cycle repeats.

(b). The borrow output of the down counter CO2 is also led to the load terminal of the down counter CO1. Therefore, the down counter CO1 takes in the preset data from the on/off period calculation circuit 30a from the preset terminal at this cycle.

(c). The lighting/lighting out period calculation circuit 30a is
The necessary lamp lighting period and lighting period are calculated from the input dimming setting signal Ti, and a digital value proportional to the lighting period is outputted to the down counter CO1 as output data θi. Therefore, the down counter CO1 is the down counter CO1.
The borrow output of 2 is set as a load signal, and a countdown is executed until the borrow output of itself is output, and the preset data is loaded.

(d). In addition, the down counter CO1 is
After BORROW is output (BORROW=l), change this signal state to E.
Since it is configured to feed back to the N terminal and use it, it disables itself (EL=L) and holds the borrow output in the "L" state. In other words,
The number is counted according to the digital value, and the output during this period has a signal content such that it is "H" during the lighting period and "L" during the lighting period.

(e). Therefore, the PWM signal Pia during countdown is inverted to the "L" state by the inverter 30d and output to the switch circuit 6, and the lamp 10 is turned on.

(F). When the next borrow output comes out, PWM
Since the signal Pia is in the "H" state, the lamp 10 is turned off. By designing the “H←→L” (switching on/off) of the PWM signal Pia to be synchronized with the rising (or falling) of the clock, it can be switched off when the output of the inverter 30d is at zero voltage. It works to replace it. Therefore, predetermined light control can be performed.

In this way, the PWM signal Pia is inverted.
By creating a clock based on a pulse synchronized with the zero crossing of the output waveform of the output waveform of the lamp 20 and a pulse multiplied by the pulse, if the dimming setting input is constant, there is essentially no jitter, and the discharge state of the lamp 10 is controlled. Because it is stable, the dimming range is several times wider than conventional methods, and in experiments, discharge instability (lamp flickering) that previously occurred due to temperature fluctuations has been eliminated.
The phenomenon can be eliminated.

[0029]

[Problems to be Solved by the Invention] On the other hand, this prior art has the following problems.

(A). In order to make digital changes in lamp brightness less noticeable, a counter C0 for PWM signal generation is used.
A double pulse signal Yi is used at one clock. However, the period of this signal is almost constant, and PWM
The resolution of the signal is the same at low brightness and high brightness. Incidentally, in order to make digital changes in brightness less noticeable, it is sufficient to improve the resolution of the PWM signal, but in reality, this is due to the limitation of resolution of the A/D converter α1 in the previous stage shown in FIG. Achieving high resolution is difficult.

[0031] This will be described in more detail.

Normally, the frequency of the zero cross signal Zi is several 10
It is about 0KHz. Further, in order to make the flickering of the lamp 10 inconspicuous, a PWM cycle of about several hundred Hz is required. For example, set the Xerox signal frequency to 100KH
When the PWM period is 100 Hz, the count number of the counter C02 is 1000, which requires 10 bits.

Here, the relationship between the clock frequency (Yi) of the counter input through the multiplier circuit 7 and the required number of bits of the counter is 11 bits at 200 KHz and 40 bits at 200 KHz.
12 bits at 0KHz, 13 bits at 800KHz, etc. On the other hand, as the number of bits required for the counter increases, the resolution of the A/D converter α1 also increases from 11 bits to 1
It is necessary to increase the resolution to 2 bits, 13 bits, etc., but the resolution of A/D converter α1 is 12 bits due to the influence of external noise.
If the number of bits is approximately 13 bits, the effective number of bits is lower, so it is necessary to use relatively high bits, but at present the limit is approximately 16 bits.

On the other hand, the influence of external noise affects the output data θ
This appears as instability in the lower bits of i, which causes PWM
Since this becomes a factor that makes the signal Pia unstable and causes the lamp 10 to flicker, the effect of improving the resolution of dimming cannot be expected by using these 16 bits. In other words, the higher the resolution of dimming (the resolution of the A/D converter α1) and the smaller the digital brightness change, the more susceptible it becomes to noise and the worse the stability becomes. In short, the clock frequency (Yi) of the multiplier circuit 7
The relationship between and the required number of bits of the counter is 800KHz
The resolution of the A/D converter α1 is also 13 bits.
It would be fine if it could be reduced to a bit level, but as described above, it is not possible to reduce digital brightness changes due to the influence of noise.

(i). The range of change in the PWM signal is always constant with respect to changes in the brightness setting signal, and the degree of freedom in designing the dimming characteristics is low.

The present invention has been made in view of the above-mentioned problems of the conventional technology, and its purpose is to achieve good dimming even when digitally controlling dimming. The purpose of the present invention is to provide a fluorescent tube lighting device with dimming that can perform the following steps.

More specifically, the present invention provides a dimmable fluorescent tube lighting device that makes digital changes in brightness inconspicuous and achieves smooth dimming when digitally controlling dimming. The purpose is to

Another object of the present invention is to provide a fluorescent tube illumination device with dimming that allows arbitrary dimming characteristics to be designed when performing digital dimming control.

[0039] Furthermore, in the case of performing digital dimming control, there is provided a fluorescent tube lighting device with a dimming function, which allows setting of a brightness setting signal in particular to match the response characteristics of the human eye. The purpose is to

[0040] Furthermore, when performing digital dimming control,
It is an object of the present invention to provide a fluorescent tube lighting device with dimming that is configured to be able to switch the dimming range, dimming resolution, etc. according to the surrounding environment (according to the ambient light).

[0041]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method in which DC power is supplied, the output of the secondary side of the transformer is supplied to the fluorescent tube, and an auxiliary winding provided on the secondary side of the transformer is provided. A self-excited inverter having a line terminal connected to a lamp voltage synchronization pulse generation circuit that detects the zero cross of the inverter output and generates a pulse train synchronized therewith, and a dimming setting signal and the lamp voltage synchronization pulse generation circuit. outputs a signal that operates a switch circuit to control the dimming of the fluorescent tube by turning it on or off or both in synchronization when the inverter output is at zero potential. In a fluorescent tube lighting device with dimming, which is equipped with a dimming control generation circuit for controlling the light of the tube, (a) using a PWM periodic signal of the dimming control signal generation circuit, a control voltage synchronized with the PWM periodic signal; A control voltage generator that generates a control voltage, and a control voltage generator that inputs a control voltage from the control voltage generator to improve resolution at low brightness and make digital brightness changes less noticeable, and has a frequency proportional to the input voltage. A voltage controlled oscillator that outputs an output pulse train to the dimming control signal generation circuit is provided, and the output of the voltage controlled oscillator is used as a clock in the dimming control signal generation circuit. be. Alternatively, (b) a frequency modulation circuit is provided between the lamp voltage synchronization pulse generation circuit and the dimming control signal generation circuit, and the frequency modulation circuit modulates the PWM periodic signal of the dimming control signal generation circuit and the lamp. The present invention is characterized in that the signal from the voltage synchronization pulse generation circuit is frequency-modulated, and the frequency-modulated signal is used as a clock for the dimming control signal generation circuit. (c) The dimming control signal generation circuit includes a lighting/extinguishing period calculation circuit that digitally converts the input dimming setting signal, and a digital signal from the lighting/extinguishing period calculating circuit which is converted into a two-mode signal and then converted into a two-mode signal. - Select one of the modes using the mode switching signal.
and a data switching circuit for outputting a code signal to the means for generating the PWM periodic signal.

[0042]

[Operation] By using frequency-modulated pulses as the clock for the dimming control signal generation circuit, resolution at low brightness is improved and digital brightness changes are made less noticeable. In other words, frequency modulation is set to a higher frequency when the brightness is low and to a lower frequency when the brightness is high, and is repeatedly performed at the same cycle as the PWM cycle. Furthermore, a frequency modulation circuit is disposed after the zero-cross detection circuit, and a frequency-modulated pulse is used as the clock of the dimming control signal generation circuit, so that arbitrary dimming characteristics can be realized.

[0043]

[Example] Examples will be explained with reference to the drawings.
In the following drawings, parts that overlap with those in FIGS. 11 to 13 are given the same numbers, and the explanation thereof will be omitted. FIG. 1 is a diagram showing a specific embodiment of a fluorescent tube lighting device with dimming according to the present invention. FIG. 2 is a time chart showing an outline of each voltage waveform for explaining FIG. 3 to 5 are diagrams for explaining the present invention. FIG. 6 is a diagram for explaining another embodiment of the present invention. 7 and 8 are diagrams for explaining FIG. 6. FIG.

In FIG. 1, 80 is a control voltage generator, which includes, for example, a sawtooth oscillator 81 that generates a sawtooth wave Vsa synchronized with the PWM periodic signal VCb inputted via the inverter 30e, and a subsequent voltage controlled oscillator. (hereinafter abbreviated as "VCO") 90 can be constructed from an arithmetic circuit 82 that performs correction, span adjustment, etc. to match the characteristics of VCO 90.

Here, in order to improve the resolution at low brightness and make digital brightness changes less noticeable, the VCO 90 provided for using frequency-modulated pulses as the clock for the dimming control signal generation circuit 30 is used. If so, the output pulse train Vf has a frequency proportional to the input voltage.
is output to the down counter CO1 for PWM cycle generation of the dimming control signal generation circuit 30. In other words, the output pulse train V
f is used as a clock for the down counter CO1. On the other hand, the clock of the down counter CO2 is the zero cross signal Zi (in this case, the zero cross signal Zi
Instead, the output pulse train Vf is converted to a down counter CO2
(can also be used as a clock).

The PWM periodic signal Vca output to the inverter 30e becomes the borrow output of the down counter CO2.

[0047] Such a configuration will be explained with reference to FIG.

The input signal Vsb to the VCO 90 is shown in FIG.
), the PWM periodic signal Vcb shown in FIG.
It reaches its maximum at the rising edge of , and then decreases linearly with time.

That is, the output pulse train Vf is as shown in FIG. 2(d).
As shown in FIG. 2, the PWM periodic signal Vcb changes continuously during one period so that it becomes a higher frequency pulse at the beginning and becomes a lower frequency pulse at the period of the PWM periodic signal Vcb. In this case, the change in the width of the PWM signal when the dimming setting signal Ti changes by one bit is smaller at the beginning of the PWM cycle, that is, at low brightness than at high brightness.

That is, the frequency modulation can be set to a higher frequency when the brightness is low and to a lower frequency when the brightness is high, and can be repeatedly performed at the same period as the PWM period. In principle, this change in width can be made as small as possible and high resolution can be achieved at low brightness, so even when performing digital dimming control, digital changes in brightness can be made inconspicuous and smooth. This means that it is possible to realize kana dimming.

By the way, in order to set the brightness setting signal in accordance with the human eye, in the circuit of the prior art shown in FIG. A possible configuration is to input a setting signal).

In this case, as shown in FIG. 3, the signal Vi from the dimming setting signal generating circuit β1 is adjusted in accordance with the response of the human eye, which is quick to adapt to light and slow to adapt to dark.

More specifically, when the surroundings become bright, the signal Vi is immediately increased, that is, the brightness becomes high, and when the surroundings become dark, the signal Vi is gradually decreased, that is, the brightness is gradually decreased. Response correction circuit β2 for correcting
The corrected signal Vd is input to the A/D converter α1 via the A/D converter α1.

At this time, regarding the response correction circuit β2, the output signal Vd follows the input signal Vi as it is when it rises, and follows it exponentially with a time constant of RC when it falls. For example, a circuit configuration in which a resistor R and a capacitor C are arranged in parallel between a pair of amplifiers is generally considered.

However, since the signal Vd decreases exponentially, voltage changes are particularly slow in low brightness areas in a circuit configuration using resistors and capacitors, and the resolution is low when performing digital dimming control. If it is not high enough, the brightness change will feel discontinuous. This is particularly noticeable when the voltage changes slowly.

Therefore, in the present invention, such a problem is solved by making the voltage change linear in the response correction circuit β2a.

Specifically, the configuration shown in FIGS. 4 and 5 makes the voltage change linear.

In FIG. 4, a pair of amplifiers Q3 and Q4
The circuit has a circuit configuration in which a diode D is placed at the output terminal of the amplifier Q3, and a constant current source I and a capacitor C are placed in parallel between the diode D and the input terminal of the amplifier Q4.

FIG. 5 shows a more specific circuit configuration as a constant current source I; in this case, an NchFET
This shows a constant current circuit configuration in which a resistor R1 is inserted between the gate and source of the circuit. However, since the resistor R1 is for current adjustment, the gate and source of the NchFET may be short-circuited. Furthermore, it goes without saying that a PchFET, a low current diode, or the like may be used as the constant current circuit as long as the desired constant current characteristics can be obtained.

Let us now look at the rise and fall of the signal Vi in such a case.

(a): <At the time of rising> Diode D becomes conductive and capacitor C is charged up to Vi. Output voltage (V
As for d), the voltage of C appears as is, but since the charging time constant is small, it immediately follows the rise of the input voltage (Vi).

(b): <<At the time of falling>> Diode D becomes non-conductive, and the charge in capacitor C is discharged through the constant current circuit until Vi and Vd are balanced. Here, if the voltage of capacitor C is Vca and the constant current value is Ia, then dV
d/dt=dVca/dt=-(I/C), and the output signal Vd decreases linearly with time. The slope of this straight line is arbitrarily set by the values of C and I. In other words, since this allows the signal Vd to fall linearly, it is possible to eliminate the sense that brightness changes are discontinuous in digital dimming control.

<<Other Examples>> The present invention is not limited to the above examples.

(A): For example, dimming control signal generation circuit 3
In the case where a frequency modulated pulse is used as the 0 clock, a configuration is also possible in which arbitrary dimming characteristics can be realized. That is, as shown in FIG. 6, a frequency modulation circuit 31 is arranged between the zero cross detection circuit 5 and the dimming control signal generation circuit 30. This allows arbitrary dimming characteristics to be designed when performing digital dimming control.

A more specific embodiment of FIG. 6 (an example of a method for generating frequency-biased pulses) is shown in FIG.

In FIG. 7, the frequency modulation circuit 31 includes a programmable counter (÷M) 31a, a μP (microprocessor) 31b, and a PLL (phase locked loop) 31c.
It can be composed of. And furthermore, PLL3
1c is a phase comparator 31c1, a loop filter 31c2
, VCO31c3 and program counter (÷N)31
c4, and their mutual relationships are as shown in the figure.

At this time, the programmable counter (÷M
) 31a and the frequency division values of the program counter (÷N) 31c4 are controlled by μP 31b. Therefore, the zero cross signal Zi (frequency f) is calculated by the programmable counter (÷M)
31a divides the frequency by M, and the output frequency f/M is PLL3
1c, the program counter (
÷N) When the frequency of 31c4 is divided by N, the frequency (N/M)f of the output signal is obtained.

Note that the μP31b receives PWM as a control signal.
A periodic signal is input, and the above operation is repeated at the same period as the PWM period.

The explanation of FIG. 7 will be further explained using FIG. 8.

The frequency modulation circuit 31 can change the frequency of the clock used in the dimming control signal generation circuit 30, and by controlling the frequency with the μP 31b, the characteristics of the lamp and the way the human eye perceives it are taken into account. Desired dimming characteristics can be designed.

For example, if the clock is changed to a higher frequency at the beginning and a lower frequency at the end within the PWM cycle, the dimming characteristics can be made as shown in FIG. 8.

In FIG. 8, the broken line indicates the case where the clock cycle is constant, and it is assumed that the lamp is such that the dimming setting voltage and the brightness are proportional. This is an example that takes into consideration the way the human eye perceives, and means that smooth dimming can be performed by adjusting brightness with higher resolution when the brightness is low. In other words, it is possible to design arbitrary dimming characteristics in digital dimming control.

(B): In order to reduce digital brightness changes due to the influence of external noise, for example, a configuration as shown in FIG. 9 showing another embodiment of the present invention may be used. can. Note that FIG. 10 is a circuit block diagram showing a more specific embodiment of FIG. 9.

In FIG. 9, the on/off period calculation circuit 30
After a, a data switching circuit 32 is arranged and its output Wi
It is possible to adopt a configuration in which the PWM signal is loaded into the down counter C01 for generating a PWM signal. In this case, the data switching circuit 32 has two modes: Hi (hereinafter referred to as "Day mode") or Low (hereinafter referred to as "Night mode") digital signal ( A configuration may be adopted in which switching is performed using a mode switching signal (mode switching signal) S.

On the other hand, the mode switching signal S divides the brightness of the surroundings into two levels at a certain appropriate level.
t mode (this switching signal may be generated automatically, or may be selected using a switch, etc.). Therefore, the data switching circuit 32 transmits data that has a wide dimming range and low resolution in the Day mode, and data that has a narrow dimming range and high resolution in the Night mode. Data can be loaded into down counter C01.

In the data switching circuit 32 of FIG.
s is a data selector, which can be composed of 12 data selectors (signs Ds1 to Ds12). The relationship between the input and output terminals of the data selector Ds with respect to the mode switching signal S is that S is Da
When in y mode (i.e. Hi), the signal from input terminal A is output to output terminal D, and when S is in Night mode (i.e. L0
), the signal from input terminal B is output to output terminal D.

Here, the frequency and the number of bits of the counter are arbitrary, but in this embodiment, the frequency of the zero cross signal Zi is 100 KHz, and the frequency of the PWM signal P
It is assumed that the signal period of ia is 100 Hz, the clock of down counter C01 for PWM signal generation is 400 KHz, and the number of effective bits of the on/off period calculating circuit 30a is 10 bits. Then, a down counter C0 for PWM cycle generation
The number of bits of 2 is 10, the count number is 1000, and PW
Achieves M period of 100Hz. Further, it is assumed that the number of bits of the down counter C01 for PWM signal generation is 12.

The explanation of the data switching circuit 32 in FIG. 10 will be continued again. In Day mode, the lighting/off period calculation circuit 30
The 10 bits of the output data θi of a are set to the upper 10 bits of the 12-bit dimming setting signal Ti. Also, N
In the light mode, 10 bits of the output data θi are set to the lower 10 bits of the dimming setting signal Ti. or,
The remaining two bits of each mode are always at a low level. That is, 10 bits of output data θi are converted into θ9, θ8
,...θ0 (θ0 = LSB), the output Wi becomes the dimming setting signal based on the output data θi in each mode.
(However, i = 11, 10,... 0, W0 = LSB)
becomes as follows. │

││

[0079]

││Dimmer setting signal│W11 W10 W9 W8
W7 W6 W5 W4 W3 W2 W1 W0 │
Day mode θ9 θ8 θ7 θ6
θ5 θ4 θ3 θ2 θ1 θ0 0 0
Night mode 0 0 θ9 θ8
θ7 θ6 θ5 θ4 θ3 θ2 θ1 θ0

[
Therefore, when a PWM signal is generated according to the dimming setting signal Wi like this, each time the output data θi increases by "1", the count number becomes as follows in the Day mode.
4,8,12,...4092, 1 in Night mode,
It changes as 2, 3, ..., 1023. At this time, the width of the PWM signal is 4000 when the maximum brightness is D.
In ay mode 4/4000, 8/4000, 12
/4000 ,...4000/4000 (count number is 4
000 or higher, the brightness is always at maximum), Night mode
1/4000, 2/4000, 3/4000 in
,...,1023/4000.

That is, the dimming range is up to the maximum brightness in the Day mode, and is narrowed to about 1/4 of the maximum brightness in the Night mode. Also, the resolution is low at 4/4000 = 1/1000 compared to the maximum brightness in Day mode.
In Night mode, the brightness is 1/4000 of the maximum brightness.

[0082]

[Effects of the Invention] Since the present invention is constructed as described above, it produces the following effects. (b) It is possible to achieve smooth dimming by making digital changes in brightness less noticeable (resolving the problem that brightness changes feel discontinuous). (b) Arbitrary dimming characteristics can be designed. (c) Reducing digital brightness changes, which has been difficult to achieve due to the influence of noise, can be easily and stably achieved by configuring as shown in FIGS. 9 and 10. Note that it is also possible to take measures against noise at the input stage of the on/off period calculation circuit 30a to widen the dimming range and increase the resolution, but doing so will involve a considerable increase in cost. Above, the relationship between the characteristics required for lamp dimming and the surrounding brightness. In other words, when the surroundings are bright, the lamp needs to be brightened to its maximum brightness, but since the brightness changes are not very noticeable, the resolution can be a little low. If the surroundings are dark, it is not necessary to brighten up to the maximum brightness, but changes in brightness will be noticeable, so it is necessary to increase the resolution. (without leading to cost increase).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a specific embodiment of a fluorescent tube lighting device with dimming according to the present invention.

FIG. 2 is a time chart showing an outline of each voltage waveform for explaining FIG. 1;

FIG. 3 is a diagram for explaining the present invention.

FIG. 4 is a diagram for explaining the present invention.

FIG. 5 is a diagram for explaining the present invention.

FIG. 6 is a diagram for explaining another embodiment of the present invention.

FIG. 7 is a diagram for explaining FIG. 6;

FIG. 8 is a diagram for explaining FIG. 6;

FIG. 9 is a diagram showing another embodiment of the present invention.

FIG. 10 is a circuit block diagram showing a more specific embodiment of FIG. 9;

FIG. 11 is a block diagram showing the configuration of a conventional dimming fluorescent tube lighting device.

FIG. 12 is a block circuit diagram of a prior art dimmable fluorescent tube lighting device.

FIG. 13 is a diagram for explaining FIG. 12;

[Explanation of symbols]

1 Lamp (cold cathode fluorescent tube) 2, 20 Self-excited inverter (inverter) 3,
30, Dimming control signal generation circuit 4 Switch circuit 5 Lamp voltage synchronization pulse generation circuit (zero cross detection circuit) 6, 60 Dimming switch circuit 7 Multiplier circuit 80 Control voltage generator 31 Frequency modulation circuit

Claims (3)

[Claims] [Claim 1] DC power is supplied, the output of the secondary side of the transformer is supplied to the fluorescent tube, and the zero cross of the inverter output is detected and synchronized with the auxiliary winding terminal provided on the secondary side of the transformer. A self-excited inverter is connected to a lamp voltage synchronization pulse generation circuit that generates a pulse train, and a dimming setting signal and a signal from the lamp voltage synchronization pulse generation circuit are guided to control the dimming of the fluorescent tube in the inverter. - a dimming control generating circuit that dims the fluorescent tube by outputting a signal that operates a switch circuit to turn on or off or both in synchronization when the output of the fluorescent lamp is at zero potential; In a fluorescent tube lighting device with a light, a control voltage generator (81) uses the PWM periodic signal of the dimming control signal generation circuit (30) to generate a control voltage synchronized with the PWM periodic signal.
Then, in order to improve the resolution at low brightness and make digital brightness changes less noticeable, the control voltage from the control voltage generator is input and the output pulse train having a frequency proportional to the input voltage is controlled by the dimming control. A dimmable fluorescent tube lighting device comprising: a voltage controlled oscillator (90) outputting to a signal generating circuit; and the output of the voltage controlled oscillator is used as a clock in the dimming control signal generating circuit. Device. 2. The dimming fluorescent tube lighting device according to claim 1, wherein a frequency modulation circuit (31) is provided between the lamp voltage synchronization pulse generation circuit and the dimming control signal generation circuit, and the frequency modulation circuit PW of the dimming control signal generation circuit
A fluorescent light control device characterized in that frequency modulation is performed using an M-period signal and a signal from the lamp voltage synchronization pulse generation circuit, and the frequency modulated signal is used as a clock for the dimming control signal generation circuit. Tube lighting device. 3. The dimming fluorescent tube lighting device according to claim 1, wherein the dimming control signal generation circuit (30) includes a lighting/extinguishing period calculation circuit 30a for digitally converting an input dimming setting signal; Data switching that converts the digital signal from the lighting/extinguishing period calculation circuit into two mode signals and then outputs one of the mode signals to the means for generating the PWM periodic signal using a mode switching signal. A fluorescent tube lighting device with a dimming function, characterized in that a circuit 32 is arranged.