JPH04288783A - Clock generation circuit for video equipment - Google Patents

Abstract

PURPOSE:To prevent superimposed display from being horizontally shifted by dividing the frequency of an oscillation output from the clock generating circuit of a video equipment, generating a video clock for superimpose and resetting it according to a horizontal synchronizing signal. CONSTITUTION:The frequency of an output signal from a crystal oscillator 21 is divided by frequency dividers 22 and 23, and horizontal and vertical synchronizing signals HD and VD and a field index signal FI are prepared from one of those frequency-divided signals. The horizontal synchronizing signal HD is also used as the reset signal of a timing generating circuit 25 and the frequency divider 23. The other signal is generated into a video clock and further, a timing signal is prepared at a timing generation circuit 25. A character signal generating circuit 27 generates a selection control signal from these signals and generates a display character signal synchronously with the video clock. Thus, since the frequency divider 23 to generate the video clock is reset by the horizontal synchronizing signal HD, a character to be superimposed during each horizontal scanning period is not horizontally shifted and video quality is improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for a video device, and more particularly to a clock generation circuit for a video device that generates a clock synchronized with vertical and horizontal synchronization signals.

[0002] In recent years, images obtained by visible or infrared sensors are usually digitized, subjected to various signal processing, superimposed with characters, etc., and displayed on a monitor receiver. Therefore, in the video device, it is necessary to generate vertical and horizontal synchronization signals of the video signal and a video clock that indicates the pixel position of the character to be superimposed.

0003

2. Description of the Related Art FIG. 3 shows a block diagram of a conventional clock generation circuit.

In the figure, the frequency 10 output from the oscillator 10
The oscillation signal of several MHz is supplied to frequency dividers 11 and 12. The frequency divider 11 divides the frequency of the oscillation signal to generate and output a video clock having a frequency of 1 to 2 MHz. The frequency divider 12 divides the oscillation signal to give a frequency of 15.75 k in the case of monochrome.
A horizontal synchronizing signal of Hz is generated and output, and the output of the frequency divider 12 is supplied to a frequency divider 13, which generates and outputs a vertical synchronizing signal of a frequency of 60 Hz.

[0005]

In the conventional circuit, a video clock and a horizontal synchronization signal are separately generated from an oscillation signal by frequency dividing circuits 11 and 12, respectively. Therefore, unless the oscillation signal frequency is a common multiple of the video clock frequency and the horizontal synchronization signal frequency, the video clock and the horizontal synchronization signal cannot be synchronized. If the above-mentioned synchronization was not achieved, there would be a problem that the vertical lines of characters, figures, etc. to be superimposed would shift horizontally from line to line, as shown in FIG.

Furthermore, if the oscillation signal frequency is made the least common multiple of the video clock frequency and the horizontal synchronization signal frequency, the above deviation will disappear, but the oscillation signal frequency will be several hundred MHz, and the circuit scale of the oscillator 10 and frequency dividers 11 and 12 will be reduced. There was a problem in that it became large and was not suitable for practical use.

[0007] The present invention has been made in view of the above points.
It is an object of the present invention to provide a clock generation circuit for a video device that does not require an increase in oscillation signal frequency and prevents a horizontal shift in superimposed display.

[0008]

[Means for Solving the Problems] A clock generation circuit of a video device of the present invention frequency-divides an oscillation signal output from an oscillator to generate a horizontal synchronization signal and a vertical synchronization signal of a standard video signal, and also generates a horizontal synchronization signal and a vertical synchronization signal of a standard video signal. In a clock generation circuit of a video device that separately divides the frequency to generate a video clock for superimposition, the frequency divider that divides the frequency of an oscillation signal to generate the video clock is reset by a horizontal synchronization signal.

[0009]

In the present invention, the frequency divider that generates the video clock is reset by the horizontal synchronization signal, so that the phases of the video clock in each horizontal scanning period are aligned, and the vertical lines of the superimposed characters are aligned.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of an embodiment of the circuit of the present invention.

In the figure, an oscillation signal with a frequency of 10-odd MHz outputted from a crystal oscillator 21 is supplied to frequency dividers 22 and 23, respectively. The frequency divider 22 divides the frequency of the oscillation signal to approximately 2 MHz and supplies it to the synchronization signal generation circuit 24. The synchronization signal generation circuit 24 divides the supplied signal and in the case of monochrome, specifies a horizontal synchronization signal (HD) with a frequency of 15.75 kHz, a vertical synchronization signal (VD) with a frequency of 60 Hz, and an odd field/even field. A field index signal (FI) with a frequency of 30 Hz is generated and supplied to the character signal generation circuit 27, and a composite synchronization signal obtained by superimposing a horizontal synchronization signal and a vertical synchronization signal is supplied to the D/A converter 28. . Further, the horizontal synchronization signal (HD) is supplied to each of the frequency divider 23 and the timing signal generation circuit 25 as a reset signal.

The frequency divider 23 is reset each time a horizontal synchronizing signal is received, divides the frequency of the oscillation signal, generates a video clock having a frequency of 1 to 2 MHz, and supplies the video clock to the timing signal generation circuit 25. The timing signal generation circuit 25 is reset each time a horizontal synchronization signal is received, counts the video clock, and generates a timing signal for instructing the horizontal display period. /A converters 28 respectively.

Further, a digital signal of an image obtained by a visible sensor or an infrared sensor is input to the terminal 30, and the signal processing circuit 26 converts the scanning method of the sensor to the raster scanning method of a normal television. Then, signal processing such as filtering and edge emphasis is performed, and the processed digital signal is output in synchronization with the video clock during the display period specified by the timing signal and supplied to the selector 31.

The character signal generation circuit 27 uses vertical and horizontal synchronization signals and field index signals to determine the superimpose display position and generate a selection control signal, and also generates a digital signal of a character to be displayed in synchronization with the video clock. The selection control signal and character digital signal are supplied to the selector 31. The selector 31 normally selects the image digital signal from the signal processing circuit 26 under the control of the selection control signal, selects the character digital signal at the superimposed display position, and supplies it to the D/A converter 28.

The D/A converter 28 converts the digital signal from the selector 31 into an analog signal, adds it to the composite synchronization signal from the synchronization signal generation circuit 24 to generate a composite video signal, and supplies it to the monitor receiver from the terminal 32. .

As described above, the frequency divider 23 that generates the video clock is reset by the horizontal synchronizing signal (HD), so the video clocks are in phase in each horizontal scanning period (on the line), and the superinput As shown in FIG. 2, the vertical lines of characters such as letters and figures that pose poses are aligned without horizontal deviation, improving the quality of the image.

[0017]

As described above, according to the clock generation circuit of the video device of the present invention, it is not necessary to increase the oscillation signal frequency, and horizontal shifts in the superimposed display can be prevented, and the quality of the video can be improved. and is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the circuit of the present invention.

FIG. 2 is a diagram showing an example of superimposed display by the circuit of the present invention.

FIG. 3 is a block diagram of an example of a conventional circuit.

FIG. 4 is a diagram showing an example of superimposed display by a conventional circuit.

[Explanation of symbols]

21 Crystal oscillator 22, 23 Frequency divider 24 Synchronization signal generation circuit

Claims (1)

[Claims] 1. An oscillation signal output from an oscillator (21) is frequency-divided to generate a horizontal synchronization signal and a vertical synchronization signal of a standard video signal, and the oscillation signal is separately frequency-divided to generate a superimposed video signal. A clock generation circuit for a video device that generates a clock, wherein a frequency divider (23) that divides the frequency of the oscillation signal to generate a video clock is reset by the horizontal synchronization signal. .