JPH04287256A - System for detecting fault of output buffer - Google Patents

Abstract

PURPOSE:To offer a system for detecting faults of output buffers which can detect the fault of an output buffer with a simple configuration for the transmission of data signals from one device to plural devices through output buffers. CONSTITUTION:A two-input check circuit 2 which inputs the input and output signals of each output buffer 1 is provided. The circuit 2 is constituted in such a way that the circuit 2 compares the two signals from each output buffer 1 and, when the signals are not coincident, generates a fault detect signal to each output buffer 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer failure detection method in the transfer of data signals through an output buffer. The technology of providing multiple controlled devices (to be controlled) for a controlling device and transmitting the same data signal from the controlling device to the multiple controlled devices is used in information processing, communication, control, etc. It is used in various systems. In such cases, the data signal is transmitted via an output buffer, and if a failure occurs in the output buffer, the system will operate incorrectly, so it is desirable to efficiently detect failures in the output buffer. .

0002

2. Description of the Related Art FIG. 6 is a diagram showing a conventional wiring system for transmitting data signals. A device B group consisting of a plurality of devices B1 to Bn controlled by a certain device A is provided,
A technique is used to make the data signals from device A to device B group the same. Note that even if the data signals are the same, each device B1
~Bn may be configured to identify the destination (address) included in the data signal, take in only the data addressed to itself, and ignore data not addressed to itself. As an example of a device having such a configuration, an upper subscriber control circuit is provided for multiple subscriber circuits in an exchange, and control data signals are transmitted from the subscriber control circuit to each subscriber circuit. There is a device that controls the

[0003] As a wiring configuration in such a case, (a)
．． The multi-wiring method uses a common output buffer as shown in (b). There is a star wiring method in which individual output buffers are provided corresponding to each of the devices B1 to Bn, as shown in FIG. Among these (a). The multi-wiring method shown in Figure 1 is a method that can be used to suspend device A and other devices B when a failure occurs in one device B, for example, when insertion and removal (hot insertion and removal) must be performed while the power is on in device B group. If faulty device B is inserted or removed without doing this, noise will be induced in the data signal line, resulting in other devices receiving erroneous data signals. Furthermore, if the output buffer becomes faulty, all the data lines will become stuck (fixed), and all the devices B sharing the data signal line will not be able to receive data signals normally. On the other hand, (b). In the star wiring method, an output buffer is individually provided for each of the device group B, so it is not affected by the hot insertion and removal as described above.

0004

[Problem to be solved by the invention] (b) of the above conventional example
．． In the star wiring method, it is necessary to provide output buffers according to the number of devices in the device group B, so there is a problem in that the probability of occurrence of a failure in the output buffers increases accordingly. SUMMARY OF THE INVENTION An object of the present invention is to provide an output buffer failure detection method that can detect output buffer failures with a simple configuration.

[0005]

[Means for Solving the Problems] FIG. 1 is a first principle diagram of the present invention, and FIG. 2 is a second principle diagram of the present invention. Figure 1 shows the configuration for detecting faults in individual output buffers, and Figure 2 shows the configuration for detecting faults in output buffers in the case of star wiring. The 2-input check circuit 3 is an n+1-input check circuit which receives an input signal and the output of each output buffer when there are n output buffers. The present invention provides a check circuit for detecting an abnormal output that is different from a normal signal output that should be output with respect to an input signal of an output buffer.

[0006]

[Operation] It is assumed that the output buffer 1 shown in FIG. 1 is a non-invert buffer. The check circuit 2 is constituted by a circuit that checks whether the two inputs, which are the input signal and the output signal of the output buffer 1, are the same. 2
If the input signals do not match, an output is generated indicating a failure. Furthermore, if the output buffer 1 is an invert buffer, the check circuit 2 checks whether the two input signals are different, and if they match, generates an output indicating a failure. When the output buffer 1 is an invert buffer, the check circuit 2 can detect a failure in the output buffer 1 by checking whether two input signals match.

Next, in FIG. 2, output buffers 1-1 to
Each of the output signals 1-n is input to the check circuit 3, and the input signal is also input. The check circuit 3 checks the state of the n+1 signal and generates a corresponding signal output if it is in a normal operating state, and generates an output indicating the failure if one of the output buffers is in failure. The check function of the check circuit 3 may be changed depending on whether the output buffers 1-1 to 1-n are non-invert buffers or invert buffers.

[0008]

Embodiment FIG. 3 is a block diagram of the first embodiment. FIG. 4 is a configuration diagram of the second embodiment, and FIG. 5 is another configuration diagram of the second embodiment. The configuration of FIG. 3 is the configuration of an embodiment corresponding to the first principle diagram shown in FIG. 1 above. In FIG. 3, 30 is an output buffer (corresponding to 1 in FIG. 1), and 31 is an exclusive OR circuit (EOR circuit).
(represented by a circuit) (corresponds to check circuit 2 in FIG. 1). An operation diagram 32 shows the operation of the EOR circuit 31 when the output buffer 1 is a non-invert buffer. According to this operation diagram, when the input value and output value of the output buffer are the same, the EOR circuit 31 generates an "L" output (normal),
If the two are different, it indicates that the output buffer is abnormal.
If the output buffer 30 is an invert buffer, by inverting the output of the EOR circuit 31, a logic output indicating normality or abnormality similar to the case of FIG. 3 is generated.

Next, the structure of the second embodiment shown in FIG. 4 and the other structure of the second embodiment shown in FIG. 5 will be explained. These structures are both examples corresponding to the second principle diagram of FIG. 4 and 5, 40-1 to 40-n are a plurality of output buffers (corresponding to 1-1 to 1-n in FIG. 2), 41(
4) and 42 (FIG. 5) are parity generation circuits (represented by PG circuits), in which the multi-input check circuit 3 of FIG. 2 is realized by a parity generation circuit. A in FIG. In the configuration, each of the output buffers 40-1 to 40-n is a non-invert buffer, and the configuration is such that the number n of output buffers is an odd number, and the parity generation circuit 41 generates even parity. .

The operation of this configuration is shown in B. of FIG. As shown in the operation table, when the input signal to each output buffer 40-1 to 40-n is "L", if each output buffer is normal, the output of the parity generation circuit 41 is also "L" ( (This is because all inputs are "L" and "H" is zero). Also,
Even when the input signal is "H", the output signal is "L" (because there is an even number of "H" inputs). However, the input signal is “L”
”, the odd number of output buffers (1, 3
) becomes an "H" stack fault, the output of the parity generation circuit 41 becomes "H" to indicate fault detection. Further, when the input to each output buffer is "H", if an odd number of output buffers become "L" stuck, the output of the parity generation circuit 41 becomes "H". Therefore, if the output of the parity generation circuit 41 is "H", it indicates that a failure has occurred in the output buffers 40-1 to 40-n.

Even with the configuration shown in FIG. 4, it is not possible to deal with all failures, in which case the failure is displayed as not detected in the operation table. However, in general, data signal lines carry "L" and "H" level data, and the probability of multiple output buffer failures occurring at the same time is extremely low, so this operation is not recommended. If there is a fault detection function shown in the figure, it is possible to effectively detect faults. In the embodiment configuration of FIG. 5, each output buffer 40-1 to 40-
n is a non-invert buffer, and this is the configuration when the number n of output buffers is an even number, and unlike the case in FIG. 4, the input signal is not input to the parity generation circuit 41, and the circuit generates even parity. The operation is performed according to the same operation diagram as in the case of FIG. Even with this configuration, failure cannot be detected in the same case as in FIG. 4, but it is possible to perform effective failure detection.

0012

According to the present invention, a fault in an output buffer can be detected with a simple additional circuit. In particular, when a parity generation circuit is used, failure detection for a plurality of output buffers can be realized with one additional circuit for a plurality of signal lines.

[Brief explanation of the drawing]

FIG. 1 is a first principle diagram of the present invention.

FIG. 2 is a second principle diagram of the present invention.

FIG. 3 is a configuration diagram of Example 1.

FIG. 4 is a configuration diagram of a second embodiment.

FIG. 5 is another configuration diagram of the second embodiment.

FIG. 6 is a diagram showing a conventional wiring system for transmitting data signals.

[Explanation of symbols]

Claims (2)

[Claims] Claim 1: In an output buffer failure detection method for transmitting data signals from one device to multiple devices via respective output buffers, a two-input check circuit is provided that receives input signals and output signals of each output buffer. An output buffer failure detection method, wherein the check circuit generates an output buffer failure detection signal if the two signals are not normal by comparing the two signals. 2. In an output buffer failure detection method in the transmission of data signals from one device to a plurality of devices via respective output buffers, a check circuit is provided which receives an input signal and an output signal of each buffer as input, An output buffer failure detection system, wherein the circuit generates an output signal representative of normal conditions in the input and output signals and a failure of at least one output buffer.