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JPH04286356A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH04286356A
JPH04286356A JP3051419A JP5141991A JPH04286356A JP H04286356 A JPH04286356 A JP H04286356A JP 3051419 A JP3051419 A JP 3051419A JP 5141991 A JP5141991 A JP 5141991A JP H04286356 A JPH04286356 A JP H04286356A
Authority
JP
Japan
Prior art keywords
film
high dielectric
electrode layer
dielectric constant
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3051419A
Other languages
Japanese (ja)
Inventor
Takashi Kato
隆 加藤
Fumitake Mieno
文健 三重野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3051419A priority Critical patent/JPH04286356A/en
Publication of JPH04286356A publication Critical patent/JPH04286356A/en
Withdrawn legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To provide a semiconductor device which is provided with a capacitor suitable for the memory cell of a DRAM (dynamic random access memory), enhanced in surface area by making its surface rugged, and hardly deteriorating in dielectric breakdown strength even if a dielectric film of high dielectric constant is used. CONSTITUTION:The method includes a first process where a first electrode layer 12 whose surface is rugged is formed, a second process where a high dielectric film 14 high in dielectric constant is provided onto the surface of the first electrode layer 12, and a third process where an insulating film 16 is formed oxidizing or nitriding a part near an interface between the high dielectric film 14 and the first electrode layer 12 through a heat treatment carried out in an oxidizing atmosphere or a nitriding atmosphere.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体装置、特にDRA
M(ダイナミックランダムアクセスメモリ)のメモリセ
ルに用いるのに適したキャパシタを有する半導体装置及
びその製造方法に関する。
[Industrial Application Field] The present invention relates to semiconductor devices, particularly DRA
The present invention relates to a semiconductor device having a capacitor suitable for use in an M (dynamic random access memory) memory cell, and a method for manufacturing the same.

【0002】0002

【従来の技術】DRAMのメモリセルを構成するキャパ
シタは、下部電極と上部電極間に誘電体膜を挟んだ構造
をしている。従来のDRAMでは誘電体膜としてシリコ
ン酸化膜を用いられている。DRAMの集積度の向上の
伴ってシリコン酸化膜の膜厚がますます薄くなってきて
おり、シリコン酸化膜を薄膜化してキャパシタの容量を
確保するには、信頼性の点で薄膜化の限界に近付いてい
る。
2. Description of the Related Art A capacitor constituting a memory cell of a DRAM has a structure in which a dielectric film is sandwiched between a lower electrode and an upper electrode. In conventional DRAMs, a silicon oxide film is used as a dielectric film. As the degree of integration of DRAMs increases, the thickness of silicon oxide films is becoming thinner and thinner, and in order to ensure capacitor capacity by thinning silicon oxide films, we are reaching the limits of thinning in terms of reliability. It's approaching.

【0003】そこで、キャパシタの容量を大きくするた
めに、下部電極表面を凹凸にして面積を増加させる方法
や、誘電体膜としてシリコン酸化膜より誘電率の高い高
誘電体膜を用いる方法が考えられている。
Therefore, in order to increase the capacitance of a capacitor, methods have been considered such as increasing the area by making the surface of the lower electrode uneven, and using a high dielectric film having a higher dielectric constant than a silicon oxide film as the dielectric film. ing.

【0004】0004

【発明が解決しようとする課題】しかしながら、下部電
極表面を凹凸にして面積を増加させる方法では、凹凸の
ある表面にシリコン酸化膜を形成すると、図4に示すよ
うに、鋭角部に応力が集中するため成長するシリコン酸
化膜が薄くなり、この鋭角部で絶縁破壊が起きて絶縁耐
圧が劣化するという問題があった。
[Problems to be Solved by the Invention] However, in the method of increasing the area by making the surface of the lower electrode uneven, when a silicon oxide film is formed on the uneven surface, stress is concentrated at the acute corners as shown in FIG. As a result, the silicon oxide film that grows becomes thinner, and dielectric breakdown occurs at these acute corners, resulting in a decrease in dielectric strength.

【0005】誘電率の高い高誘電体膜を用いる方法では
、高誘電体材料はもともとリーク電流が大きく耐圧が小
さい材質であるため、薄膜化することが困難であり、容
量の大きなキャパシタを形成することが困難であるとい
う問題があった。本発明の目的は、表面を凹凸にして面
積を増加させ、誘電率の高い高誘電体膜を用いても、絶
縁耐圧が劣化することのないキャパシタを有する半導体
装置及びその製造方法を提供することにある。
[0005] In the method of using a high dielectric film with a high dielectric constant, it is difficult to make the film thin because the high dielectric material originally has a large leakage current and a low withstand voltage, and it is difficult to form a capacitor with a large capacitance. The problem was that it was difficult to An object of the present invention is to provide a semiconductor device having a capacitor whose dielectric strength does not deteriorate even when the surface is made uneven to increase the area and a high dielectric constant film is used, and a method for manufacturing the same. It is in.

【0006】[0006]

【課題を解決するための手段】本発明の原理を図1及び
図2を用いて説明する。シリコン基板10上に下部電極
層12が形成され、面積を増大させるために下部電極層
12の表面を凹凸にしておく。下部電極層12上に誘電
率の高い高誘電体膜14を形成した後、酸化雰囲気中又
は窒化雰囲気中で熱処理すると、下部電極層12と高誘
電体膜14の界面近傍が酸化(界面酸化)又は窒化(界
面窒化)され、図1(a)に示すように、下部電極層1
2と高誘電体膜14の間に絶縁膜16が形成される。高
誘電体膜14により鋭角部における応力が緩和され、均
一な膜厚の絶縁膜16が形成される。
[Means for Solving the Problems] The principle of the present invention will be explained using FIGS. 1 and 2. A lower electrode layer 12 is formed on a silicon substrate 10, and the surface of the lower electrode layer 12 is made uneven to increase its area. After the high dielectric constant film 14 with a high dielectric constant is formed on the lower electrode layer 12, when heat treatment is performed in an oxidizing atmosphere or a nitriding atmosphere, the vicinity of the interface between the lower electrode layer 12 and the high dielectric constant film 14 is oxidized (interfacial oxidation). or nitrided (interfacial nitrided), as shown in FIG. 1(a), the lower electrode layer 1
An insulating film 16 is formed between the high dielectric constant film 14 and the high dielectric constant film 14 . The high dielectric film 14 relieves stress at the acute angle portion, and an insulating film 16 with a uniform thickness is formed.

【0007】なお、鋭角部における応力を確実に緩和す
るためには、高誘電体膜14の膜厚が絶縁膜16の膜厚
より厚いことが望ましい。また、凹凸のある下部電極層
12上に形成された高誘電体膜14の膜厚が、鋭角部で
薄くなったとしても、酸化雰囲気中又は窒化雰囲気中で
熱処理したとき、鋭角部では薄くなって種が通りやすく
なった又は応力により種が通りやすくなった高誘電体膜
14を透過して多くの酸化種又は窒化種が界面に作用す
るため、図1(b)に示すように、高誘電体膜14の薄
い鋭角部における絶縁膜16が厚くなり、絶縁耐圧の低
い部分が自然に修復される。
[0007] In order to reliably relieve the stress at the acute angle portion, it is desirable that the high dielectric constant film 14 be thicker than the insulating film 16. Furthermore, even if the film thickness of the high dielectric constant film 14 formed on the uneven lower electrode layer 12 becomes thinner at the acute corner portions, it becomes thinner at the acute corner portions when heat treated in an oxidizing atmosphere or a nitriding atmosphere. As shown in FIG. 1(b), many oxidizing or nitriding species pass through the high dielectric constant film 14, which has become easier for seeds to pass through due to stress, and act on the interface. The insulating film 16 becomes thicker at the thin acute corner portions of the dielectric film 14, and the portions with low dielectric strength are naturally repaired.

【0008】さらに、図2に示すように、酸化雰囲気中
又は窒化雰囲気中で熱処理する代わりに、酸化雰囲気中
で熱処理し界面酸化して、下部電極層12と高誘電体膜
14間に酸化膜16aを形成した後に、窒化雰囲気中で
熱処理し界面窒化して、下部電極層12と酸化膜16a
間に窒化膜16bを形成してもよい。なお、逆に、界面
窒化した後に界面酸化してもよい。
Furthermore, as shown in FIG. 2, instead of heat treatment in an oxidizing atmosphere or nitriding atmosphere, an oxide film is formed between the lower electrode layer 12 and the high dielectric constant film 14 by performing a heat treatment in an oxidizing atmosphere to oxidize the interface. After forming the lower electrode layer 12 and the oxide film 16a, heat treatment is performed in a nitriding atmosphere to nitride the interface.
A nitride film 16b may be formed in between. Note that, conversely, interfacial oxidation may be performed after interfacial nitridation.

【0009】[0009]

【作用】このように本発明によれば、表面が凹凸の第1
電極層上に誘電率の高い高誘電体膜を形成した後に、酸
化雰囲気中又は窒化雰囲気中で熱処理して、高誘電体膜
と第1電極層との界面近傍を酸化又は窒化して絶縁体膜
を形成するようにしたので、凹凸の鋭角部における応力
が緩和され、誘電率の高い高誘電体膜を用いても、絶縁
耐圧が劣化することがない。
[Operation] According to the present invention, as described above, the first
After forming a high dielectric film with a high dielectric constant on the electrode layer, heat treatment is performed in an oxidizing atmosphere or a nitriding atmosphere to oxidize or nitride the vicinity of the interface between the high dielectric film and the first electrode layer to form an insulator. Since a film is formed, the stress at the acute angle portions of the unevenness is relaxed, and even if a high dielectric film with a high dielectric constant is used, the dielectric breakdown voltage does not deteriorate.

【0010】0010

【実施例】本発明の一実施例による半導体装置の製造方
法を図3を用いて説明する。本実施例ではDRAMのメ
モリセルのキャパシタに本発明を適用している。まず、
シリコン基板20の素子領域に窒化膜(図示せず)を形
成し、フィールド酸化してフィールド酸化膜22を形成
する。続いて、窒化膜を除去して素子領域のシリコン基
板20表面を露出させる(図3(a))。
Embodiment A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. In this embodiment, the present invention is applied to a capacitor of a DRAM memory cell. first,
A nitride film (not shown) is formed in the element region of the silicon substrate 20, and field oxidation is performed to form a field oxide film 22. Subsequently, the nitride film is removed to expose the surface of the silicon substrate 20 in the element region (FIG. 3(a)).

【0011】次に、ゲート酸化膜24を形成し、通常の
CVD法により多結晶シリコンを堆積し、パターニング
してワードラインであるゲート電極26を形成する。続
いて、ゲート電極26をマスクとして、シリコン基板2
0表面にAsをイオン注入し、不純物領域28、30を
形成する。続いて、BPSG膜32を形成した後、90
0℃でアニールして、BPSG膜32をメルトして平坦
化すると共に、不純物領域28、30を活性化する。続
いて、BPSG膜32に不純物領域30へのコンタクト
ホールを開口する。
Next, a gate oxide film 24 is formed, and polycrystalline silicon is deposited by the usual CVD method and patterned to form a gate electrode 26 which is a word line. Next, using the gate electrode 26 as a mask, the silicon substrate 2 is
As ions are implanted into the 0 surface to form impurity regions 28 and 30. Subsequently, after forming the BPSG film 32,
Annealing is performed at 0° C. to melt and planarize the BPSG film 32 and to activate the impurity regions 28 and 30. Subsequently, a contact hole to the impurity region 30 is opened in the BPSG film 32.

【0012】続いて、圧力が0.1〜0.2Torrで
、温度が570℃で、シラン(SiH4)を200sc
cmの流量でながす減圧CVD条件で、BPSG膜32
上に多結晶シリコンを堆積させると、表面が凹凸な多結
晶シリコン電極層(蓄積電極層)34が形成される。 多結晶シリコン電極層34全体の膜厚を300nmとす
ると、表面に約100nm程度の凹凸が形成される。こ
れにより、形成されるキャパシタの表面積は2倍近く増
加する。
[0012] Next, silane (SiH4) was applied for 200 sc at a pressure of 0.1 to 0.2 Torr and a temperature of 570°C.
The BPSG film 32 was deposited under low pressure CVD conditions at a flow rate of cm.
When polycrystalline silicon is deposited thereon, a polycrystalline silicon electrode layer (storage electrode layer) 34 having an uneven surface is formed. If the entire film thickness of the polycrystalline silicon electrode layer 34 is 300 nm, irregularities of about 100 nm are formed on the surface. This nearly doubles the surface area of the formed capacitor.

【0013】続いて、テトラエトキシタンタルをソース
ガスとするプラズマCVDにより、表面が凹凸の多結晶
シリコン電極層34上に誘電率の高い(比誘電率=20
)酸化タンタル(Ta2O5)を3nm成長させて高誘
電体膜36を形成する。続いて、多結晶シリコン電極層
34と高誘電体膜36をパターニングする(図3(b)
)。
Next, by plasma CVD using tetraethoxy tantalum as a source gas, a film having a high dielectric constant (relative dielectric constant = 20
) A high dielectric constant film 36 is formed by growing tantalum oxide (Ta2O5) to a thickness of 3 nm. Subsequently, the polycrystalline silicon electrode layer 34 and the high dielectric constant film 36 are patterned (FIG. 3(b)).
).

【0014】次に、ドライ酸素雰囲気中で、約900℃
で熱処理することにより、多結晶シリコン電極層34と
高誘電体膜36の界面に約1nmのシリコン酸化膜38
を成長(界面酸化)させる。高誘電体膜36を形成する
酸化タンタルの比誘電率は、シリコン酸化膜38の比誘
電率(=4)の約5倍あるので、3nm厚の高誘電体膜
36と1nm厚のシリコン酸化膜38が積層された誘電
体膜は、約1.6nm(=3[nm]/5+1[nm]
=0.6[nm]+1[nm])の厚さのシリコン酸化
膜に相当することになる。なお、界面酸化における熱処
理は、電気炉により加熱しても、光(レーザー、紫外線
、赤外線等)を用いたRTA(Rapid Therm
al Aneal) でもよく、更に、プラズマを利用
した熱処理でもよい。 特に光加熱を用いれば、高誘電体膜36の屈折率が大き
く反射防止膜となるので界面だけが集中的に加熱され、
界面窒化及び界面酸化に有利となる。
Next, in a dry oxygen atmosphere, the temperature is about 900°C.
By heat treatment, a silicon oxide film 38 of approximately 1 nm thick is formed at the interface between the polycrystalline silicon electrode layer 34 and the high dielectric constant film 36.
grows (interfacial oxidation). The relative dielectric constant of tantalum oxide forming the high dielectric film 36 is about five times that of the silicon oxide film 38 (=4), so the 3 nm thick high dielectric film 36 and the 1 nm thick silicon oxide film The dielectric film on which 38 is laminated has a thickness of approximately 1.6 nm (=3 [nm]/5+1 [nm]
This corresponds to a silicon oxide film with a thickness of 0.6 [nm] + 1 [nm]). Note that heat treatment for interfacial oxidation can be performed by RTA (Rapid Thermal Treatment) using light (laser, ultraviolet rays, infrared rays, etc.) even if heated in an electric furnace.
Al Aneal) may be used, or heat treatment using plasma may be used. In particular, if optical heating is used, the high dielectric constant film 36 has a large refractive index and serves as an antireflection film, so only the interface is heated intensively.
This is advantageous for interfacial nitriding and interfacial oxidation.

【0015】続いて、CVD法によりタングステン又は
窒化チタンからなる上部電極層40を形成する。続いて
、全面に層間絶縁膜42を堆積した後、ビットコンタク
トを開口し、アルミニウム又はシリサイドからなるビッ
トライン44を形成し(図3(c))、最後にカバー膜
(図示せず)を堆積する。本発明は上記実施例に限らず
種々の変形が可能である。
Subsequently, an upper electrode layer 40 made of tungsten or titanium nitride is formed by CVD. Subsequently, after depositing an interlayer insulating film 42 on the entire surface, a bit contact is opened, a bit line 44 made of aluminum or silicide is formed (FIG. 3(c)), and finally a cover film (not shown) is deposited. do. The present invention is not limited to the above embodiments, and various modifications are possible.

【0016】例えば、上記実施例では酸化雰囲気中で熱
処理して、多結晶シリコン電極層34と高誘電体膜36
の界面を酸化(界面酸化)したが、窒化雰囲気中で界面
窒化して、多結晶シリコン電極層34と高誘電体膜36
の間にシリコン窒化膜を形成してもよい。この窒化雰囲
気としてN2H4ヒドラジンを用いれば反応性、透過性
に優れており有利である。しかも、反応性にすぐれてい
るので窒化温度が800〜900℃と低温で可能である
For example, in the above embodiment, the polycrystalline silicon electrode layer 34 and the high dielectric constant film 36 are heated in an oxidizing atmosphere.
The interface was oxidized (interfacial oxidation), but the interface was nitrided in a nitriding atmosphere, and the polycrystalline silicon electrode layer 34 and the high dielectric constant film 36
A silicon nitride film may be formed in between. It is advantageous to use N2H4 hydrazine as the nitriding atmosphere since it has excellent reactivity and permeability. Moreover, since it has excellent reactivity, nitriding can be performed at a low temperature of 800 to 900°C.

【0017】また、多結晶シリコン電極層34と高誘電
体膜36の界面を熱処理するときに、最初は酸化雰囲気
中で熱処理(界面酸化)し、その後、窒化雰囲気中で熱
処理(界面窒化)してもよい。逆に、界面窒化した後に
界面酸化してもよい。さらに、上記実施例では高誘電体
膜として酸化タンタルを用いたが、ジルコニウム(Zr
)、チタン(Ti)、ハフニウム(Hf)、バナジウム
(V)、ニオブ(Nb)等の3A族、4A族又は5A族
の酸化物(ZrO2  、TiO2、HfO2、V2O
5、Nb2O5等)でもよい。
Furthermore, when heat-treating the interface between the polycrystalline silicon electrode layer 34 and the high dielectric constant film 36, the interface is first heat-treated in an oxidizing atmosphere (interfacial oxidation), and then heat-treated in a nitriding atmosphere (interfacial nitridation). It's okay. Conversely, interfacial oxidation may be performed after interfacial nitridation. Furthermore, although tantalum oxide was used as the high dielectric film in the above embodiment, zirconium (Zr
), titanium (Ti), hafnium (Hf), vanadium (V), niobium (Nb), etc. Group 3A, group 4A, or group 5A oxides (ZrO2, TiO2, HfO2, V2O
5, Nb2O5, etc.).

【0018】[0018]

【発明の効果】以上の通り、本発明によれば、表面が凹
凸の第1電極層上に誘電率の高い高誘電体膜を形成した
後に、酸化雰囲気中又は窒化雰囲気中で熱処理して、高
誘電体膜と第1電極層との界面近傍を酸化又は窒化して
絶縁体膜を形成するようにしたので、凹凸の鋭角部にお
いて応力が緩和され、誘電率の高い高誘電体膜を用いて
も、絶縁耐圧が劣化することがなく、絶縁耐圧が高く、
しかも対向面積を増加させたキャパシタを実現すること
ができる。
As described above, according to the present invention, a high dielectric constant film having a high dielectric constant is formed on a first electrode layer having an uneven surface, and then heat-treated in an oxidizing atmosphere or a nitriding atmosphere. Since an insulating film is formed by oxidizing or nitriding the vicinity of the interface between the high dielectric film and the first electrode layer, stress is relaxed at the acute corners of the unevenness, and a high dielectric film with a high dielectric constant is used. The dielectric strength voltage is high, and the dielectric strength voltage does not deteriorate even when
Moreover, a capacitor with an increased opposing area can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の原理図である。FIG. 1 is a diagram showing the principle of the present invention.

【図2】本発明の原理図である。FIG. 2 is a diagram of the principle of the present invention.

【図3】本発明の一実施例による半導体装置の製造方法
を示す工程断面図である。
FIG. 3 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図4】凹凸のある面上に形成されたシリコン酸化膜の
断面形状を示す図である。
FIG. 4 is a diagram showing a cross-sectional shape of a silicon oxide film formed on an uneven surface.

【符号の説明】[Explanation of symbols]

10…シリコン基板 12…下部電極層 14…高誘電体膜 16…絶縁膜 16a…酸化膜 16b…窒化膜 20…シリコン基板 22…フィールド酸化膜 24…ゲート酸化膜 26…ゲート電極 28、30…不純物領域 32…BPSG膜 34…多結晶シリコン電極層 36…高誘電体膜 38…シリコン酸化膜 40…上部電極層 42…層間絶縁膜 44…ビットライン 10...Silicon substrate 12...Lower electrode layer 14...High dielectric film 16...Insulating film 16a...Oxide film 16b...Nitride film 20...Silicon substrate 22...Field oxide film 24...Gate oxide film 26...Gate electrode 28, 30... impurity region 32...BPSG film 34...Polycrystalline silicon electrode layer 36...High dielectric film 38...Silicon oxide film 40... Upper electrode layer 42...Interlayer insulation film 44...Bit line

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】  表面が凹凸である第1電極層と、前記
第1電極層上に形成された絶縁膜と、前記絶縁幕上に形
成された誘電率の高い高誘電体膜と、前記高誘電体膜上
に形成された第2電極層とを有することを特徴とする半
導体装置。
1. A first electrode layer having an uneven surface; an insulating film formed on the first electrode layer; a high dielectric constant film having a high dielectric constant formed on the insulating screen; A semiconductor device comprising a second electrode layer formed on a dielectric film.
【請求項2】  請求項1記載の半導体装置において、
前記高誘電体膜の膜厚が前記絶縁膜の膜厚よりも厚いこ
とを特徴とする半導体装置。
2. The semiconductor device according to claim 1,
A semiconductor device characterized in that the thickness of the high dielectric constant film is thicker than the thickness of the insulating film.
【請求項3】  請求項1又は2記載の半導体装置にお
いて、前記第1電極層がシリコンを含んでおり、前記絶
縁膜がシリコン酸化膜又はシリコン窒化膜であり、前記
高誘電体膜が3A族、4A族又は5A族の元素の酸化物
からなることを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the first electrode layer contains silicon, the insulating film is a silicon oxide film or a silicon nitride film, and the high dielectric constant film is a group 3A film. , 4A group, or 5A group element oxide.
【請求項4】  表面が凹凸の第1電極層を形成する工
程と、前記第1電極層上に誘電率の高い高誘電体膜を形
成する工程と、酸化雰囲気中又は窒化雰囲気中で熱処理
して、前記高誘電体膜と前記第1電極層との界面近傍を
酸化又は窒化して絶縁体膜を形成する工程とを有するこ
とを特徴とする半導体装置の製造方法。
4. A step of forming a first electrode layer having an uneven surface, a step of forming a high dielectric constant film having a high dielectric constant on the first electrode layer, and a heat treatment in an oxidizing atmosphere or a nitriding atmosphere. A method of manufacturing a semiconductor device, comprising the step of oxidizing or nitriding the vicinity of the interface between the high dielectric constant film and the first electrode layer to form an insulating film.
【請求項5】  請求項4記載の半導体装置の製造方法
において、前記絶縁膜の膜厚が前記高誘電体膜の膜厚よ
りも薄くなるように熱処理することを特徴とする半導体
装置。
5. The method of manufacturing a semiconductor device according to claim 4, wherein the heat treatment is performed so that the thickness of the insulating film becomes thinner than the thickness of the high dielectric constant film.
【請求項6】  請求項4又は5に記載の半導体装置の
製造方法において、前記第1電極層がシリコンを含んで
おり、熱処理により形成される前記絶縁膜がシリコン酸
化膜又はシリコン窒化膜であり、前記高誘電体膜が3A
族、4A族又は5A族の元素の酸化物からなることを特
徴とする半導体装置の製造方法。
6. The method of manufacturing a semiconductor device according to claim 4, wherein the first electrode layer contains silicon, and the insulating film formed by heat treatment is a silicon oxide film or a silicon nitride film. , the high dielectric constant film is 3A
1. A method for manufacturing a semiconductor device, comprising an oxide of an element of Group 4A or Group 5A.
JP3051419A 1991-03-15 1991-03-15 Semiconductor device and manufacture thereof Withdrawn JPH04286356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3051419A JPH04286356A (en) 1991-03-15 1991-03-15 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3051419A JPH04286356A (en) 1991-03-15 1991-03-15 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04286356A true JPH04286356A (en) 1992-10-12

Family

ID=12886408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3051419A Withdrawn JPH04286356A (en) 1991-03-15 1991-03-15 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04286356A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268156A (en) * 1993-03-17 1994-09-22 Nec Corp Thin-film capacitor and its manufacture
JP2006060230A (en) * 2004-08-20 2006-03-02 Samsung Electronics Co Ltd Three-dimensional semiconductor capacitor and manufacturing method thereof
JP2007194652A (en) * 2001-06-21 2007-08-02 Matsushita Electric Ind Co Ltd Semiconductor device
WO2019239804A1 (en) * 2018-06-15 2019-12-19 株式会社村田製作所 Capacitor and method for producing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268156A (en) * 1993-03-17 1994-09-22 Nec Corp Thin-film capacitor and its manufacture
JP2007194652A (en) * 2001-06-21 2007-08-02 Matsushita Electric Ind Co Ltd Semiconductor device
JP2006060230A (en) * 2004-08-20 2006-03-02 Samsung Electronics Co Ltd Three-dimensional semiconductor capacitor and manufacturing method thereof
WO2019239804A1 (en) * 2018-06-15 2019-12-19 株式会社村田製作所 Capacitor and method for producing same
JPWO2019239804A1 (en) * 2018-06-15 2021-01-14 株式会社村田製作所 Capacitors and their manufacturing methods
US11476056B2 (en) 2018-06-15 2022-10-18 Murata Manufacturing Co., Ltd. Capacitor and method for manufacturing the same

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