JPH04282474A - Clock level determinator - Google Patents

Abstract

PURPOSE:To obtain a device which can determine an output clock on the basis of the presence or absence of edges of the output clock. CONSTITUTION:A data input fixed at an 'H' level is latched at the timing of an output clock by an output clock leading edge detecting circuit 14 and an output clock trailing edge detecting circuit 15. Outputs A and E being the latched results and determination signals I and II are subjected to prescribed logic operations by logic circuits 16, 18 and 20 and 17, 19 and 21, and thereby the output clock can be determined by executing a measuring waveform only once.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a device for determining the level of a clock of a semiconductor integrated circuit (hereinafter referred to as an IC), and particularly to a device installed in a device for measuring the repetition frequency of an IC. It is.

0002

2. Description of the Related Art FIG. 4 shows a conventional device of this kind. Here, the block configuration of the conventional device is shown, taking as an example an output level judgment circuit installed in a general tester for testing ICs. There is. In the figure, 1 is an output "H" level determination circuit composed of D flip-flops, 2 is an output "L" level determination circuit also composed of D flip-flops, and 3 is an "H" level output circuit composed of a NAND circuit. 4 is an "L" level side matching circuit composed of an AND circuit, 5 is an error judgment circuit composed of an AND circuit, 6 is an output clock of the IC, 7a is a judgment signal for "H" level, 7b is a determination signal for "L" level, 8 is an "H" expected value, 9 is an "L" expected value, and 10 is an error signal.

Next, an example of the operation in repetitive frequency measurement will be explained. First, FIG. 3 shows a measured waveform diagram of the repetition frequency. In the period of the reference clock Tφ11, the input clock waveform 12 is applied to the IC at a certain repetition frequency. Next, when a waveform serving as the trigger input 13 is applied to the IC, after a certain delay time has elapsed with respect to the trigger input waveform 13, the waveform of the output clock 6 is output at approximately the same frequency as the input clock 12. The IC tester measures the frequency of this output and can determine whether the IC is good or bad depending on whether the frequency is as expected.

If there is some kind of defect inside the IC, the output will be the input clock 12 as shown in FIG.
The clock corresponding to this will not be output. In such a case, it is meaningless to measure the frequency of the IC output, so by determining the voltage level of the output clock, it is possible to detect whether such an error has occurred, and if an error is detected, the IC The tester is programmed to interrupt frequency measurement.

In a general tester for testing an IC, a circuit as shown in FIG. 4 constitutes a circuit for determining the voltage level of the output clock as described above. 4, the output clock 6 of FIG. 3 is input to the "H" level determination circuit 1 and the "L" level determination circuit 2 of FIG. Next, determination signals 7a and 7b for determining the output clock 6
Therefore, both determination circuits 1 and 2 latch the output clock 6 only for a certain period of the period of the reference clock Tφ11. Next, the output result of the "H" level determination circuit 1 becomes the input to the "H" level side matching circuit 3, and the NA with the "H" expected value 8 is
The ND product is taken. Similarly, the output result of the “L” level determination circuit 2 becomes the input to the “L” level side matching circuit 4, and “
The AND product with the "L" expected value 9 is taken. Next, the output results of the "H" level side matching circuit 3 and the "L" level side matching circuit 4 are input to the error determination circuit 5, and the AND product is calculated. An error signal 10 is obtained.

Next, to explain the operation in more detail, the "H" level determination circuit 1 and the "L" level determination circuit 2 are both composed of D flip-flops.
The output clock of the IC is supplied to the data input, and this is latched at the timing of the determination signals 7a and 7b supplied to the trigger input. The judgment signals 7a and 7b are first
a and 1b (same waveform) are supplied to determination circuits 1 and 2. When the determination signals 1a and 1b are supplied, their timings do not match with the "H" level of the output clock 6, so the outputs Q of both level determination circuits 1 and 2 both remain at "L". The output of the “H” level side coincidence circuit 3 is the judgment circuit 1
NAND the output “L” and “H” expected value to “H”
The output of the "L" level side matching circuit 4 is the judgment circuit 2.
The output “L” is ANDed with the “L” expected value to become “L”
become. Therefore, the error judgment circuit 5 has both coincidence circuits 3 and 4.
It becomes "H" by ANDing the outputs of. Since the error determination circuit 5 continues this state for any clock of the determination signals 1a, 1b, the IC tester can detect that the determination signals 1a, 1b are deviated from the output clock 6. Next, the IC tester continues to judge the output level by providing new judgment signals 2a and 2b in place of 1a and 1b. At this time, the timing of the judgment signals 2a and 2b coincides with the output clock 6, so "L" is output as an error signal in the part where there is an output clock, and "H" is output as an error signal in the part where there is no output clock. Output. Thereafter, the output level is determined by sequentially supplying the phase-delayed determination signals in the same manner, and finally the determination of the output level is completed using the determination signals na and nb.

[0007]

[Problem to be Solved by the Invention] The output level determination circuit in a conventional general tester for testing ICs is configured as described above, so that the output level determination circuit for the trigger input 13 is not output after a certain delay time has elapsed. In the output clock 6, if the delay time is unstable depending on the IC, the judgment signal 7a
, 7b several times to several dozen times as 1a~na, 1b~nb, 1n
It is necessary to repeat the measurement pattern of the repetition frequency many times while changing it by about s, and depending on the variation in delay time, the determination signal setting may have to be reset many times. There were problems in that the length would be enormous and the measurement time would also be enormous.

[0008] This invention was made in order to solve the above-mentioned problems, and it is possible to judge the clock level by inputting the measured waveform only once, and furthermore, it is possible to judge the clock level by inputting the measured waveform with a long vector length. It is an object of the present invention to provide a clock level determination device capable of measuring repetition frequency without having to do so.

[0009]

[Means for Solving the Problems] A clock level determining device according to the present invention uses the waveform of a clock of a device under test whose repetition frequency is measured as a clock input to an output edge determining circuit, and has a clock level determining device fixed to the output edge determining circuit. The latched input data is latched, and a logic circuit is constructed for this latched result with a determination signal, so that the repetition frequency can be measured by executing the measurement waveform once.

0010

[Operation] In the clock level determining device according to the present invention, the presence or absence of an edge of the output clock of the IC is detected by using the output edge determining circuit provided in the repetition frequency measuring device, and the clock level is determined based on this. Therefore, measurement can be performed by setting the determination signal for determining the repetition frequency only once.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an output edge determination circuit of a frequency measuring circuit according to an embodiment of the present invention. In the figure, 14 is an output clock rising edge detection circuit composed of a D flip-flop, and 15 is a D flip-flop as well. Output clock falling edge detection circuit consisting of
6 is the output clock, 11 is the reference clock Tφ, 7a, 7
b is a determination signal I and a determination signal II, both of which have the same waveform. 16 is a rising edge side determination circuit that takes the AND product of the output Q of the output clock rising edge detection circuit 14 and the determination signal I7a, and 17 is the AND product of the output Q of the output clock falling edge detection circuit 15 and the determination signal II7b. 18 is an inversion circuit that inverts the output of the rising edge side judgment circuit 16; 19 is an inversion circuit that inverts the output of the falling edge side judgment circuit 17; 7c is an inverted waveform of the judgment signal I; 7d is the inverted waveform of judgment signal II, 1
0 is an error signal, 20 is an exclusive OR of the output of the inverting circuit 18 and the inverted waveform 7c of the judgment signal I, and an error signal 1 is obtained.
A circuit 21 that outputs 0 is a circuit that takes the exclusive OR of the output of the inversion circuit 19 and the inverted waveform 7d of the determination signal II, and outputs an error signal 10.

FIG. 2(a) is a diagram showing waveforms in the block on the output clock rising edge detection circuit 14 side. In the figure, 11 is the reference clock Tφ waveform, 6 is the output clock waveform, and A is the output clock rising edge. The output waveform of the edge detection circuit 14, 7a is the waveform of the judgment signal I, B is the output waveform after ANDing the output A and the judgment signal I7a, C is the inverted waveform of the output B, and 7c is the inversion of the judgment signal I. The waveform D is the error signal waveform obtained by performing exclusive OR of the output C and the inverted waveform 7c of the determination signal I.

FIG. 2(b) is a diagram showing waveforms in the block on the output clock falling edge detection circuit 15 side. In the figure, E indicates the output waveform of the output clock falling edge detection circuit 15, and 7b indicates The waveform of the judgment signal II,
F is the output waveform after ANDing the output E and the judgment signal II7b, G is the inverted waveform of the output F, and 7d is the judgment signal II
H is the inverted waveform 7d of output G and judgment signal II.
This is the error signal waveform after performing exclusive OR.

Next, the operation will be explained. First, Figure 3
shows the measurement waveform diagram of the repetition frequency. Reference clock T
In a period of φ11, the input clock waveform 12 is applied to the IC at a certain repetition frequency. Next, when a waveform serving as the trigger input 13 is applied to the IC, after a certain delay time has elapsed with respect to the trigger input waveform 13, the output clock waveform 6 is output at approximately the same frequency as the input clock 12.

Next, in a general tester for testing this IC, an output edge determination circuit shown in FIG. 1 is constructed. The output clock rising edge detection circuit 14 in FIG. 1 pulls up the data input to the "H" level and latches the data at the rising edge of the output clock waveform 6. The latched output A is reset every cycle by the reference clock Tφ11. The output level of the output A of the output edge determination circuit waveform shown in FIG. 2A remains at "L" at the third bit where the output clock waveform 6 has no edge. Next, the output A of the output clock rising edge detection circuit 14 is ANDed with the determination signal I7a by the rising edge side determination circuit 16, and the determination result has the waveform shown in the output B of FIG. 2(a). Next, an inverting circuit 18 that inverts the output of the rising edge side determination circuit 16 inverts the output B to obtain the waveform of the output C shown in FIG. 2(a). The waveform of the output C is exclusive ORed with the inverted waveform 7c of the determination signal I in the exclusive OR circuit 20, and the error signal D shown in FIG. 2(a) is obtained. That is, an error signal 10 is obtained for a bit in which the output clock waveform 6 does not have a rising edge.

Further, the output clock falling edge detection circuit 15 in FIG. 1 pulls up the data input to the "H" level and latches the data at the falling edge of the output clock waveform 6. The latched output E is the reference clock T
It is reset every cycle at φ11. The output level of the output E of the output edge determination circuit waveform shown in FIG. 2(b) remains at "L" at the third bit where the output clock waveform 6 has no edge. Next, the output E of the output clock falling edge detection circuit 15
is ANDed with the determination signal II7b by the falling edge side determination circuit 17, and the determination result has the waveform shown in output F in FIG. 2(b). Next, an inverting circuit 19 that inverts the output of the falling edge side determination circuit 17 inverts the output F to obtain the waveform of the output G shown in FIG. 2(b). The waveform of the output G is the inverted waveform 7 of the judgment signal II in the exclusive OR circuit 21.
An exclusive OR is performed with d to obtain the error signal H shown in FIG. 2(b). That is, an error signal 10 is obtained for a bit in which the output clock waveform 6 does not have a falling edge.

As described above, in the above embodiment, the waveform of the output clock of the IC whose repetition frequency is measured is used as the clock input of the output clock rising edge detection circuit 14 and the output clock falling edge detection circuit 15, and the respective data inputs are Input data whose level is fixed to "H" and latch it, and perform a predetermined logical operation on this latched result with judgment signals I and II to determine the level of the output clock. Since the determination is made, the level of the output clock can be determined in one waveform measurement, and in turn, the repetition frequency can be measured in one measurement.

In the above embodiment, two circuits, the output clock rising edge detection circuit 14 and the output clock falling edge detection circuit 15, are provided, but only the output clock rising edge detection circuit 14 is used for output. The clock 6 may be inverted or non-inverted, and the same effects as in the above embodiment can be obtained.

FIG. 5 is a diagram showing an edge detection circuit according to another embodiment of the present invention configured as described above, and as shown in the figure, the edge discrimination signal 22 is at "H" level and "L"
By providing the output clock inverting circuit 23 and the output clock non-inverting circuit 24, which are respectively active when the output clock 6 is inverted, the level of the edge discrimination signal 22 is set to "H" level when the output clock 6 is inverted, and when the output clock 6 is not inverted. By setting each to the "L" level, the same effects as in the above embodiment can be achieved.

[0020]

As described above, according to the clock level determination device according to the present invention, the waveform of the clock of the IC under test whose repetition frequency is measured is used as the clock input, and the level can be determined based on this clock input. In addition to latching fixed input data, a logic circuit with a judgment signal is configured for this latched result, so that the clock level of the output clock can be judged by executing the measurement waveform once. Therefore, it is possible to perform the measurement by setting the determination signal only once when measuring the repetition frequency, and even if the measurement pattern vector of the repetition frequency becomes enormous, the measurement can be carried out in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an output edge determination circuit according to an embodiment of the present invention.

FIG. 2 is an output edge determination circuit waveform diagram showing the waveform diagram in FIG. 1;

FIG. 3 is a measurement waveform diagram showing an example of measuring repetition frequency.

FIG. 4 is a block diagram showing a conventional output level determination circuit.

FIG. 5 is a diagram showing an edge detection circuit showing another embodiment of the invention.

[Explanation of symbols]

6 Output clock 7a Judgment signal I 7b Judgment signal II 7c Inverted waveform of judgment signal I 7d
Inverted waveform 10 of judgment signal II
Error signal 11 Reference clock Tφ12
Input clock 13 Trigger input 14 Output clock rising edge detection circuit 15 Output clock falling edge detection circuit 16 Rising edge side determination circuit 17
Falling edge side determination circuit 18, 19
Inverting circuits 20, 21 Exclusive OR circuit 22 Edge discrimination signal

Claims (1)

[Claims] 1. A means for detecting an edge of a clock waveform by receiving a predetermined level as data input and holding the data input using a clock waveform of a semiconductor integrated circuit as a trigger, and a means for detecting an edge of the clock waveform, and , means for determining the level of the clock waveform by determining the presence or absence of an edge by performing a predetermined logical operation with the determination signal.