JPH04280682A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a integrated circuit to be enhanced in drive capacity and operation speed without shortening channel length. CONSTITUTION:A first thin semiconductor film 14 whose inhibited bandwidth is wider than that of a substrate 1 is formed on the substrate 1, a second thin semiconductor film 17 whose inhibited bandwidth is narrower than that of the first thin semiconductor film 14 is provided onto the first thin semiconductor 14, and the junction surfaces of a source region and a drain region are located inside the first thin semiconductor film 14 or at a hetero-interface between the first thin semicondctor film 14 and the second thin semiconductor film 17.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-small semiconductor device and a method of manufacturing the same, and more particularly to a MIS field effect transistor and a method of manufacturing the same.

0003

2. Description of the Related Art In general, higher integration and higher performance of this type of MIS integrated circuit are achieved by miniaturizing the elements. In particular, shortening the channel length reduces the device area and improves the current driving ability of the device, which is extremely important for improving the operating speed.

However, when the channel length is shortened, a so-called short channel effect occurs, and in order to prevent such short channel effect, it is necessary to increase the substrate impurity concentration.

[0005]

However, in the conventional MIS integrated circuit described above, the channel length is 0.1μ.
When shortened to around m, the required substrate concentration becomes 1018
cm-3 or more, the source
The width of the depletion layer of the pn junction between the drain and the substrate becomes narrower, and the junction leakage current increases due to the tunnel current caused by the Zener breakdown mechanism. In addition, an increase in the substrate concentration increases the threshold voltage and reduces the logic amplitude, resulting in a reduction in the driving power of the transistor, resulting in a reduction in the operating speed of the circuit.

[0006] In view of the above-mentioned problems, the object of the present invention is to
The present invention provides a semiconductor device and a method for manufacturing the same, which can improve the driving force and operating speed of an integrated circuit regardless of the shortening of the channel length.

[Configuration of the invention]

[0008]

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a method in which a first semiconductor thin film made of gallium arsenide having a wider band gap than the substrate is formed on a substrate, and the first semiconductor thin film A second semiconductor thin film made of germanium, a superlattice of silicon and germanium, or a silicon germanium alloy having a narrower bandgap than the first semiconductor thin film is formed thereon, and a gate insulating film is formed on the second semiconductor thin film. , gate electrodes are sequentially stacked, and
A source region and a drain region are formed on both sides of the gate electrode, and a junction surface of the source region and a junction surface of the drain region are formed in the first semiconductor thin film or in the first semiconductor thin film.
A semiconductor device located at a hetero interface between a semiconductor thin film and a second semiconductor thin film, and a method for manufacturing such a device includes:
After forming an element isolation insulating film on the non-active region of the substrate to perform element isolation, a first semiconductor thin film having a band gap wider than that of the substrate is formed on the active region of the substrate; A second semiconductor thin film having a narrow forbidden band width is sequentially epitaxially grown, a gate insulating film and a gate electrode are sequentially formed on a predetermined region of the second semiconductor thin film, and a gate insulating film and a gate electrode are formed on both sides of the gate electrode. ion implantation or solid phase diffusion of impurities into the source/drain region, the junction surface of which is present in the first semiconductor thin film or at the heterointerface between the first semiconductor thin film and the second semiconductor thin film. It is something.

[0009]

[Operation] In the present invention, the junction surface of the source region and the junction surface of the drain region are in the first semiconductor thin film or in the first semiconductor thin film.
Since it is located at the hetero-interface between the semiconductor thin film and the second semiconductor thin film, which has a narrower forbidden band width than the first semiconductor thin film, the second semiconductor thin film, which has a smaller effective mass and a higher mobility, becomes a channel layer. Current driving power is increased without shortening the channel length.

Furthermore, the second semiconductor thin film has a larger energy interval between the bottom of the conduction band and the vacuum level than the first semiconductor thin film or the substrate semiconductor, and a smaller energy interval between the top of the valence band and the vacuum level. Therefore, the flat band voltage of the second semiconductor thin film shifts by the difference in energy interval from that of the first semiconductor thin film or the substrate semiconductor, and the absolute value of the threshold voltage decreases, resulting in a large logic amplitude and current driving power. increases.

Furthermore, since the pn junction of the source/drain region is formed in the first semiconductor thin film having a wide forbidden band width,
The width of the depletion layer of the pn junction becomes wider, and the tunnel leakage current due to Zener breakdown does not increase.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device and method of manufacturing the same according to the present invention will be described below with reference to FIGS. 1 to 10.

FIGS. 1 and 2 show cross-sectional views of an n-channel MISFET with two heterojunction interfaces.

That is, in the drawings, reference numeral 1 denotes a p-type silicon substrate (hereinafter referred to as substrate), and an element isolation oxide film 2 for element isolation is formed on a non-active region of this substrate 1. On the element region of the substrate 1, a p-type gallium arsenide thin film 14 and a p-type germanium thin film (or a superlattice film of silicon and germanium or a silicon-germanium alloy film may be used) 17 which are lattice-matched to the substrate 1 are sequentially laminated. A gate electrode 4 of an n-channel MISFET is formed on a predetermined region of this germanium thin film 17 with a gate insulating film 9 interposed therebetween. Further, on both sides of the gate electrode 4, a high concentration n-type gallium arsenide layer 15 constituting a source region and a high concentration n-type germanium layer 18 are sequentially laminated in a self-aligned manner, and a high concentration n-type gallium arsenide layer 18 constituting a drain region is laminated in sequence. An arsenic layer 16 and a high concentration n-type germanium layer 19 are sequentially laminated. The junction surface of the source region and the junction surface of the drain region are located in the gallium arsenide thin film 14 (see FIG. 1) or at the heterointerface between the gallium arsenide thin film 14 and the germanium thin film 17 (see FIG. 2). Further, the substrate 1 on which the MISFET is formed is covered with an insulating film 10, and this insulating film 10 has openings above the source region, gate electrode 4, and drain region, and a source metal electrode is formed on each opening. 11, a gate metal electrode 12 and a drain metal electrode 13 are formed, respectively.

Therefore, in this embodiment, the germanium thin film 17, which has a small effective mass and a high mobility, serves as a channel layer, so that the current driving force is increased. Furthermore, since the pn junction plane of the source/drain region is formed in the gallium arsenide thin film 14 having a wide forbidden band width, the depletion layer width of the pn junction becomes wide, and the tunnel leakage current due to Zener breakdown is reduced.

Furthermore, since the channel layer has a narrow forbidden band width,
Intrinsic carrier concentration increases. The amount of band bending required to form the inversion layer is (2kB T/q)In(N
SUB /ni ) (kB is the Boltzmann constant, T is the temperature, NSUB is the impurity concentration in the depletion layer, and ni is the intrinsic carrier concentration), so the higher the intrinsic carrier concentration, the smaller the bending of this band becomes, and the threshold value decreases. Furthermore, the germanium thin film 17 has a larger energy interval between the bottom of the conduction band and the vacuum level than the gallium arsenide thin film 14, and a smaller energy interval between the top of the valence band and the vacuum level, so that it can be used in n-channel MISFETs and p-channel MISFETs. In either case, the gallium arsenide thin film 1
The flat band voltage is shifted by the difference in energy interval from 4, and the threshold value is lowered. Therefore, the logic amplitude of the MISFET can be increased, and the current driving power can be increased.

Next, a method for manufacturing a semiconductor device having such a structure will be described with reference to FIGS. 1 to 8.

First, as shown in FIG. 3, an element isolation insulating film 2 is formed on a non-active region of a substrate 1 to perform element isolation.

Thereafter, as shown in FIG. 4, a gallium arsenide thin film 14 of several thousand angstroms is selectively deposited in the transistor region by vapor phase epitaxial growth using trimethyl gallium and arsine as raw material gases, and then p-type germanium is deposited on this film. A thin film 17 of 50 to 1000 angstroms is laminated. At this time, the raw material gas is SiH
4 (monosilane) and GeH4 (germane),
B2 H6 (diborane) for p-type doping
Use gas.

Subsequently, as shown in FIG. 5, a silicon oxide film is deposited on the substrate 1 using a CVD (vapor phase deposition) method.
A gate insulating film 9 is formed by depositing 0 angstroms.

Next, as shown in FIG. 6, after depositing polysilicon on the gate insulating film 9 by the CVD method,
This is patterned to form the gate electrode 4.

Thereafter, as shown in FIG. 7, the gate electrode 4
Using as a mask, apply a dose of 5×1015 to the entire surface of the substrate 1.
After implanting arsenic ions with an implantation energy of approximately 30 keV at approximately cm-2 and implanting silicon ions, activation annealing is performed at 1000° C. for approximately 30 seconds using a rapid lamp heating method to inject a high concentration into the germanium thin film 17. High concentration n-type gallium arsenide layers 15 and 16 are formed within the concentration n-type germanium layers 18 and 19 and the gallium arsenide thin film 14 . Alternatively, only arsenic ion implantation is performed. At this time, arsenic is a germanium thin film 17 which is a group IV semiconductor.
Since it becomes an n-type dopant in the gallium arsenide thin film 14, which is a III-V group semiconductor, it does not become a dopant in the gallium arsenide thin film 14, which is a III-V group semiconductor. This corresponds to the hetero interface between the arsenic layer 16 and the germanium layer 19 (see FIG. 2). In this way, since the junction depth of the source/drain region is defined by the film thickness of the germanium layers 18 and 19, the junction depth can be easily controlled. Therefore, fine channel MISFE requires shallow junction formation.
It is advantageous for manufacturing T.

Thereafter, as shown in FIG. 8, a silicon oxide film is deposited on the entire surface of the substrate 1 by the CVD method to form an interlayer insulating film 10. Then, the interlayer insulating film 10 is patterned, and the germanium layers 18 and 19 and the gate electrode 4 are patterned.
A contact hole 10a is opened at the top.

Furthermore, as shown in FIG. 1, a thin metal film of aluminum or the like is deposited on the substrate 1 containing the above-mentioned components by sputtering, and then patterned to form a source metal electrode 11 on each contact hole 10a. , a gate metal electrode 12 and a drain metal electrode 13 are formed, respectively. In this way, the MISFET is completed.

FIG. 9 shows a cross-sectional view of an n-channel MISFET with one heterojunction interface.

In the figure, an element isolation oxide film 2 is formed on a non-active region of a substrate 1. A p-type silicon germanium alloy (Six Ge1-x) thin film 3 lattice-matched to the substrate 1 is formed on the element region of the substrate 1, and a predetermined region of the p-type silicon germanium alloy thin film 3 is , n-channel MIS via gate insulating film 9
A gate electrode 4 of the FET is formed. On both sides of this gate electrode 4, a high concentration n-type silicon region 5 constituting a source region and a high concentration n-type silicon germanium alloy layer 7 are sequentially laminated in a self-aligned manner, and a high concentration n-type silicon region constituting a drain region. 6. High concentration n-type silicon germanium alloy layers 8 are sequentially laminated. Furthermore, MISF
An interlayer insulating film 10 is provided over the substrate 1 on which the ET is formed. The interlayer insulating film 10 has openings above the source region 7, gate electrode 4, and drain region 8, respectively, and a source metal electrode 11 and a gate metal electrode 12 on each opening.
and a drain metal electrode 13 are formed.

FIG. 10 shows p with one heterojunction interface.
A band diagram when forming an inversion layer of a channel MISFET is shown. According to this, the energy difference at the top of the valence electron between silicon and silicon germanium alloy or germanium is larger than the energy difference at the bottom of the conduction band. In other words, Si
p channel M using 0.5 Ge0.5 in the channel
ISFET has a contribution of only 0.3 due to energy difference.
There is a threshold voltage drop of 7V, and high driving force can be expected. This means that the p-channel MISFET
SFETs are advantageous.

The present invention is not limited to n-channel MISFETs, but can also be applied to p-channel MISFETs by changing the conductivity type of each semiconductor region. Additionally, by adding sidewall insulating films, etc., LDD (Lightly Doped)
ed Drain) structure. Furthermore, the heterojunctions are Si/Si1-x Gex, Si/G
Not limited to aAs/Ge, for example, GaAs/Si1-
x Gex, GaP/Si1-x Gex, Si/
SiC/Si, Si/GaP/Si1-x Gex,
Si/GaAs/Si1-x Gex, Si/Al1
-x Gax As/Si1-y Gey, Si/G
aAs/Ga1-x InAs, Si/ZnS1-x
Sex /Si1-y Gey (both 0≦x≦1
, 0≦y≦1).

[0029]

[Effects of the Invention] As explained above, according to the present invention, the second semiconductor thin film, which has a small effective mass and a high mobility, becomes the channel layer, so the current driving force is increased without shortening the channel length. do. Furthermore, the second semiconductor thin film has a larger energy interval between the bottom of the conduction band and the vacuum level and a smaller energy interval between the top of the valence band and the vacuum level than the first semiconductor thin film. The flat band voltage of the thin film shifts by the difference in energy interval from the first semiconductor thin film or the substrate semiconductor, and the absolute value of the threshold voltage decreases. Further, since the pn junction of the source/drain region is formed in the first semiconductor thin film having a wide forbidden band width, the depletion layer width of the pn junction becomes wide, and tunnel leakage current due to Zener breakdown is reduced. As a result, in a MISFET with a fine channel length, the drain current driving force can be increased and the operating speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an n-channel MISFET with two heterojunction interfaces of the present invention.

FIG. 2: Another n with two heterojunction interfaces of the present invention.
FIG. 3 is a cross-sectional view of a channel MISFET.

FIG. 3: N-channel MI with two heterojunction interfaces
It is a sectional view of the manufacturing process of SFET.

FIG. 4: N-channel MI with two heterojunction interfaces
It is a sectional view of the manufacturing process of SFET.

FIG. 5: N-channel MI with two heterojunction interfaces
It is a sectional view of the manufacturing process of SFET.

FIG. 6: N-channel MI with two heterojunction interfaces
It is a sectional view of the manufacturing process of SFET.

FIG. 7: N-channel MI with two heterojunction interfaces
It is a sectional view of the manufacturing process of SFET.

FIG. 8: N-channel MI with two heterojunction interfaces
It is a sectional view of the manufacturing process of SFET.

FIG. 9 is a cross-sectional view of an n-channel MISFET with one heterojunction interface of the present invention.

FIG. 10 is a band diagram when forming an inversion layer of a p-channel MISFET having one heterojunction interface according to the present invention.

[Explanation of symbols]

1 p-type silicon substrate 2 element isolation oxide film 4 gate electrode 9 gate insulating film 10 interlayer insulating film 11 metal source electrode 12 metal gate electrode 13 metal drain electrode 14 p-type gallium arsenide thin film 15, 16 high concentration n-type gallium arsenide layer 17 p-type germanium thin film

Claims (3)

[Claims] 1. A first semiconductor thin film having a wider forbidden band width than the substrate is formed on a substrate, and a second semiconductor thin film having a narrower forbidden band width than the first semiconductor thin film is formed on the first semiconductor thin film. A thin film is formed, and a gate insulating film and a gate electrode are sequentially laminated on the second semiconductor thin film, and a source region and a drain region are formed on both sides of the gate electrode, and the junction surface of the source region and the drain region are formed on both sides of the gate electrode. A semiconductor device characterized in that a bonding surface of the region is located in the first semiconductor thin film or at a heterointerface between the first semiconductor thin film and the second semiconductor thin film. 2. The semiconductor device according to claim 1, wherein the first semiconductor thin film is made of gallium arsenide, and the second semiconductor thin film is made of germanium, a superlattice of silicon and germanium, or a silicon-germanium alloy. 3. After forming an element isolation insulating film on a non-active region of a substrate to perform element isolation, a first semiconductor thin film having a wider forbidden band width than that of the substrate is formed on an active region of the substrate, and a first semiconductor thin film having a band gap wider than that of the substrate; A second semiconductor thin film having a narrower forbidden band width than the first semiconductor thin film is sequentially epitaxially grown, a gate insulating film and a gate electrode are sequentially formed on a predetermined region of the second semiconductor thin film, and the gate By ion-implanting or solid-phase diffusion of impurities on both sides of the source electrode, a junction surface is formed in the first semiconductor thin film or at the heterointerface between the first semiconductor thin film and the second semiconductor thin film. A method of manufacturing a semiconductor device, comprising forming a drain region.