JPH0427708B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor memory devices, and particularly to improvements in dynamic RAM. [Technical Background of the Invention] A conventional dynamic RAM has a two-layer electrode structure as shown in FIG. That is, 1 in the figure is p
The main surface of this substrate 1 has an island-shaped cell region 3 separated by a field oxide film 2.
is formed. A capacitor electrode 4 made of, for example, polycrystalline silicon is provided in a portion extending from the surface of the cell region 3 to the field oxide film 2 via a thin oxide film 5 formed on the same surface.
On the surface of the cell region 3 under this capacitor electrode 4,
An n ^- type diffusion layer 6 is provided. Further, an n ⁺ -type diffusion layer 7 is provided on the surface of the cell region 3 at a desired distance from the n ^- -type diffusion layer 6 . Furthermore, 8 in the figure is a transfer gate electrode made of, for example, polycrystalline silicon, and this gate electrode 8 is partially formed by the gate oxide formed between the n ^- type diffusion layer 6 and the n ⁺ type diffusion layer 7. The cell area 3 through the membrane 9
It is located on the surface, and the other end extends onto the capacitor electrode 4 via the oxide film 10. The entire surface including the transfer gate electrode 8 is covered with an interlayer insulating film 11. On this interlayer insulating film 11, an A wiring 12 connected to the capacitor electrode 4 through a contact hole, and an A wiring 13 as a word line connected to the transfer gate electrode 8 through a contact hole are provided. . [Problems in the Background Art] However, in the above-mentioned dynamic RAM, voltage is applied to the transfer gate electrode 8 from the A wiring 13, and the voltage n ^- under the capacitor electrode 4 is
In order to exchange charges between the type diffusion layer 6 and the n ⁺ type diffusion layer 7, a maze (surcharge) is provided in the A wiring 13.
There was a drawback that if high voltage (voltage) was applied, the gate would be destroyed. For this reason, an input protection circuit is provided on the A wiring (external terminal) side to prevent surge damage, but the addition of the input protection circuit causes a decrease in the degree of integration and an increase in additional costs. In addition, because conventional dynamic RAM has a two-layer electrode structure, the area of the cell area increases.
There were naturally limits to increasing density. Furthermore, conventional dynamic RAM has a two-layer electrode structure, and its surface is extremely uneven, making it difficult to process fine patterns. Moreover, a two-layer A wiring structure is required in which both the word line and the bit line are formed of A wiring. [Object of the Invention] The present invention provides a dynamic RAM that can prevent gate breakdown due to surge voltage without providing an input protection circuit, and that is highly integrated and easy to process fine patterns.
The present invention aims to provide a semiconductor memory device such as the following. [Summary of the Invention] The present invention provides a method of selectively providing a semiconductor region of a second conductivity type on the main surface of a semiconductor substrate of a first conductivity type, and providing an island-shaped cell region separated by an element isolation region in this semiconductor region. , a thin insulating film is provided on the surface of the cell region, and an electrode serving as at least a capacitor electrode and a transfer gate is provided on the insulating film,
and providing a first conductivity type impurity layer with a low concentration and a high concentration electrically isolated from each other on the surface of the cell region,
The potential of the semiconductor region is changed by a control means, and the semiconductor region is composed of the impurity layer, the insulating film, and the electrode.
The main idea is to obtain a semiconductor memory device having the above-mentioned characteristics by controlling switching of MOS transfer transistors. [Embodiments of the Invention] Hereinafter, an example in which the present invention is applied to a dynamic RAM will be described in detail with reference to FIGS. 2A to 2C. Reference numeral 21 in the figure is, for example, an n-type silicon substrate, and this base body 21 is selectively provided with two mutually adjacent p-well regions 22 and 22'.
One p-well region 22 has a column direction (X direction).
An element isolation region 23 made of buried SiO ₂ extending to
Embedded SiO ₂ extending in the row direction (Y direction) as a...
Element isolation regions 23b... consisting of element isolation regions 23a..., 23b... are provided.
... _, a plurality of island-shaped cell regions 24 ₁₁ , 24 12 , 24 ₁₃ , 24 ₂₁ , 24 ₂₂ , 2 in the p-well region 22
4 ₂₃ is formed. As shown in FIG. 2B, the element isolation regions 23a extending in the column direction are located above the bottom surface of the p-well region 22 (interface with the substrate 21) by a desired distance, and The element isolation regions 23b extending in the direction have their bottoms in contact with the bottom surface of the p-well region 22, as shown in FIG. That is, the cell regions 24 ₁₁ , 24 ₂₁ , 24 12 , 24 ₂₂ , _{24 13 ,} 24 extending in the row direction
Cell regions 24 ₁₁ , 24 12 , 24 ₁₃ , 24 ₂₁ , 24 ₂₂ , _{23 are} commonly connected and extend in the column direction.
24 ₂₃ are electrically isolated from each other by element isolation regions 23b... Further, on one end side of the p-well region 22, an element isolation region 23a...
..., 23b..., island-like regions 25 ₁ ,
25 ₂ and 25 ₃ are provided. These island regions 25 ₁ to _{25 3} are electrically isolated from _each other by element _isolation regions 23b _.
24 ₁₃ and 24 ₂₃ , respectively. Further, in the other p-well region 22', island regions 26 ₁ to 26 ₃ are formed which are electrically isolated from each other by the element isolation regions 23b extending in the row direction. Further, the cell areas 24 ₁₁ to 24 ₁₃ and 24 ₂₁ to
24 ₂₃ and island-like regions 25 ₁ to 25 ₃ , 26 ₁ to 26 ₂
A thin oxide film 27 is coated on the surface. N ⁺ type diffusion layers 28 are provided on the surfaces of each of the cell regions 24 ₁₁ to 24 ₁₃ and 24 ₂₁ to 24 ₂₃ , and both ends of these n ⁺ type diffusion layers 28 in the column direction are The element isolation region 23b extending in the row direction
It is in contact with... These n ⁺ type diffusion layers 28...
Each of the cell regions 24 ₁₁ is spaced a desired length from the cell region 24
~24 ₁₃ , 24 ₂₁ ~ 24 ₂₃ are provided with n ^- type diffusion layers 29 on most of their surfaces, and both ends of these n ^- type diffusion layers 29 in the column direction extend in the row direction. It is in contact with the element isolation regions 23b extending in the column direction, and one end in the row direction is in contact with the element isolation regions 23a extending in the column direction. Then, on the oxide film 27 of each of the cell regions 24 ₁₁ to 24 ₁₃ , 24 ₂₁ to 24 ₂₃ and the surrounding element isolation regions 23 a . . . , 23 b . An electrode 30 is provided. In other words, each cell area 2
In 4 ₁₁ to 24 ₁₃ and 24 ₂₁ to 24 ₂₃ , the portion of the electrode 30 above the n ^- type diffusion layer 29... functions as a capacitor electrode, and the n ^- type diffusion layer 29... and the n ⁺ type diffusion layer 28... A portion of the electrode 30 on the region in between (channel region) functions as a transfer gate electrode. Further, on the oxide film 27 between the island-like region 25 ₁ of the p-well region 22 and the island-like region 26 ₁ of the p-well region 22', a polycrystalline silicon film formed in the same process as the electrode 30 is formed. Gate electrode 31 ₁
is provided. Similarly, the island regions 25 ₂ and 25 ₃ of the p-well region 22 and the p-well region 2
Gate electrodes 31 ₂ and 31 ₃ are provided between the island-like regions 26 ₂ and 26 ₃ of 2', respectively. Furthermore, the electrode 30 and gate electrodes 31 ₁ to 3
An interlayer insulating film 32 made of SiO ₂ is provided on the entire surface including 1 ₃ .
is covered. Further, the n ⁺ type diffusion layer 28
A contact hole 33... is opened in the oxide film 27, electrode 30, and interlayer insulating film 32 corresponding to a part of..., and the contact hole 33...
An oxide layer 34 for insulating the later A wiring and the electrode 30 is formed between the side surface and the electrode 30 made of polycrystalline silicon. A contact hole 33 is formed on the interlayer insulating film 32...
A extending in the column direction and connected to each n ⁺ type diffusion layer 28 of the cell regions 24 ₁₁ to 24 ₁₃ via the
A wiring (bit line) ₃₅₁ is provided.
Further, a contact hole 33 is formed on the same insulating film 32.
A extending in the column direction and connected to each of the n ⁺ type diffusion layers 28 of the cell regions 24 ₂₁ to 24 ₂₃ through the
A wiring (bit line) ₃₅₂ is provided.
With this configuration, each memory area 24 ₁₁ to 24 _1
3 and 24 ₂₁ to 24 ₂₃ have memory cells 36 ₁₁ to 36 ₁₃ ,
36 ₂₁ to 36 ₂₃ are formed. Further, an equivalent circuit diagram of this memory cell is shown in FIG. That is, Tr ₁ in the figure is formed in each memory cell.
MOS transfer transistor, C is electrode 3
0, n ^-diffusion layer 29 and oxide film 27 between them
It is a capacitor formed by The gate of these transistors Tr ₁ and capacitor C are constant power supplies.
Connected to V _DD . Said transistor _Tr1 is connected to the bit line BL. Further, an external power supply V _CC is connected to the transistor Tr ₁ for applying a back gate bias. And there is p between transistor Tr ₁ and external power supply V _CC
- A MOS transistor Tr ₂ consisting of well regions 22, 22', an oxide film 27, and gate electrodes 31 ₁ , 31 ₂ , 31 ₃ is interposed, and the transistor Tr ₂
A word line WL is connected to the gate of the word line WL. Next, the operation of the memory cell of the above-mentioned dynamic RAM will be explained. First, a constant voltage of, for example, 1.5V is applied from the constant power source V _DD to the electrode 30, and a predetermined voltage is applied from the bit line _BL to the n ⁺ type diffusion layer 28 . ’ each island region 2
For example, when a voltage of -5V is applied to 6 ₁ to 26 ₃ and the gate electrode 31 ₁ of the MOS transistor Tr ₂ is turned on from the word line WL, the gate electrode 3
The island region 25 ₁ and cell regions 24 ₁₁ and 24 ₂₁ extending in the row direction of the p-well region ₂₂ corresponding to 1 1 are commonly connected to each other, and the other island regions 25 ₂ and 25 ₃ and cell region 24 ₁₂ , 24 ₁₃ , 24 ₂₂ , and 24 ₂₃ , the island-shaped region 2
5 ₁ only to the cell areas 24 ₁₂ and 24 ₂₁ -
A voltage of 5V is applied. In this way, cell area 2
When a voltage of -5V is applied to 4 ₁₂ and 24 ₂₁ , the same cell region 24
₁₂ , 24 ₂₁ Threshold voltage of the MOS transfer transistor constituted by the n ^- type diffusion layer 29, the n ⁺ type diffusion layer 28, the oxide film 27, and the electrode 30 portion between the diffusion layers 29 and 28 (V _Th ) increases, so the transistor is turned off. on the other hand,
Since the voltages in the other cell regions 24 ₁₂ , 24 ₁₃ , 24 ₂₂ , and 24 ₂₃ are 0V, the MOS transfer transistors in these cell regions are turned on. Next, writing, reading, etc. of the dynamic RAM will be explained. () Unselected Each island region 26 ₁ to 26 of the p-well region 22'
₃ is applied with -5V from the external power supply V _CC and a voltage of, for example, 1.5V is applied to the electrode 30 from the constant power supply V _DD , each MOS transistor Tr 2 having the gate electrodes 31 ₁ to 31 ₃ is turned on, and all MOS transistors Tr ₂ are turned on. Cell area 24 ₁₁ ~2
By applying a voltage of -5V to 4 ₁₃ , 24 ₂₁ to 24 ₂₃ , these memory cells 36 ₁₁ to 36 ₁₃ , 36 ₂₁ to 36 ₂₃
Turn off MOS transfer transistor Tr ₁ . () Writing Apply similar voltages to the p-well region 22' and electrode 30, select the bit line 35 ₁ (BL), and apply a predetermined voltage to the memory cells 36 ₁₁ , 36 ₁₂ , 36 ₁₃
is applied to each n ⁺ type diffusion layer 28..., the MOS transistor Tr ₂ having the gate electrode 31 ₁ is turned off via the word line WL, and the voltage of the cell regions 24 ₁₁ , 24 ₂₁ extending in the row direction is turned off. By setting it to 0V, the address of the memory cell ₃₆₁₁ is selected, its transistor _Tr1 is turned on, and charges are accumulated in the capacitor C. After this, the gate electrode 31
The transistor Tr ₂ having a value of ₁ is turned on, and the transistor Tr ₁ of the memory cell 36 ₁₁ is turned off. () Read Apply a similar voltage to the p-well region 22' and electrode 30, select the bit line 35 ₁ (BL), and apply a predetermined voltage to the memory cells 36 ₁₁ , 36 ₁₂ , 36 ₁₃
is applied to each n ⁺ type diffusion layer 28..., the MOS transistor Tr ₂ having the gate electrode 31 ₁ is turned off via the word line WL, and the voltage of the cell regions 24 ₁₁ and 24 ₂₁ is similarly set to OV. Then, the address of the memory cell ₃₆₁₁ is selected, the transistor _Tr1 is turned on, and the charge accumulated in the capacitor C is transferred to the n ⁺ type diffusion layer 28, and the bit line 3611 is selected.
5 ₁ (BL) outputs a high voltage “1” signal. Also, under similar conditions, a MOS transistor with a gate electrode 31 ₂ is connected via the word line WL.
Tr ₂ is turned off and the cell area 24 ₁₂ extending in the row direction is
By setting the voltage of 24 _{to 22} to OV, the address of memory cell 36 _{to 12} is selected and its transistor is
Tr ₁ turns on, but capacitor C of cell 36 ₁₂
Since no charge is stored in the bit line 35 ₁ (BL), a low voltage "0" signal is output. Therefore, switching control of the MOS transfer transistor can be performed by changing the voltage in the well region from the external voltage while fixing the voltage to the electrode that serves as the capacitor electrode and the transfer gate. Even if a surge voltage is applied to
Not only the capacitor of MOS transfer transistor, but also between the well region and the substrate, and between the well region and the substrate.
It is divided by the capacitors between the n ^- type diffusion layers and between the well region and the n ⁺ type diffusion layer, thereby preventing gate breakdown. As a result, since the input protection circuit can be omitted, a highly reliable and highly integrated dynamic RAM can be obtained. Furthermore, whereas the conventional structure has a two-layer structure consisting of a capacitor electrode and a transfer gate electrode, the present invention requires only one layer of electrode that also serves as the capacitor electrode and the transfer gate electrode.
Since only one layer of wiring is required, the surface has excellent flatness and microfabrication is possible. Moreover, for the same reason, disconnections in the A wiring can be significantly reduced, and reliability and yield can be improved. Furthermore, since the capacitor electrode and the transfer gate electrode can be shared, the area of the cell region can be greatly reduced, and the degree of integration can be dramatically improved. In the above embodiment, an oxide film having a uniform thickness was formed under the electrode serving as both the capacitor electrode and the transfer gate electrode, but the present invention is not limited thereto. For example, as shown in FIG. 4, a thin oxide film 37 is provided under a portion of the electrode 30 that becomes a capacitor region, and a thicker oxide film 37' is provided under a portion of the electrode 30 that becomes a transfer gate region. Good too. With such a configuration, the capacity of the storage capacitor can be further increased, and the reliability of the MOS transfer transistor can also be improved. In the above embodiment, the bit line connected to the n ⁺ -type diffusion layer was formed using the A wiring, but the wiring (bit line) made of the same material may be formed in the same step as forming the electrode made of polycrystalline silicon. With such a structure, the surface flatness can be further improved. In the above embodiment, the voltage supply to the p-well region is controlled using a transistor having a MOS structure, but the present invention is not limited thereto. For example, as shown in FIG. 5, n ⁺
A junction type MOS FET consisting of a type junction region 38 and a gate electrode 39 in contact with this region 38 is provided,
Due to the expansion of the depletion layer 40 due to this FET, p-
The voltage supply to the well region 22 may also be controlled. [Effects of the Invention] As detailed above, according to the present invention, gate destruction due to surge voltage can be prevented without providing an input protection circuit, and fine pattern processing is easy.
It is possible to provide a highly reliable, highly integrated semiconductor memory device such as a dynamic RAM that can prevent disconnection of wiring, etc., and further reduce the area of the cell region to a large extent.

[Brief explanation of drawings]

Figure 1 shows the dynamics of the conventional two-layer electrode structure.
2A is a plan view of a dynamic RAM memory cell showing an embodiment of the present invention; FIG. 2B is a sectional view taken along line BB in FIG. 2A; FIG. 3 is an equivalent circuit diagram of the memory cells shown in FIGS. 2A to 2C, and FIGS. 4 and 5 show other embodiments of the present invention, respectively. FIG. 2 is a cross-sectional view of a main part of a memory cell of the dynamic RAM shown in FIG. 21...n-type silicon substrate, 22, 22'...
P-well region, 23a, 23b...Buried element isolation region, ₂₄₁₁ to ₂₄₁₃ , ₂₄₂₁ to ₂₄₂₃ ...
Cell region, 25 ₁ to _{25 3} , 26 ₁ , 26 ₃ ... Island region, 27, 37, 37' ... Oxide film, 28 ...
n ⁺ type diffusion layer, 29... n ^- type diffusion layer, 30... electrode, 31 ₁ to 31 ₃ , 39... gate electrode, 35...
...A wiring (bit line), 36 ₁₁ to 36 ₁₃ ,
36 ₂₁ to 36 ₂₃ ... memory cell, 38 ... n ⁺ type junction region, Tr ₁ ... MOS transfer transistor, Tr ₂ ... MOS transistor, C ... capacitor, BL ... bit line, WL ... word line .

Claims (1)

[Claims] 1. A semiconductor region of a second conductivity type selectively provided on the main surface of a semiconductor substrate of a first conductivity type, an element isolation region provided in this semiconductor region, and an element isolation region provided in this element isolation region. a thin insulating film formed on the surface of the separated island-shaped cell region; an electrode serving as at least a capacitor electrode and a transfer gate provided on the thin insulating film; and an electrode provided on the surface of the cell region. a highly-concentrated impurity layer of a first conductivity type; a low-concentration impurity layer of a first conductivity type provided on most of the surface of the cell region spaced apart from the impurity layer by a desired length; 1. A semiconductor memory device comprising: control means for controlling switching of a MOS transfer transistor formed by each of the impurity layers, an insulating film, and an electrode by changing a potential. 2 Island-shaped cell regions are arranged in the row and column directions, are commonly connected in the row or column direction, and are connected in common in the row or column direction, by changing the potential of the semiconductor region extending in the row or column direction. 2. The semiconductor memory device according to claim 1, wherein a cell area in a column direction is selected.