JPH0427572B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control method that allows the amount of microprograms to be reduced when performing the same processing on multiple external inputs. .

Microprogram control methods are currently widely used mainly for central processing units such as computers and controllers, but because they can provide high flexibility in the control unit configuration, they can be used for various intelligence input/output devices and functions. Its use in modules is also progressing.

By the way, in intelligence input/output devices, functional modules, etc., when performing the same processing on multiple external inputs, for example, counting the pulse characteristics of multiple pulse trains for each pulse train. There is. Conventionally, in such cases, in order to reduce the amount of hardware, the processing for each external input was written in a microprogram.
When an external input occurs, a processing program corresponding to the external input is executed, but since a processing program must be provided to correspond to the external input, the amount of microprograms increases in proportion to the number of external inputs. , it had the disadvantage that the program structure became complicated.

FIG. 1 is a block diagram for explaining the conventional method, and is for the case where the number of pulses in each of a plurality of pulse trains is counted. In the figure, 1 indicates a micro sequencer 2, a micro program memory 3 in which micro instructions are stored, a pipeline register 4, a branch control circuit 5,
A microprogram control section consisting of a test condition selection circuit 6; 7 is an arithmetic control section consisting of an arithmetic circuit 8, an arithmetic register 9, and a memory 10; 11X, 11Y;
11Z is an input terminal for the pulse trains X, Y, and Z, respectively, and 12 is an OR gate. FIG. 2 shows an example of the format of microinstructions stored in the microprogram memory 3, where BOP is a branch control field that determines the operation mode of the microprogram control section 1, and TCS is a branch control field that determines the operation mode of the microprogram control section 1. A test condition selection field indicating which of the applied pulse trains X, Y, and Z, the output signal RT of the OR gate 12, and the output signal AL of the arithmetic circuit 8 (for example, a signal indicating overflow, etc.) is to be applied to the branch control circuit 5. , BAD is a branch address field indicating the address of the branch destination, MAD is a memory address field indicating the address of the memory 10, and AOP is an arithmetic control unit control field. Further, FIG. 3 is a diagram showing an example of a microprogram for counting processing stored in the microprogram memory 3.

First, the functions of each part in FIG. 1 will be explained. The microsequencer 2 specifies an address in the microprogram memory 3 and reads out the microinstruction written at the address, and the read microinstruction is added to the pipeline register 4. Pipeline register 4 also provides a branch control field for the set microinstruction.
Add BOP, test condition selection field TCS, arithmetic control unit control field AOP, memory address field MAD, and branch address field BAD to the branch control circuit 5, test condition selection circuit 6, arithmetic register 9, memory 10, and microsequencer 2, respectively. It is something.

Further, the test condition selection circuit 6 selects the OR gate 1 according to the contents of the test condition selection field TCS.
2, the pulse trains X, Y, Z, and the output AL of the arithmetic circuit 8 are selected and applied to the branch control circuit 5. Further, the branch control circuit 5 decodes the contents of the branch control field BOP,
Based on the decoding result, a control signal is created to control the operation of the microsequencer 2. If the content of the branch control field BOP is PC+1 mode, the control signal to advance sequentially is created, and if it is in branch mode, the control signal is created to control the operation of the microsequencer 2. has a branch address field
If the control signal that causes the contents of BAD to be output as is is in conditional branch mode, the contents of the branch address field BAD will be output when the signal applied via the test condition selection circuit 6 becomes “1”. This is to add a control signal to the microsequencer 2 that causes it to be output as is.

Also, the memory 10 to which the memory address field MAD is added from the pipeline register 4
As shown in the figure, areas CTX, CTY, and CTZ are provided to store the number of input pulses of pulse trains When specified, the number of input pulses stored in the specified area is added to one input terminal of the arithmetic circuit 8,
The arithmetic circuit 8 adds this number of input pulses to the numerical value added from the arithmetic register 9 to the other input terminal, and stores the addition result in the specified area of the memory 10 again. Furthermore, normally,
The value added from the calculation register 9 to the calculation circuit 8 is "1" to make the number of input pulses stored in each area CTX, CTY, CTZ equal to the actual number of input pulses. The numerical value added to circuit 8 is the arithmetic control section control field.
Since it can be set freely depending on the contents of the AOP, the value added to the arithmetic circuit 8 is set to, for example, "N" (N is an integer), and the number of input pulses stored in each area is set to the actual number of input pulses. It can also be multiplied by N.

Next, with reference to FIG. 3, the microprogram for counting stored in the microprogram memory 3 and the operation of the apparatus shown in FIG. 1 will be explained in relation to each other.

The microprogram control unit 1 always reads the microprogram A shown in the figure from the microprogram memory 3 and checks whether there is a pulse input, that is, whether the output of the OR gate 12 is 1" or 0. There is. In addition, at this time, ORGATE 1
The contents of the test condition selection field TCS are set so that the output signal RT of No. 2 is applied to the branch control circuit 5 via the test condition selection circuit 6.

Then, the output signal RT of the OR gate 12 is
1", the microprogram B shown in the figure is read out from the microprogram memory 3, and
It is checked whether the input pulse is of pulse train X, and if it is determined that the input pulse is pulse train X, subroutine E is executed to count up the number of input pulses stored in area CTX of memory 10. If the pulse input is not the pulse train X, the microprogram C for checking whether the pulse input is the pulse train Y is read out from the microprogram memory 3. Furthermore, microprogram B has branch control field BOP=
〓Conditional branch mode”, test condition selection field
TCS=〓Select pulse train X”, Branch address field BAD=〓Start address of subroutine E”
This is what has become the norm. That is, the branch control circuit 5
As mentioned above, if the content of the branch control field BOP is conditional branch mode, when the signal from the test condition selection circuit 6 becomes 〓1'',
Branch address field in micro sequencer 2
Since a control signal is added to output the contents of BAD as is, if the pulse input is from pulse train The subroutine E is added to the program memory 3 and read out. In this case, the memory address field MAD of subroutine E contains the area CTX of memory 10.
The address of
When the subroutine E is set in the pipeline register 4, the memory 10 calculates the number of input pulses stored in the area CTX corresponding to the pulse train Usually, "1") is added, and the addition result is stored in the area CTX again as the number of input pulses. Thereafter, a return instruction (RETURN) is executed and the microprogram C is read from the microprogram memory 3.

Also, when the microprograms C and D detect that the pulse input is the pulse train Y and Z, the subroutines F and G corresponding to the pulse train Y and Z are read out and the area of the memory 10 is read out, as described above. The number of input pulses stored in CTY and CTZ is counted up.

As mentioned above, the conventional method uses multiple external inputs (pulse trains X, Y, Z in the explanation of the conventional example).
Even if the same processing is to be performed on the external input, a processing program (subroutines E, F, and G in the conventional example) is provided for the external input. The problem is that the number of programs increases in proportion to the number of programs, making the program description complex.

The present invention has improved the above-mentioned drawbacks, and its purpose is to enable one processing program to process multiple external inputs when the same process is performed on multiple external inputs. By doing so, it is possible to prevent an increase in the amount of microprograms and to enable simple microprogram description. Examples will be described in detail below.

FIG. 4 is a block diagram of an embodiment of the present invention, in which the number of input pulses of each of a plurality of pulse trains is counted. In the figure, 13 is an encoder, and the same reference numerals as in the other figures in FIG. 1 represent the same parts. Further, FIG. 5 shows an example of a microprogram for counting processing stored in the microprogram memory 3.

When the pulse of the pulse train X is applied from the input terminal 11
When pulses of pulse train Y are added from input terminal 11Y, signal a becomes 〓0'' and signal b becomes 〓1''. When pulses of pulse train Z are applied from input terminal 11Z, signal a becomes 〓1''. , the signal b is 〓0'',
These signals a and b are stored in the memory address field.
It is added to the most significant digit side of MAD, and is added to memory 10, and memory 10 also receives signals a and b from encoder 13 and memory address field MAD from pipeline register 4.
The data (number of input pulses) stored at the address determined by the contents of is read out and applied to one input terminal of the arithmetic circuit 8. Then, in the arithmetic circuit 8, the number of input pulses from the memory 10 and the numerical value from the arithmetic register 9 are added together in the same way as described above, and the addition result is used as the number of input pulses to add the signals a, b and the memory again. It is stored at the address determined by the address field MAD.

Therefore, in this case, the microprogram memory 3
As shown in Figure 5, the presence or absence of pulse input,
That is, whether the output of the OR gate 12 is 〓1''〓
It is sufficient to store only the microprogram A that checks whether the pulse input is 0" and the subroutine B for counting processing. In other words, the microprogram A checks whether there is a pulse input, and if there is a pulse input, it is necessary to store it. For example, subroutine B for counting processing is read from the microprogram memory 3 and set in the pipeline register 4, and is then read out based on the contents of the memory address field MAD set in the pipeline register 4 and the output signals a and b of the encoder. This method specifies the area corresponding to the input pulse train, and adds the number of input pulses stored in the specified area to one input terminal of the arithmetic circuit 8. There is no need to provide a microprogram to check whether it is a pulse or not, and there is no need to provide a processing program (subroutine) for pulse trains, so the amount of microprograms can be significantly reduced compared to conventional methods. can.
In addition, in subroutine B in the same figure, △ is X,
It indicates either Y or Z, and encoder 1
Depending on the output signals a and b of No. 3, any one of X, Y, and Z is automatically set.

In addition, in the embodiment, the case where the same processing is performed on multiple external inputs has been explained.
Of course, the present invention can also be applied to a case where there are a plurality of sets of external inputs that perform the same processing, and the processing content of each set is different.

As explained above, the present invention is provided with detection means such as the encoder 13 for detecting which of a plurality of external inputs is applied.
Unlike the conventional method, there is no need to provide a processing program to check which of the external inputs has been applied. Since the processing results obtained in B) are stored in an area of the memory corresponding to external input, a processing program (subroutines E to G in the explanation of the conventional example) is provided to correspond to external input, as in the conventional method. Therefore, there is an advantage that the amount of microprogram can be significantly reduced compared to the conventional method, and the structure of the microprogram can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a diagram showing an example of the format of a microinstruction, FIG. 3 is a diagram showing an example of a microprogram in the conventional system, and FIG. 4 is a diagram showing an example of the implementation of the present invention. An example block diagram, FIG. 5, is a diagram showing an example of a microprogram in the system of the present invention. 1 is a micro program control unit, 2 is a micro sequencer, 3 is a micro program memory, 4
is a pipeline register, 5 is a branch control circuit, and 6 is a pipeline register.
1 is a test condition selection circuit, 7 is an arithmetic control section, 8 is an arithmetic circuit, 9 is an arithmetic register, 10 is a memory, 11
X~11Z are input terminals, 12 is an OR gate, 13
is an encoder.

Claims (1)

[Claims] 1. In a microprogram control method in which the same process is executed for a plurality of external inputs according to a microprogram, the plurality of external input identification means for identifying an external input of the plurality of external inputs and outputting address information that becomes part of an address signal of an area corresponding to the external input of the memory based on the identification result; and a microprogram memory storing a microprogram including one subroutine program for executing the process, and when the external input is detected, the subroutine program is read from the microprogram memory and the process for the external input is executed. A microprogram that is executed and stores a processing result in an area of the memory corresponding to an external input specified by a combination of address information output from the external input identification means and address information within the microprogram. control method.