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JPH04275610A - Clock generating circuit - Google Patents

Clock generating circuit

Info

Publication number
JPH04275610A
JPH04275610A JP3034945A JP3494591A JPH04275610A JP H04275610 A JPH04275610 A JP H04275610A JP 3034945 A JP3034945 A JP 3034945A JP 3494591 A JP3494591 A JP 3494591A JP H04275610 A JPH04275610 A JP H04275610A
Authority
JP
Japan
Prior art keywords
circuit
oscillator
frequency
clock
ambient temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3034945A
Other languages
Japanese (ja)
Inventor
Mikio Kiyono
清野 幹雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3034945A priority Critical patent/JPH04275610A/en
Publication of JPH04275610A publication Critical patent/JPH04275610A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a logic circuit from malfunctioning by generating a clock whose oscillation frequency is lower than specified when ambient temperature rises above a prescribed range. CONSTITUTION:An oscillator 1 oscillates at the specific frequency and an oscillator 2 oscillates at a lower frequency than the oscillator 1. The outputs of both the oscillators 1 and 2 are connected to a switching circuit 3, the measurement signal of a temperature sensor 5 is compared by a decision circuit 4 with a prescribed value, and the comparison result is supplied to the switching circuit 3. The clock of the logic circuit 6 is supplied from the output of the switching circuit 3. When the ambient temperature rises above the specific range, the operation speed of the logic circuit 6 becomes slow and the circuit does not operate at the clock frequency. The deviation in the ambient temperature from the specific range is detected by the temperature sensor 5 and decision circuit 4. Consequently, the logic circuit 6 is prevented from malfunctioning.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はクロック発生回路に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit.

【0002】0002

【従来の技術】従来、クロック発生回路は固定された発
振周波数の発振器を一個有し、または複数有して試験時
にその周波数を切り換えている。
2. Description of the Related Art Conventionally, a clock generation circuit has one or more oscillators with a fixed oscillation frequency, and the frequency is switched during testing.

【0003】0003

【発明が解決しようとする課題】従来のクロック発生回
路は、動作環境における異常な温度上昇に伴なって、C
MOS論理回路等の動作速度は遅くなる為、所定のクロ
ック周波数では正規の動作が損われることがある。
[Problems to be Solved by the Invention] Conventional clock generation circuits suffer from the problem of C
Since the operating speed of MOS logic circuits and the like becomes slow, normal operation may be impaired at a predetermined clock frequency.

【0004】0004

【課題を解決するための手段】本発明のクロック発生回
路は、第一の発振器と、これより発振周波数の低い第二
の発振器と、周囲温度を測る温度センサと、前記温度セ
ンサ出力が規定値を越えたかどうかを判別する判定回路
と、前記判定回路の出力信号にもとづいて前記発振器の
出力を切り換える切り換え回路とを有している。
[Means for Solving the Problems] The clock generation circuit of the present invention includes a first oscillator, a second oscillator whose oscillation frequency is lower than the first oscillator, a temperature sensor that measures ambient temperature, and an output of the temperature sensor that is set to a specified value. and a switching circuit that switches the output of the oscillator based on the output signal of the determining circuit.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例の回路図である。発振器1
は所定周波数F1を発生し、発振器2はF1より低い周
波数F2を発生する。これら両発振器1,2の出力は切
り換え回路3に接続され、温度センサ5の測定信号を判
定回路4で規定値と比較されその比較結果が切り換え回
路3に供給される。論理回路6のクロックは切り換え回
路3の出力から供給される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. Oscillator 1
generates a predetermined frequency F1, and the oscillator 2 generates a frequency F2 lower than F1. The outputs of these oscillators 1 and 2 are connected to a switching circuit 3, and a determination circuit 4 compares the measurement signal of the temperature sensor 5 with a specified value, and the comparison result is supplied to the switching circuit 3. The clock for logic circuit 6 is supplied from the output of switching circuit 3.

【0006】論理回路6の動作クロック周波数F1は周
囲温度が所定範囲内にある時正常動作が可能な最高周波
数F1となっている。周囲温度がこの所定範囲よりも高
くなると論理回路6の動作速度は遅くなりクロック周波
数F1では動作しなくなる。本実施例ではこのような周
囲温度の所定範囲からの逸脱を温度センサ5と判定回路
4とで検出する。規定以上の温度上昇が検出されると切
り換え回路3はF2発振器2の出力を選択して論理回路
6へ供給する。即ち所定よりもクロック周波数を下げて
論理回路6の動作を可能にする。
The operating clock frequency F1 of the logic circuit 6 is the highest frequency F1 that allows normal operation when the ambient temperature is within a predetermined range. When the ambient temperature rises above this predetermined range, the operating speed of the logic circuit 6 becomes slow and it no longer operates at the clock frequency F1. In this embodiment, the temperature sensor 5 and the determination circuit 4 detect such deviation of the ambient temperature from a predetermined range. When a temperature rise above a specified value is detected, the switching circuit 3 selects the output of the F2 oscillator 2 and supplies it to the logic circuit 6. That is, the clock frequency is lowered than a predetermined value to enable the logic circuit 6 to operate.

【0007】[0007]

【発明の効果】以上説明したように本発明は、周囲温度
が規定範囲を越えて上昇すると発振周波数が所定よりも
低いクロックを発生することにより、論理回路の誤動作
を防ぐことが出来る。
As described above, the present invention can prevent malfunctions of logic circuits by generating a clock whose oscillation frequency is lower than a predetermined value when the ambient temperature rises beyond a predetermined range.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1    発振器 2    発振器 3    切り換え回路 4    判定回路 5    温度センサ 6    論理回路 1 Oscillator 2 Oscillator 3 Switching circuit 4 Judgment circuit 5 Temperature sensor 6 Logic circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  第一の発振器と、これより発振周波数
の低い第二の発振器と、周囲温度を測る温度センサと、
前記温度センサ出力が規定値を越えたかどうかを判別す
る判定回路と、前記判定回路の出力信号にもとづいて前
記第一と第二の発振器の出力を切り換える切り換え回路
とを含むことを特徴とするクロック発生回路。
Claim 1: A first oscillator, a second oscillator with a lower oscillation frequency, and a temperature sensor that measures ambient temperature.
A clock comprising: a determination circuit that determines whether the output of the temperature sensor exceeds a specified value; and a switching circuit that switches outputs of the first and second oscillators based on an output signal of the determination circuit. generation circuit.
JP3034945A 1991-03-01 1991-03-01 Clock generating circuit Pending JPH04275610A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3034945A JPH04275610A (en) 1991-03-01 1991-03-01 Clock generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3034945A JPH04275610A (en) 1991-03-01 1991-03-01 Clock generating circuit

Publications (1)

Publication Number Publication Date
JPH04275610A true JPH04275610A (en) 1992-10-01

Family

ID=12428311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3034945A Pending JPH04275610A (en) 1991-03-01 1991-03-01 Clock generating circuit

Country Status (1)

Country Link
JP (1) JPH04275610A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655838A2 (en) * 1993-11-26 1995-05-31 TEMIC TELEFUNKEN microelectronic GmbH Method for operating a digital logic semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02183321A (en) * 1989-01-10 1990-07-17 Nec Corp Clock generation circuit
JPH02207312A (en) * 1989-02-08 1990-08-17 Nec Corp Clock generating circuit
JPH0318912A (en) * 1989-06-15 1991-01-28 Nec Corp Clock signal generating circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02183321A (en) * 1989-01-10 1990-07-17 Nec Corp Clock generation circuit
JPH02207312A (en) * 1989-02-08 1990-08-17 Nec Corp Clock generating circuit
JPH0318912A (en) * 1989-06-15 1991-01-28 Nec Corp Clock signal generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655838A2 (en) * 1993-11-26 1995-05-31 TEMIC TELEFUNKEN microelectronic GmbH Method for operating a digital logic semiconductor device
EP0655838A3 (en) * 1993-11-26 1995-12-06 Telefunken Microelectron Method for operating a digital logic semiconductor device.

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Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19970924