JPH04269677A - Pll circuit device - Google Patents

Abstract

PURPOSE:To enable combining in a system and generating PLL slip imperatively by providing a first frequency dividing circuit with variable frequency division ratio. CONSTITUTION:By changing the initialization value of a frequency division counter constituting a first frequency division circuit, the frequency division ratio changes and following to this, the frequencies of two clocks mCLK and sCLK for phase comparison object change and PLL slip is generated. This PLL slip is detected with an error detection circuit 4. By this, PLL slip is generated imperatively and the inspection of status accompanying an error due to the generation of the PLL slip and the inspection of the function of the error detection circuit 4, etc., are automatically done.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION The present invention proposes a completely new PLL circuit device that can forcibly generate a PLL slip.

0002

[Prior Art] In a system equipped with a PLL circuit, a PLL slip (a phase shift between two pulse signals to be compared in the PLL circuit) is forcibly generated to inspect the operation of the system, or PLL
Operations such as checking the operation of an error detection circuit that detects the occurrence of a slip are performed. FIG. 1 shows a PLL circuit device, and the PLL circuit 3 includes a phase comparator 31, an LPF
(low pass filter) section 32 and VCO (voltage controlled oscillator) section 33. The first frequency dividing circuit 1 to which the master clock is input divides the master clock by 1/M (M is an integer) and outputs the clock mCLK, and the phase comparator 3
1 is used as one input.

[0003] The slave clock that is the output of the PLL circuit 3 is given to the second frequency divider circuit 2, and the clock sCLK obtained by dividing the frequency by 1/N (N is an integer) is sent to the phase comparator 31. is given as input. With this circuit configuration, the PLL circuit 3 output, that is, the slave clock, has a frequency of 1/N of the clock mCLK.
A clock with a stable frequency of 1/M·N of the frequency of the master clock can be obtained. clock mCLK,
sCLK is also input to the error detection circuit 4,
If there is a phase shift between the two, that is, a PLL slip, this is detected and a PLL error signal is generated. In order to check whether or not the error detection circuit 4 operates, it is necessary to forcibly generate a PLL slip. Conventionally, PL was controlled by cutting off the master clock, or cutting off the master clock supply from the master clock generation source (for example, a crystal oscillator), and replacing it with a frequency synthesizer output, and changing the output.
It was planned that an L slip would occur.

0004

[Problem to be solved by the invention] For this reason, P as shown in the figure
Although it is possible to generate a PLL slip using only the LL circuit device, it is actually impossible to generate a PLL slip in a system incorporating this device. In particular, it is impossible to automatically perform self-diagnosis during system operation. The present invention forcibly executes PLL even when it is incorporated into a system or when the system is operated.
Completely new PLL that can generate slips
The purpose is to provide a circuit device.

[0005]

[Means for Solving the Problems] In the PLL circuit device of the present invention, a PLL slip can be generated arbitrarily by making the first frequency dividing circuit 1 variable in frequency division ratio.

[0006]

[Operation] The first frequency dividing circuit 1 is constituted by a frequency dividing counter. By changing the initial setting value of this counter, the frequency division ratio changes, and accordingly, the frequency values of the two clocks mCLK and sCLK whose phases are compared change, and the PLL
A slip occurs. This PLL slip is detected by the error detection circuit 4.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof. Although the PLL circuit device of the present invention differs in the configuration of the first frequency dividing circuit 1 that divides the master clock, the overall configuration is shown in FIG. 1 as in the conventional PLL circuit device. That is, the PLL circuit 3 includes a phase comparator 31, LP
It is composed of an F (low pass filter) section 32 and a VCO (voltage controlled oscillator) section 33. The first frequency dividing circuit 1 to which the master clock is inputted divides the master clock by 1/M (M is an integer) and outputs a clock mCLK, which is used as one input of the phase comparator 31. The slave clock that is the output of the PLL circuit 3 is given to the second frequency divider circuit 2, where the frequency is divided by 1/N (N is an integer) and the resulting clock sC
LK is provided to the phase comparator 31 as another input. The clocks mCLK and sCLK are also input to the error detection circuit 4, and there is a phase difference between them, that is, PL.
L If there is a slip, it is detected and the PLL
I am trying to emit an error signal.

FIG. 2 shows a simplified example of the configuration of the first frequency dividing circuit 1 for the purpose of explanation. The first frequency divider circuit 1 can load the count initial value by applying its ripple carry output terminal RC output to the load terminal LOAD. Top 3 of terminals D0, D1, D2, and D3 for setting initial values
Bits D1, D2, and D3 are given fixed values, for example, "0", and the lowest one bit D0 is given "0" or "1" from the initial value setting circuit 11. This initial value setting circuit 11 is, for example, a microprocessor that controls the entire system including this PLL circuit device. The master clock is applied to the terminal CLK of the first frequency dividing circuit 1 as a counting target. Further, the carry output is used as the clock mCLK.

The frequency division ratio of the first frequency dividing circuit 1 is such that the D0 input is “
If the D0 input is “1”, the division ratio is 1/(M-1).
(1/15 in Figure 2). In other words, by changing the frequency division ratio in this way, the clock mCLK changes, and the clock sCLK changes accordingly, causing a PLL slip. For communication, master clock,
The slave clock is on the order of several MHz to several tens of MHz, and the clock mCLK is on the order of several kHz. Therefore, the frequency division ratio M is approximately 212.

FIG. 3 is a block diagram showing the configuration of the first frequency dividing circuit 1 in this case. 4-bit frequency division counter 21,
22 and 23 are connected in series. The ripple carry output terminal RC of the first stage frequency division counter 21 is connected to the enable terminal EN of the second stage frequency division counter 22, and the ripple carry output terminal RC is connected to the enable terminal EN of the third stage frequency division counter 23. has been done. The third stage ripple carry terminal RC is connected to the load terminal LOA of the full frequency division counters 21, 22, 23 via an inverter.
Connected to D.

[0011] The master clock is a full frequency division counter 21, 2.
2 and 23 counting input terminals CLK. 2
The initial value input terminals of the frequency dividing counters 22 and 23 in the third and third stages are all fixed to "0". Upper 3 bits D1, D2, D of the initial value input terminal of the first stage frequency division counter 21
3 is fixed at "0", and only the least significant bit D0 is set to "0" or "1" by the initial value setting circuit 11. The carry output of the third stage is used as the clock mCLK.

In the first frequency dividing circuit 1 having such a configuration, when the least significant bit is set to "0", the frequency dividing counter 21 is set to 2.
A ripple carry signal is generated at a count of 4=16, and since the second stage frequency division counter 22 is enabled at this time, the frequency division counter 22 generates a ripple carry signal at a master clock input of 28. Since this is given to the third-stage frequency division counter 23, the output of the frequency division counter 23, that is, the clock mCLK, becomes a frequency-divided output of 212=4096. Therefore, when the least significant bit is set to "1", the first frequency dividing circuit 1 becomes a 4095 frequency dividing circuit.

The rate of change in the frequency division ratio is expressed by the following equation (1).

[{C/(M-1)}-(C/M)]/(C/M)
...(1) However, C: Master clock frequency

[0015] Now, C=32.768MHz, M=4
096, the value of formula (1) is 244.200243
8 x 10-6, and a frequency change of about 244 ppm is possible. FIG. 4 shows another example of the first frequency dividing circuit. In this example, all bit values of the initial value are stored in the memory 12, so that changes in the frequency division ratio can be freely selected within a wider range. Of course, it is not necessary to store all bits, but a plurality of necessary bits may be changed.

[0016]

[Effects of the Invention] According to the present invention as described above, a PLL slip can be forcibly generated regardless of the connection status and operation status of the PLL circuit device. Therefore, the present invention provides P
This is extremely useful for automatically performing inspections of conditions associated with errors caused by occurrence of LL slips, function inspections of error detection circuits, and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PLL circuit device.

FIG. 2 is a schematic configuration diagram of a first frequency dividing circuit.

FIG. 3 is a block diagram of a first frequency dividing circuit.

FIG. 4 is a schematic configuration diagram of a first frequency dividing circuit.

[Explanation of symbols]

1 First frequency divider circuit 2 Second frequency divider circuit 3 PLL circuit 31 Phase comparison section 32 LPF section 33 VCO Department

Claims (1)

[Claims] [Claim 1] A first frequency dividing circuit (1
), a PLL circuit (3) which uses the output of the first frequency dividing circuit (1) as one input of its phase comparator (31), and divides the output of the VCO section (33) of the PLL circuit (3). In the PLL circuit device, the first frequency dividing circuit (1) is configured to set a frequency division ratio. A PLL circuit device characterized by being variable.