JPH0426917Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a bus relay device that connects parallel buses such as electronic control devices, and particularly relates to enhancement of bus abnormality detection function.

(Conventional technology) FIG. 5 is a configuration diagram of a conventional bus relay device.

In such a bus relay device, a parity bit is added to the bus (hereinafter referred to as an upper bus) when the reliability of information transmission is particularly desired to be ensured in the control device used. No parity bit is used on the bus for transmission (hereinafter referred to as the lower bus). Therefore, when connecting the buses of such devices, the following measures have been taken for bus relay devices.

(1) Upper bus → lower bus Information transmitted from the upper bus to the lower bus is checked for consistency between address data, write data, and parity bits. As a result, an abnormality occurs on the upper bus (for example,
(Hiclump, Low clamp, etc.) can often be found.

(2) Lower bus → upper bus When data is transmitted from the lower bus to the upper bus, there is no redundancy in the lower bus, so even if an error occurs in the lower bus, it is assumed that no error has occurred in the upper bus. A parity bit is added accordingly.

(Problem that the invention aims to solve) However, with conventional devices, when data is transmitted from a lower bus to an upper bus, an abnormality that occurs in the lower bus cannot be discovered on the upper bus side, and the parity bit does not operate effectively. There was a problem.

Incidentally, failures in data signal lines have a low occurrence rate and failures occur independently for each bit, so the probability that two or more data signal lines will fail at the same time is extremely low. Therefore, there is virtually no problem in detecting a failure in only one or an odd number of data signal lines.

The present invention solves these problems,
It is an object of the present invention to provide a bus relay device capable of detecting an abnormality occurring in one or an odd number of data signal lines of a lower bus on the upper bus side.

(Means for Solving the Problems) The present invention that achieves the above object has a high level bus with a parity bit added and a logic high or low level when the data bus is not in use and has no parity bit.
In a bus relay device that connects a lower bus with a pull-up/down means that uniquely fixes the
It has the following configuration.

That is, a first bus transceiver that transmits data from the upper bus to the lower bus, a second bus transceiver that transmits data from the lower bus to the upper bus, and a control signal between the upper bus and the lower bus. a control circuit that controls opening and closing of these first and second bus transceivers based on;
When the data on the lower bus is input and the control signal does not instruct data transfer, a parity check is performed on the data bus of the lower bus, and when the control signal instructs data transmission from the upper bus to the lower bus. a parity check generator that performs a parity check on the upper bus in a state in which the upper bus is in the upper bus, and generates parity bits based on data on the lower bus in a state in which a control signal instructs data transmission from the lower bus to the upper bus; The parity check generator circuit comprises a mask circuit that stops the bus relay operation of the control circuit when a parity check abnormality is detected in the parity check generator circuit.

(Function) Each component of the present invention has the following function. The pull-up/down means maintains the logic of the data bus of the lower bus constant when not in use. The parity check/generator circuit performs a parity check on the lower bus when not in use to determine whether there is an abnormality or not, and when an abnormal situation occurs, the mask circuit is used to stop the use of the upper bus and the lower bus.

(Example) The present invention will be explained below using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11 is a bus control signal line of the upper bus, 12 is a data signal line of the upper bus, and 13 is a parity bit of the upper bus, which operates depending on the bit state of the data signal line 12.

21 is a control signal line of the lower bus, and 22 is a data signal line of the lower bus. data signal line 2
2 is equipped with a means for uniquely fixing the logic to H or L when not in use. For example, an open collector type bus driver and a pull-up resistor may be used, or the terminal of the tri-state bus driver may be terminated with a resistor. It may be pulled up or pulled down.

30 is a bus relay device, the details of which are as follows. 31 is a control circuit that operates based on the control signal lines 11 and 21 of the upper bus and lower bus; 32 is a control circuit that operates from the data signal line 12 to the data signal line 2;
a first bus transceiver for transmitting data to the second bus transceiver;
Opening and closing operations are performed according to instructions from the control circuit 31. 3
A second bus transceiver 3 transmits data from the data signal line 22 to the data signal line 12, and opens and closes according to instructions from the control circuit 31. 34 is a parity check generator circuit which performs a parity check on the data signal line 22 when the control signals on the control signal lines 11 and 21 do not instruct data transfer, and the control signal is transferred from the data signal line 12 to the data signal line 22. When the control signal is instructing data transmission from the data signal line 22 to the data signal line 12, a parity check is performed on the data signal line 22, and when the control signal is instructing data transmission from the data signal line 22 to the data signal line 12, the data on the data signal line Based on this, a parity bit is generated and output to the data signal line 12. 35 is a parity check generator circuit 34, and when an abnormality in the parity check is detected, the control circuit 3
This is a mask circuit for stopping the bus relay operation of No. 1, and is provided inside the control circuit 31 here.

The operation of the apparatus configured in this way will be explained separately for each case.

(1) For light sequence FIG. 2 is a flowchart of the write sequence.

The bus master outputs a bus sequence start signal to the control signal line 11 and an address signal to the data signal line 12 (T1). Then, the parity check generator circuit 34 connects the data signal line 22.
It is determined whether the signals on all data signal lines 22 match predetermined logic signals (T2). When an abnormality is detected, the operation of the control circuit 31 is stopped via the mask circuit 35, and the following operations are inhibited.

The control circuit 31 opens the bus transceiver 32;
The address signal of the data signal line 12 is passed to the data signal line 22. The parity check generator circuit 34 performs a parity check when the data signal line 22 is settled (T3). When a parity error occurs, the operation of the control circuit 31 is stopped via the mask circuit 35, and the following operations are inhibited.

The control circuit 31 sends a bus sequence start signal to the control signal line 21 (T4). Then, the slave station connected to the lower bus receives the bus sequence start signal from the control signal line 21 and sends back an address reception signal to the control signal line 21 (T5).

The control circuit 31 transfers the address reception signal to the control signal line 11 and transfers the address reception signal to the bus transceiver 32.
Close (T6).

When the bus master receives the address acceptance signal,
Write data is output on the data signal line 12, and a write data sending signal is output on the control signal line 11 (T7).

When the control circuit 31 receives the write data sending signal, it opens the bus transceiver 32 and sends the write data onto the data signal line 22 (T8). The parity check generator circuit 34 determines the consistency between the parity bit of the upper bus and the write data on the data signal line 22 when the data signal line 22 is settled. When an abnormality is detected, the operation of the control circuit 31 is stopped via the mask circuit 35, and the following operations are inhibited.

The control circuit 31 outputs a write data sending signal to the control signal line 21 (T9). Then, the slave station connected to the lower bus receives the write data sending signal from the control signal line 21 and sends back the write data reception signal to the control signal line 21 (T10).

The control circuit 31 transfers the write data reception signal to the control signal line 11 (T11). When the bus master receives the write data reception signal, it pulls up the write data on the data signal line 12 and the write data sending signal on the control signal line 11, and performs a sequence end operation (T12). The control circuit 31 closes the bus transceiver 32 and performs a sequence end operation (T13).

(2) For read sequence FIG. 3 is a flowchart of the read sequence.

In the case of a read sequence, the same operations as T1 to T6 of the write sequence are performed.

After that, when the bus master receives the address reception signal, it issues a read data request signal on the control signal line 11 (T7).

When the control circuit 31 receives the read data request signal, it transfers it to the control signal line 21 (T
8).

Then, the slave station connected to the lower bus receives the read data request signal from the control signal line 21, issues a read data sending signal to the control signal line 21, and issues read data to the data signal line 22 (T9).

When the control circuit 31 receives the read data sending signal from the control signal line 21, it reads the read data from the data signal line 22, generates a parity bit via the parity check generator circuit 34, and sends it to the upper bus (T10). .
Further, the control circuit 31 opens the bus transceiver 32 to transfer read data from the data signal line 22 to the data signal line 21 and transfers a read data sending signal from the control signal line 21 to the control signal line 11.

When the bus master receives the read data sending signal, it pulls up the control signal on the control signal line 11 and performs a sequence end operation (T11).

The control circuit 31 closes the bus transceiver 32;
Also, the sending of the parity bit is stopped and the sequence ends (T12).

The slave station stops sending read data and performs a sequence end operation (T13).

FIG. 4 is a block diagram showing a second embodiment of the present invention. In FIG. 4, parts having the same functions as those in FIG.

In this embodiment, bus transceivers 32, 33
bus transceiver 32.
a, 32b, 33a, 33b, and internal buses 36, 37 are provided in the middle. By doing this, you can easily expand the bus relay device by connecting other devices to the internal buses 36 and 37, or connect a board with a check function to the internal buses 36 and 37, and use the bus relay device itself. Can determine failure.

(Effects of the invention) As explained above, according to the invention, in a bus relay device that connects an upper bus to which a parity bit is added and a lower bus that does not have a parity bit and is at logic H (or L) when not in use. ,
Low clamp (or Hi clamp) on lower bus
Since failures are realized through a parity check function, errors can be detected with only a small amount of modification compared to conventional devices, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart of a write sequence, FIG. 3 is a flowchart of a read sequence, and FIG. 4 is a flowchart of a write sequence.
FIG. 2 is a configuration block diagram showing a second embodiment of the present invention. FIG. 5 is a configuration diagram of a conventional bus relay device. 11, 21...control signal line, 12, 2
2...Data signal line, 13...Parity bit,
31... Control circuit, 32, 33... Bus transceiver, 34... Parity check/generator circuit, 35... Mask circuit.

Claims (1)

[Claims for Utility Model Registration] Connecting an upper bus with a parity bit added to a lower bus without a parity bit and equipped with pull-up/down means for uniquely fixing the logic to H or L when the data bus is not in use. In the bus relay device, a first bus transceiver that transmits data from the upper bus to the lower bus, a second bus transceiver that transmits data from the lower bus to the upper bus, and between the upper bus and the lower bus. a control circuit that controls opening and closing of the first and second bus transceivers based on control signals of the lower bus; In the state where the control signal instructs data transmission from the upper bus to the lower bus, the parity check of the upper bus is performed, and the control signal transmits data from the lower bus to the upper bus. When a parity check error is detected in this parity check generator circuit, the parity check generator circuit generates a parity bit based on the data on the lower bus. A bus relay device comprising: a mask circuit for stopping relay operation; and a bus relay device.