JPH04262562A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04262562A JPH04262562A JP2249991A JP2249991A JPH04262562A JP H04262562 A JPH04262562 A JP H04262562A JP 2249991 A JP2249991 A JP 2249991A JP 2249991 A JP2249991 A JP 2249991A JP H04262562 A JPH04262562 A JP H04262562A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- chip
- ceramic substrate
- cavity
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000919 ceramic Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 26
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 abstract description 12
- 230000017525 heat dissipation Effects 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 238000005219 brazing Methods 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910001080 W alloy Inorganic materials 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000006260 foam Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910018054 Ni-Cu Inorganic materials 0.000 description 1
- 229910018481 Ni—Cu Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
消費電力の大きな半導体装置のヒートシンクの構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to the structure of a heat sink for a semiconductor device that consumes a large amount of power.
【0002】0002
【従来の技術】最近のハイポーラLSIやMOSLSI
等の半導体装置では、チップの機能増大による入出力ピ
ンの増加と高集積化並び高速動作の相乗作用により、数
W〜数10Wまで消費電力が大きくなり、これに伴って
発生熱量も多くなっている。特に、パターンの微細化で
素子寸法と配線幅が小さくなり集積度が向上し消費電力
が増加する。従って発熱密度(電力/体積)が飛躍的に
増大する。更に、半導体装置の機能の増加による入出力
ピンの増大も避けられない。[Prior art] Recent high-polar LSIs and MOSLSIs
In semiconductor devices such as the There is. In particular, as patterns become finer, element dimensions and wiring widths become smaller, the degree of integration improves, and power consumption increases. Therefore, the heat generation density (power/volume) increases dramatically. Furthermore, an increase in the number of input/output pins due to the increase in the functions of semiconductor devices is unavoidable.
【0003】この様な状況の中で従来の多ピン大型チッ
プを搭載する一般的な半導体装用のパッケージとして図
4に示すフェイスアップ構造のピン・グリッド・アレイ
(以下PGAと呼ぶ)が提案されている。このPGAは
外部リード6をセラミック基板1の裏面全体に取り付け
たフルグリッドPGAである。セラミック基板1の中央
にキャビティ6を設け、その周辺に設けられたボンディ
ング導体4が内部導体5を介して基板外部に向って延長
した外部リード6と接続した構造となっているものであ
る。そしてキャビティ3にICチップ2を固着し、その
チップパッドとボンディング導体4をワイヤー4Aによ
り接続する。また金属シールリング7に金属キャップ8
を載置してシールリング7と金属キャップ8の外周を電
気抵抗溶接してキャップ封止する。従ってこの構造のP
GAは、最小面積で多ピン高密度実装が可能なパッケー
ジ構造とすることができる。Under these circumstances, a pin grid array (hereinafter referred to as PGA) with a face-up structure as shown in FIG. 4 has been proposed as a general semiconductor device package that mounts a conventional large chip with many pins. There is. This PGA is a full grid PGA in which external leads 6 are attached to the entire back surface of the ceramic substrate 1. A cavity 6 is provided in the center of the ceramic substrate 1, and a bonding conductor 4 provided around the cavity is connected to an external lead 6 extending toward the outside of the substrate via an internal conductor 5. Then, the IC chip 2 is fixed in the cavity 3, and the chip pad and the bonding conductor 4 are connected by a wire 4A. In addition, a metal cap 8 is attached to the metal seal ring 7.
The seal ring 7 and the outer periphery of the metal cap 8 are electrically resistance welded to seal the cap. Therefore, P of this structure
The GA can have a package structure that allows high-density mounting of many pins in a minimum area.
【0004】次にこのPGAをプリント板21Aに実装
する場合、貫通孔10にパッケージの外部リード6をリ
ードストッパー6Aまで挿入し半田フローにより半田付
けする。セラミック基板1の底面とプリント板21Aの
間は、半田13Aで固定した後の応力緩和の為に1mm
位の間隔をあけてある。しかしながらこの半田付け実装
したPGAは、チップ放熱面がプリント板側である為に
放熱効果が小さい欠点があった。その対策として図5に
示すように、プリント板21Aとラミック基板1の約1
mmの間隔にヒートシンク16Aを接続した構造のもの
が提案されている。Next, when mounting this PGA on a printed circuit board 21A, the external leads 6 of the package are inserted into the through hole 10 up to the lead stopper 6A and soldered using a solder flow. The distance between the bottom of the ceramic substrate 1 and the printed board 21A is 1 mm to relieve stress after fixing with the solder 13A.
They are spaced apart. However, this soldered-mounted PGA has a drawback in that the heat radiation effect is small because the chip heat radiation surface is on the printed board side. As a countermeasure for this, as shown in FIG.
A structure in which heat sinks 16A are connected at intervals of mm has been proposed.
【0005】このヒートシンク16Aでは、PGAの外
部リード6が挿入できる穴をアルミニウム板に設けてあ
り、その形状は、セラミック基板1の底面から側面に密
着することができるように凹形状になっている。このよ
うな形状に加工したアルミニウム表面にアルマイト処理
をして絶縁性を得ている。これを図5に示した様に半田
付け実装すると熱伝導によりセラミック基板1の裏面か
ら速やかに放熱できる。しかしながら本構造PGAもヒ
ートシンク16Aの穴あけ加工性、放熱性に関与する比
表面積が小さいため放熱効果が小さく、コストが高いと
いう欠点があった。[0005] In this heat sink 16A, a hole is provided in the aluminum plate into which the external lead 6 of the PGA can be inserted, and the hole is concave so that it can be closely attached to the bottom and side surfaces of the ceramic substrate 1. . The aluminum surface processed into this shape is anodized to provide insulation. If this is mounted by soldering as shown in FIG. 5, heat can be rapidly radiated from the back surface of the ceramic substrate 1 due to thermal conduction. However, the PGA of this structure also has the disadvantage that the heat sink 16A has a small specific surface area that is related to the hole-drilling workability and heat dissipation properties, so the heat dissipation effect is small and the cost is high.
【0006】図6はフェイスダウン構造のPGAであり
、実装密度が若干小さくなるが、ヒートシンクがCu−
W合金からなるチップ搭載板17に直接接着することが
できるので放熱効果が高い。しかしながらヒートシンク
16Bそのものは空気中への熱放散をより多くする為に
は表面積を大きく取りたいが、フィン型のヒートシンク
では限界があった。例えば外形寸法として長さ及び幅が
43mm、高さ7.5mm、フィン溝幅1mm、フィン
幅1mmの場合の比表面積(表面積m2 /体積m3
)は860であった。FIG. 6 shows a PGA with a face-down structure, and the mounting density is slightly lower, but the heat sink is Cu-
Since it can be directly bonded to the chip mounting board 17 made of W alloy, the heat dissipation effect is high. However, in order to increase heat dissipation into the air, the heat sink 16B itself needs to have a large surface area, but a fin-type heat sink has its limitations. For example, when the external dimensions are length and width 43 mm, height 7.5 mm, fin groove width 1 mm, and fin width 1 mm, the specific surface area (surface area m2 / volume m3
) was 860.
【0007】[0007]
【発明が解決しようとする課題】上述した従来の半導体
装置のうち、図4に示したフェイスアップ構造のPGA
では、単位面積当たりにおいて最も高密度化が可能で多
ピン化に適した構造である半面、実装構造においてプリ
ント板とパッケージ底面が接触していない為に放熱性が
悪い。その改良構造として図5に示したように、セラミ
ック基板の表面,側面,裏面(プリント板とパッケージ
外部導体間)にヒートシンクを取り付けるものでは、裏
面のヒートシンクは、外部導体の貫通孔を設ける為に、
ヒートシンクの製作が難かしく価格が高くなる欠点があ
った。又図6に示したフェイスダウン構造のものでは、
パッケージとヒートシンクの接続面積が少ないので放熱
性も悪かった。Problems to be Solved by the Invention Among the conventional semiconductor devices described above, the face-up structure PGA shown in FIG.
Although this structure allows the highest density per unit area and is suitable for increasing the number of pins, it has poor heat dissipation because the printed circuit board and the bottom of the package are not in contact with each other in the mounting structure. As shown in Figure 5, an improved structure is one in which a heat sink is attached to the front, side, and back surfaces of the ceramic substrate (between the printed circuit board and the package external conductor). ,
The disadvantage was that the heat sink was difficult to manufacture and expensive. In addition, in the face-down structure shown in Fig. 6,
Heat dissipation was also poor because the connection area between the package and the heat sink was small.
【0008】更に、フェイスアップ構造、フェイスダウ
ン構造共に従来のヒートシンクは、主にアルミニウムを
用いている為に、セラミック基板1にシリコン樹脂12
等で接着して熱膨張差による応力緩和をしなければセラ
ミック基板が割れるという現象が発生する。従って、熱
伝導が樹脂接着材で阻害されるという欠点があった。Furthermore, since conventional heat sinks for both face-up and face-down structures mainly use aluminum, silicone resin 12 is used on ceramic substrate 1.
If stress relaxation due to the difference in thermal expansion is not achieved by adhering the ceramic substrate with a bonding agent or the like, a phenomenon will occur in which the ceramic substrate will crack. Therefore, there was a drawback that heat conduction was inhibited by the resin adhesive.
【0009】[0009]
【課題を解決するための手段】本発明の半導体装置は、
キャビティを有するセラミック基板と、このキャビティ
内に搭載された半導体チップと、前記セラミック基板の
底面または周辺部に設けられた外部リードと、前記セラ
ミック基板表面の少くとも一部に固着された海綿状の金
属骨格を有するヒートシンクとを含むものである。[Means for Solving the Problems] A semiconductor device of the present invention includes:
A ceramic substrate having a cavity, a semiconductor chip mounted in the cavity, an external lead provided on the bottom or peripheral part of the ceramic substrate, and a spongy lead fixed to at least a part of the surface of the ceramic substrate. A heat sink having a metal skeleton is included.
【0010】0010
【実施例】次に本発明について図面を参照して説明する
。図1は本発明の第1の実施例の断面図であり、本発明
をフェイスダウン構造のPGAに適用した場合を示して
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of a first embodiment of the present invention, showing the case where the present invention is applied to a PGA with a face-down structure.
【0011】図1において、セラミック基板1の中央に
はキャビティ3が設けられており、このキャビティ3内
にはCu−W合金等からなるチップ搭載板17がセラミ
ック基板1のメタライズ層上にAg−Cuのロウ材19
Aでろう付けされている。キャビティ3の周辺部のセラ
ミック基板1には、ボンディング導体4が設けられ、内
部導体5を介して外部リード6に接続されている。そし
て、チップ搭載板17にはICチップが搭載され、かつ
チップパッドとボンディング導体4はワイヤー4Aによ
り接続されている。更にICチップ2の保護の為にセラ
ミック又は金属等のキャップ15が低融点硝子又はAu
−Snのろう材19を用いてキャビティの下側に封止し
てある。そしてこのフェイスダウンパッケージを構成す
るセラミック基板1及びチップ搭載板17の表面には、
放熱性を良くするために海綿状の金属骨格を有するヒー
トシンク11が半田13によって接着されている。この
ヒートシンク11は、素材そのものが全体積の93〜9
8%の気孔を有しており、各気孔は隣り同志が連ってお
り、比表面積(m2 /m3 )が500〜1700の
値を有している。In FIG. 1, a cavity 3 is provided in the center of a ceramic substrate 1, and within this cavity 3, a chip mounting plate 17 made of a Cu-W alloy or the like is mounted on a metallized layer of the ceramic substrate 1. Cu brazing material 19
It is brazed at A. A bonding conductor 4 is provided on the ceramic substrate 1 around the cavity 3 and is connected to an external lead 6 via an internal conductor 5. An IC chip is mounted on the chip mounting board 17, and the chip pad and the bonding conductor 4 are connected by a wire 4A. Furthermore, in order to protect the IC chip 2, a cap 15 made of ceramic or metal is made of low melting point glass or Au.
- The lower side of the cavity is sealed using a soldering material 19 of Sn. On the surfaces of the ceramic substrate 1 and the chip mounting board 17 that constitute this face-down package,
A heat sink 11 having a spongy metal skeleton is bonded with solder 13 to improve heat dissipation. The material itself of this heat sink 11 has a total volume of 93 to 9
It has 8% pores, each pore is connected to its neighbor, and the specific surface area (m2/m3) has a value of 500 to 1700.
【0012】このように構成された第1の実施例によれ
ば、外形寸法として長さ及び幅が40mm、高さ7.5
mmのヒートシンクを用いた場合、半導体装置の熱抵抗
は、風速1.5m/secの時に従来タイプの半導体装
置は6℃/Wであるのに対し、実施例では4℃/Wに改
善された。またヒートシンクの気孔率が93〜98%も
あるため、軽量化が可能となった。According to the first embodiment configured as described above, the external dimensions are 40 mm in length and width, and 7.5 mm in height.
When using a mm heat sink, the thermal resistance of the semiconductor device was improved to 4°C/W in the example, compared to 6°C/W for the conventional type semiconductor device at a wind speed of 1.5 m/sec. . Furthermore, since the heat sink has a porosity of 93 to 98%, it has become possible to reduce the weight.
【0013】次にこのヒートシンクの製造方法について
説明する。まずヒートシンク形状に合わせた金型に発泡
樹脂を注入・成形して、ヒートシンクと同形状の発泡樹
脂を用意する。次にこの発泡樹脂の表面と内部気泡の表
面に導電処理を施す。一般的にはカーボン粉末を電着さ
せる。次に電気メッキを行って金属の骨格を形成する。
この骨格は、海綿のように三次元的の網目状になってつ
ながっている。この骨格の厚さは、電気メッキ時間によ
ってコントロールが可能である。骨格となる金属材料は
、Ni,Ni−Cu,Cuその他メッキ可能な材料なら
ば用いることができる。次にメッキ内部に閉じこめられ
た発泡樹脂を加熱処理して分解除去する。次に合金化,
加工処理してヒートシンクとする。Next, a method of manufacturing this heat sink will be explained. First, foam resin is injected and molded into a mold that matches the shape of the heat sink to prepare foam resin that has the same shape as the heat sink. Next, conductive treatment is applied to the surface of this foamed resin and the surfaces of the internal cells. Generally, carbon powder is electrodeposited. Next, electroplating is performed to form a metal skeleton. This skeleton is connected in a three-dimensional mesh like a sponge. The thickness of this skeleton can be controlled by the electroplating time. The metal material serving as the skeleton may be Ni, Ni-Cu, Cu, or any other material that can be plated. Next, the foamed resin trapped inside the plating is heated to be decomposed and removed. Next, alloying,
It is processed and made into a heat sink.
【0014】図2は本発明の第2の実施例の断面図であ
り、本発明をフェースアップ構造のPGAに適用した場
合を示している。FIG. 2 is a sectional view of a second embodiment of the present invention, showing the case where the present invention is applied to a PGA having a face-up structure.
【0015】図2においてこのPGAは、外部リード6
をセラミック基板1の裏面全面に取り付けたフルグリッ
ドPGAであり、セラミック基板1の外部リード6の取
り付け面と反対側の中央にキャビティ3を設け、その周
辺からボンデング導体4を基板外部に向って延長し外部
リード6と接続したものである。そしてキャビティ3内
のセラミック基板1上にICチップ2を固着し、そのチ
ップパッドとボンディング導体4とをワイヤー4Aによ
り接続する。また金属シールリング7に金属製キャップ
8を載置して、シールリングとキャップ外周を電気抵抗
溶接してキャップ封止する。従って最小面積で多ピン高
密度実装が可能なパッケージが完成する。 次でパッ
ケージを構成するセラミック基板1及び金属製キャップ
8の表面に半田または樹脂によりヒートシンク11Aを
固着する。同様にセラミック基板1の下面と側面には、
貫通孔を有する凹状のヒートシンク11Bをはめこみ法
等により固着する。特にこのヒートシンク11Bは、外
部リード6と貫通孔10とを絶縁するために、ヒートシ
ンク全体を溶融したアルミニウムに含浸させて金属表面
にアルミニウムを付着させた後にアルマイト処理を行い
、10μm前後の酸化被膜を生成させておく必要がある
。
このように構成された第2の実施例のプリント板21へ
の実装は、従来と同様に外部リード6との半田付けによ
り行なう。In FIG. 2, this PGA has an external lead 6
This is a full-grid PGA in which a cavity 3 is provided in the center of the ceramic substrate 1 on the side opposite to the mounting surface of the external leads 6, and a bonding conductor 4 is extended toward the outside of the substrate from the periphery of the cavity 3. and is connected to the external lead 6. Then, the IC chip 2 is fixed on the ceramic substrate 1 in the cavity 3, and the chip pad and the bonding conductor 4 are connected by wires 4A. Further, a metal cap 8 is placed on the metal seal ring 7, and the seal ring and the outer periphery of the cap are electrically resistance welded to seal the cap. Therefore, a package capable of high-density mounting with a large number of pins in a minimum area is completed. Next, the heat sink 11A is fixed with solder or resin to the surfaces of the ceramic substrate 1 and the metal cap 8 that constitute the package. Similarly, on the bottom and side surfaces of the ceramic substrate 1,
A concave heat sink 11B having a through hole is fixed by a fitting method or the like. In particular, in order to insulate the external leads 6 and the through holes 10, this heat sink 11B is made by impregnating the entire heat sink with molten aluminum to adhere aluminum to the metal surface, and then performing alumite treatment to form an oxide film of about 10 μm. It needs to be generated. The thus constructed second embodiment is mounted on the printed circuit board 21 by soldering to the external leads 6 in the same manner as in the prior art.
【0016】図3は本発明の第3の実施例の断面図であ
り、フラットパッケージを構成するCu−W合金のチッ
プ搭載板17A上にヒートシンク11Cを半田接着した
ものである。本第3の実施例においても第1の実施例と
同様に、熱抵抗及び軽量化の改善を行うことができる。FIG. 3 is a sectional view of a third embodiment of the present invention, in which a heat sink 11C is soldered onto a Cu--W alloy chip mounting plate 17A constituting a flat package. In the third embodiment, as in the first embodiment, improvements in thermal resistance and weight reduction can be made.
【0017】[0017]
【発明の効果】以上説明したように本発明は、海綿状の
金属骨格を有するヒートシンクを用いることにより、放
熱性がよくかつ軽量化された半導体装置が得られるとい
う効果を有する。As described above, the present invention has the advantage that by using a heat sink having a spongy metal skeleton, a semiconductor device with good heat dissipation and reduced weight can be obtained.
【図1】本発明の第1の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
【図2】本発明の第2の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
【図3】本発明の第3の実施例の断面図である。FIG. 3 is a sectional view of a third embodiment of the invention.
【図4】従来の半導体装置の断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor device.
【図5】従来の半導体装置の断面図である。FIG. 5 is a cross-sectional view of a conventional semiconductor device.
【図6】従来の半導体装置の断面図である。FIG. 6 is a cross-sectional view of a conventional semiconductor device.
1 セラミック基板
2 ICチップ
3 キャビティ
4 ボンディング導体
4A ワイヤー
5 内部導体
6 外部リード
6A ストッパー
7 シールリング
8 金属製キャップ
10 貫通孔
11,11A〜11C ヒートシンク12
シリコン樹脂
13,13A 半田
15 キャップ
16,16A,16B ヒートシンク17,17
A チップ搭載板
19,19A ロウ材1 Ceramic substrate 2 IC chip 3 Cavity 4 Bonding conductor 4A Wire 5 Internal conductor 6 External lead 6A Stopper 7 Seal ring 8 Metal cap 10 Through holes 11, 11A to 11C Heat sink 12
Silicon resin 13, 13A Solder 15 Cap 16, 16A, 16B Heat sink 17, 17
A Chip mounting plate 19, 19A Brazing material
Claims (1)
、このキャビティ内に搭載された半導体チップと、前記
セラミック基板の底面または周辺部に設けられた外部リ
ードと、前記セラミック基板表面の少くとも一部に固着
された海綿状の金属骨格を有するヒートシンクとを含む
ことを特徴とする半導体装置。1. A ceramic substrate having a cavity, a semiconductor chip mounted in the cavity, an external lead provided on the bottom or peripheral part of the ceramic substrate, and fixed to at least a part of the surface of the ceramic substrate. and a heat sink having a spongy metal skeleton.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2249991A JPH04262562A (en) | 1991-02-18 | 1991-02-18 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2249991A JPH04262562A (en) | 1991-02-18 | 1991-02-18 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04262562A true JPH04262562A (en) | 1992-09-17 |
Family
ID=12084439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2249991A Pending JPH04262562A (en) | 1991-02-18 | 1991-02-18 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04262562A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6046498A (en) * | 1997-06-30 | 2000-04-04 | Nec Corporation | Device having a heat sink for cooling an integrated circuit |
CN102254882A (en) * | 2010-05-20 | 2011-11-23 | 株式会社电装 | Electric power converter |
JP2017511609A (en) * | 2014-04-18 | 2017-04-20 | レイセオン カンパニー | Method for aligning surface mount packages for thermal improvement |
-
1991
- 1991-02-18 JP JP2249991A patent/JPH04262562A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6046498A (en) * | 1997-06-30 | 2000-04-04 | Nec Corporation | Device having a heat sink for cooling an integrated circuit |
US6251709B1 (en) | 1997-06-30 | 2001-06-26 | Nec Corporation | Method of manufacturing a cooling structure of a multichip module |
CN102254882A (en) * | 2010-05-20 | 2011-11-23 | 株式会社电装 | Electric power converter |
JP2017511609A (en) * | 2014-04-18 | 2017-04-20 | レイセオン カンパニー | Method for aligning surface mount packages for thermal improvement |
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