JPH0426135A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JPH0426135A JPH0426135A JP2131763A JP13176390A JPH0426135A JP H0426135 A JPH0426135 A JP H0426135A JP 2131763 A JP2131763 A JP 2131763A JP 13176390 A JP13176390 A JP 13176390A JP H0426135 A JPH0426135 A JP H0426135A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- particles
- resin
- coated
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 12
- 239000002245 particle Substances 0.000 claims abstract description 14
- 229910052582 BN Inorganic materials 0.000 claims abstract description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims abstract description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 3
- 239000010419 fine particle Substances 0.000 claims abstract description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 3
- 239000011859 microparticle Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 abstract description 17
- 229920005989 resin Polymers 0.000 abstract description 17
- 239000004020 conductor Substances 0.000 abstract description 5
- 230000017525 heat dissipation Effects 0.000 abstract description 5
- 230000035882 stress Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Supply And Installment Of Electrical Components (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はコンピューター等の電子機器に、使用する半導
体素子を基板にアセンブリーする実装技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a mounting technique for assembling semiconductor elements used in electronic equipment such as computers onto a substrate.
従来の技術
近年、半導体製造技術の進展に伴い、ＬＳＩの高集積化
が進み、電子機器の小型・軽量化は一段と進んでいる。BACKGROUND OF THE INVENTION In recent years, as semiconductor manufacturing technology has progressed, LSIs have become more highly integrated, and electronic devices have become smaller and lighter.
これらの軽薄短小化に伴い半導体素子もパッケージ品か
らフィルムキャリアによる半導体チップ実装が用いられ
るようになり、さらには実装密度を上げるためチップを
直に実装するようにもなった。As semiconductor devices have become lighter, thinner, shorter, and smaller, semiconductor chips have shifted from packaged products to semiconductor chip mounting using film carriers, and even directly mounting chips to increase packaging density.
半導体素子を面に実装する時、チップを上に向けて基板
に固定し金線でチップと基板を結んで後チップを樹脂で
モールドする方法とチップ」−のパッドに半田等でバン
ブを形成しチップを下に向けて基板に実装しその後樹脂
でモールドする方法がある。前者の方法では実装密度が
上げられないなどの理由により後者の方法に変わりつつ
ある。When mounting a semiconductor element on a surface, there is a method of fixing the chip to the substrate with the chip facing upward, connecting the chip and the substrate with gold wire, and then molding the chip with resin, and forming bumps on the pads of the chip with solder etc. There is a method of mounting the chip on a board with the chip facing down and then molding it with resin. Due to reasons such as the inability to increase packaging density with the former method, the latter method is being replaced.
発明が解決しようとする課題
第５図は半導体チップ１１を下に向けて基板１６に実装
した例を示すものである。この場合チップより発生する
熱はチップ背面より逃がすはかなく放熱器を取り付ける
などの放熱の処理で実装密度が上がらないし、モールド
する樹脂１４にもストレスがかかるなどの問題がある。Problems to be Solved by the Invention FIG. 5 shows an example in which a semiconductor chip 11 is mounted on a substrate 16 with the semiconductor chip 11 facing downward. In this case, the heat generated by the chip cannot be dissipated from the rear surface of the chip, and mounting density cannot be increased due to heat dissipation processing such as attaching a heat sink, and there are problems such as stress being applied to the resin 14 used for molding.
また第６図のように基板１６との間を樹脂１４で充填し
た場合は樹脂１４の熱伝導性が悪いこととチップ１１と
樹脂１４の熱膨張率の違いによりチップ１１にストレス
がかかりチップ表面の素子破壊を起こす。以上のことに
より従来の方法では熱放散に間層がある。In addition, when the space between the substrate 16 and the resin 14 is filled as shown in FIG. 6, stress is applied to the chip 11 due to the poor thermal conductivity of the resin 14 and the difference in thermal expansion coefficient between the chip 11 and the resin 14, resulting in stress on the chip surface. causing element destruction. Due to the above, in the conventional method, there is an interlayer in heat dissipation.
課題を解決するための手段
本発明は半導体チップを下に向けて基板に実装するとき
にチップと基板との隙間に熱伝導性のよい粒子を充填し
周囲を樹脂モールドするものである。Means for Solving the Problems In the present invention, when a semiconductor chip is mounted on a substrate facing downward, particles with good thermal conductivity are filled into the gap between the chip and the substrate, and the surrounding area is molded with resin.
作用
本発明によればチップと基板との隙間に熱伝導性のよい
粒子を充填することでチップの熱放散を基板側にも行い
放熱の効率を高くすることができる。また粒子は比較的
固定されていないのでチップ表面への影響は小さい。そ
れによって素子−・の物理的なストレスは小さくなる。According to the present invention, by filling the gap between the chip and the substrate with particles having good thermal conductivity, heat dissipation from the chip can also be performed on the substrate side, thereby increasing the efficiency of heat dissipation. Also, since the particles are relatively unfixed, the effect on the chip surface is small. This reduces the physical stress on the element.
実施例 以下、本発明の実施例について図面を用いて説明する。Example Embodiments of the present invention will be described below with reference to the drawings.
第１図はチップ１を基板表面の導体２と接続した時の断
面図である。本実施例では導体２を銅、チップ１のバン
ブ３を半田メツキ法で形成しているとして進めるが、導
体２は銅以外でもよく、またバンブ３においてもメツキ
による金バンプなとでもよい。本実施例では次に第２図
のように一つの辺を残して３辺に樹脂４をコーティング
する。FIG. 1 is a cross-sectional view when the chip 1 is connected to the conductor 2 on the surface of the substrate. In this embodiment, the conductor 2 is made of copper and the bumps 3 of the chip 1 are formed by solder plating, but the conductor 2 may be made of other materials than copper, and the bumps 3 may also be made of gold bumps by plating. In this embodiment, next, as shown in FIG. 2, three sides except one are coated with resin 4.
この時はチップ１の周囲だけ樹脂４がコーティングされ
るようにし、隙間に進入しないようにする。次に第３図
のように基板６を少し傾け、先はど樹脂４をコーティン
グしなかった一辺より粒子５を隙間に充填していく。こ
の粒子５は熱伝導性のよいシリコンカーバイドや窒化ホ
ウ素、酸化アルミや窒化アルミの微小粒子を用いている
。基板６とチップ１の隙間が１０〜３０μｍで、バンブ
３どうしの距離が３０〜１００μｍなので微小粒子の大
きさは２〜６μｍがよい。次に第４図のようにチップ１
の残った一辺を樹脂コーティングして粒子５を封入し、
チップの樹脂モールドを終える。At this time, the resin 4 is coated only around the chip 1 to prevent it from entering the gap. Next, as shown in FIG. 3, the substrate 6 is slightly tilted, and the particles 5 are filled into the gap from one side that was not previously coated with the resin 4. The particles 5 are made of fine particles of silicon carbide, boron nitride, aluminum oxide, or aluminum nitride, which have good thermal conductivity. Since the gap between the substrate 6 and the chip 1 is 10 to 30 μm, and the distance between the bumps 3 is 30 to 100 μm, the size of the microparticles is preferably 2 to 6 μm. Next, chip 1 as shown in Figure 4.
The remaining side of is coated with resin to encapsulate particles 5,
Finish the resin mold of the chip.
発明の効果
以」−のようにチップと基板との隙間に熱伝導性の高い
粒子を充填することで、チップから熱を基板側に逃がす
ことでチップ背面に放熱器を取り付けるなどの処置を行
わなくてもよいようになり、より高密度な実装を行うこ
とができ、放熱器が必要でなくなるのでコストをさげら
れる。また粒子とチップは接触しているだけなのでチッ
プ表面の素子への熱ストレスは小さいので従来どうり素
子の信頼性は確保される。Effects of the Invention'' - By filling the gap between the chip and the substrate with highly thermally conductive particles, heat can be released from the chip to the substrate, allowing measures such as attaching a heat sink to the back of the chip. This eliminates the need for heatsinks, allows for higher-density packaging, and eliminates the need for heatsinks, reducing costs. Furthermore, since the particles and the chip are only in contact with each other, the thermal stress on the element on the chip surface is small, so the reliability of the element is ensured as before.
第１図は本発明の一実施例による半導体素子の実装方法
を用いた各工程におけるプリント基板の便面図、第２図
は同」−面図、第３図および第４図は同側面図、第５図
および第６図は従来の実装方法におけるプリント基板の
側面図である。
１・・・・・・半導体チップ、２・・・・・・基板導体
、３・・・・・デツプのバンブ、４・・・・・・コーテ
ィング樹脂、５・・・・・・粒子、
６・・・・・・基板、
７・・・・・・放熱器。FIG. 1 is a schematic view of a printed circuit board in each process using a semiconductor device mounting method according to an embodiment of the present invention, FIG. 2 is a side view of the same, and FIGS. 3 and 4 are side views of the same. , FIG. 5, and FIG. 6 are side views of a printed circuit board in a conventional mounting method. DESCRIPTION OF SYMBOLS 1...Semiconductor chip, 2...Substrate conductor, 3...Dep bump, 4...Coating resin, 5...Particles, 6 ... Board, 7 ... Heatsink.
Claims (3)
充填することを特徴とする半導体素子の実装方法。(1) A method for mounting a semiconductor element, characterized by filling particles of a material with good thermal conductivity between the chip and the substrate.
バイド、窒化ホウ素、酸化アルミ、窒化アルミの微小粒
子で行うことを特徴とした請求項１記載の半導体素子の
実装方法。(2) The semiconductor device mounting method according to claim 1, wherein the material filled between the chip and the substrate is made of fine particles of silicon carbide, boron nitride, aluminum oxide, or aluminum nitride.
する請求項１記載の半導体素子の実装方法。(3) The semiconductor device mounting method according to claim 1, wherein the diameter of the microparticles is 2 to 6 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2131763A JP2830375B2 (en) | 1990-05-22 | 1990-05-22 | Semiconductor element mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2131763A JP2830375B2 (en) | 1990-05-22 | 1990-05-22 | Semiconductor element mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0426135A true JPH0426135A (en) | 1992-01-29 |
| JP2830375B2 JP2830375B2 (en) | 1998-12-02 |
Family
ID=15065602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2131763A Expired - Fee Related JP2830375B2 (en) | 1990-05-22 | 1990-05-22 | Semiconductor element mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2830375B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6376918B1 (en) * | 1996-03-07 | 2002-04-23 | Micron Technology, Inc. | Underfill of a bumped or raised die utilizing a barrier adjacent to the side wall of slip chip |
-
1990
- 1990-05-22 JP JP2131763A patent/JP2830375B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6376918B1 (en) * | 1996-03-07 | 2002-04-23 | Micron Technology, Inc. | Underfill of a bumped or raised die utilizing a barrier adjacent to the side wall of slip chip |
| US6455933B1 (en) | 1996-03-07 | 2002-09-24 | Micron Technology, Inc. | Underfill of a bumped or raised die utilizing a barrier adjacent to the side wall of flip chip |
| US6815817B2 (en) | 1996-03-07 | 2004-11-09 | Micron Technology, Inc. | Underfill of a bumped or raised die utilizing barrier adjacent to the side wall of a flip-chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2830375B2 (en) | 1998-12-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |