JPH04261067A - How to manufacture solar cells - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a solar cell, and more particularly to a method of manufacturing a solar cell in which a pn junction of the solar cell is formed by solid phase growth.

0002

2. Description of the Related Art Solar cells using polycrystalline silicon are known. Polycrystalline silicon has the advantage of being easier to grow in area and cheaper than single crystal silicon, and is very promising as a semiconductor substrate for solar cells.

[0003] Generally, as a method for forming a pn junction on a silicon polycrystalline substrate, CVD is used on an n-type silicon substrate.
Methods used include epitaxially growing a p-type silicon layer using a method, or forming a p-type diffusion layer on an n-type silicon substrate using a diffusion method.

0004

[Problem to be solved by the invention] However, CVD
The method of epitaxially growing a silicon layer using the plasma CVD method requires high temperatures and there are restrictions on the substrates that can be used.
Although this method allows low-temperature growth, it has the disadvantage that the film quality deteriorates (device characteristics deteriorate) because it is then subjected to high-temperature heat treatment. Further, the diffusion method has the disadvantage that it is difficult to form a diffusion layer with a high concentration of 1020 cm-3 or more, and that the diffusion depth becomes deeper when the concentration is increased, and the controllability of the formation of the diffusion layer is low.

Accordingly, an object of the present invention is to provide a method for forming a shallow high-concentration pn junction at a low temperature, thereby providing a high-quality solar cell.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a substrate having at least a first conductivity type silicon crystal layer, and a second conductivity type silicon crystal layer having a conductivity type opposite to the first conductivity type. Manufacture of a solar cell, characterized in that an amorphous silicon layer of a second conductivity type is deposited, and the amorphous silicon layer of a second conductivity type is heat-treated to convert it into a crystalline silicon layer of a second conductivity type, thereby forming a pn junction. provide a method.

Briefly stated, the present invention provides p
This is a method for manufacturing a solar cell characterized by forming an n-junction. Since it is possible to form a conductive crystal layer with a high concentration layer at a low temperature using the solid phase growth method, the present inventors formed a p-n junction using the solid phase growth method to create a material of a quality that can be used as a solar cell. As a result of examining whether or not this could be obtained, it was discovered that it was possible to form a pn junction that could be sufficiently put to practical use as a solar cell, and the present invention was completed.

[0008] At least the surface of the substrate is made of a first conductivity type silicon crystal layer. The first conductivity type silicon crystal layer may be the substrate itself, or may be a layer grown on the surface of the substrate. In the low-temperature plasma CVD method, there is a large difference in film quality depending on the plane orientation of the substrate, but in the solid phase growth method, there is no such restriction.

The first conductivity type silicon crystal layer on the substrate surface is 1
n- type or p- type with a dopant concentration of about 017 to 1015/cm3 and a resistivity of about 0.1 to 10 Ωcm.
Let it be the crystal layer of the mold. It is highly desirable to perform a cleaning treatment on the surface of the substrate before depositing the amorphous silicon layer in order to form a high quality pn junction by solid phase growth. Specifically, after organic cleaning, a clean substrate surface is exposed by etching with an alkaline solution or mixed acid. In addition, in-situ plasma etching is also possible.

[0010] First, an amorphous silicon layer of a second conductivity type, which is a conductivity type opposite to the first conductivity type, is deposited on the substrate whose surface is made of a first conductivity type silicon crystal layer. The general conditions for this deposition are as follows. Silicon source: SiH4 Dopant (p type): B2H6 Dopant (n type): PH3 Dopant concentration: 0.1 to 3% Gas flow rate: 10 to 50 SCCM Substrate temperature: 150°C to 350°C Pressure: 200mTorr Plasma RF power: 10 ~20W Film thickness: 100~2000 Å or more According to this deposition method, a highly doped amorphous silicon layer can be formed to a desired thickness at a low temperature.

Next, the deposited amorphous silicon layer is heat treated to crystallize it. This heat treatment is used in the case of depositing a crystalline silicon layer by thermal CVD method etc. (generally 900 ~
(1100℃), and typically 600 to 70℃ depending on the quality of the amorphous silicon layer.
0°C is sufficient. If the temperature is lower than 500° C., it is difficult to obtain good crystals, while if the temperature is higher than that, epitaxial growth will not occur due to random crystal nucleation, resulting in polycrystals with small grain sizes. The heat treatment atmosphere may be an inert atmosphere, such as argon.

[0012] Through this heat treatment, the amorphous silicon layer is crystallized and a pn junction is formed. According to this method, a pn junction can be formed at a low temperature, so the quality of the semiconductor film or layer is not degraded. Furthermore, since the temperature is low, the dopant does not diffuse deeply into the substrate. The thickness of the crystallized silicon layer can be as thin as 200 Å. In the conventional thermal diffusion method, when trying to diffuse to a high concentration, it reaches at least about 5000 Å.
In the present invention, the thickness can be reduced regardless of the dopant concentration. However, if the thickness is made thinner than 100 Å, both the open circuit voltage and the short circuit photocurrent will decrease, and the conversion efficiency of the solar cell will decrease. The dopant concentration of the crystallized silicon layer can easily be at least about 1021 cm-3. Therefore, a pn junction having a shallow and steep concentration gradient can be obtained. What is important is that the pn junction formed by this solid phase growth method can be used as a solar cell for practical use as long as the pretreatment of the substrate is sufficiently controlled. As a result, it is possible to obtain a solar cell having a higher concentration and a shallower p-n junction than before and without deterioration in crystal quality, which also contributes to improving the characteristics of the solar cell, such as increasing the surface current.

[0013] Formation of electrodes and the like other than the formation of the pn junction can be carried out in the same manner as in ordinary solar cells.

[0014]

[Operation] Since a conductive layer of an opposite conductivity type is formed on a substrate of one conductivity type by solid phase growth, a high concentration and shallow pn junction can be formed. Furthermore, since the process is performed at a low temperature, the crystal quality of the substrate etc. will not be degraded.

[0015]

EXAMPLE A growth apparatus as shown in FIG. 1 was used. In the figure, 1 is a silicon substrate, 2 is a substrate holder and RF electrode, and 3 is a silicon substrate.
4 is a heater, 4 is a gas nozzle, 5 is an RF electrode, 6 is a gas introduction tube, 7 is a plasma generation region, and 8 is a vacuum chamber.

Referring to FIG. 2, (100) or (1
11) Cz Single crystal silicon (resistivity 2 to 6 Ωcm) or cast polycrystalline silicon is used, and after alkali etching, pretreatment for film formation includes ultrasonic organic cleaning with acetone, pure water cleaning, and oxide film removal with hydrofluoric acid. A pure water rinse and a dry nitrogen blow were performed.

This substrate 11 was mounted in a growth apparatus, and an amorphous silicon layer 12 was deposited under the following conditions. Source gas: SiH4 gas containing 1% PH3 Gas flow rate: 25SCCM Substrate temperature: 170°C Pressure: 200mToor Power: 10W Film thickness: 250Å

Next, the substrate 11 on which the amorphous silicon layer 12 was deposited was heated in an image furnace at a rate of 120° C./min, held at 600° C. for 5 minutes, and then slowly cooled. As for the characteristics of the obtained crystallized film, the crystal structure was observed by ultraviolet surface reflection and R-HEED (reflection type high energy electron diffraction), and the electrical properties were observed by Hall effect measurement and spreading resistance measurement.

As a result, the carrier concentration was 10-21 cm
It was found that a crystalline silicon film with a resistivity of -1 and a resistivity of about 10 -4 Ωcm was obtained.

Next, the solar cell will be explained with reference to FIG. 3. It was prepared as follows. In FIG. 3, 21 is a transparent electrode;
22 is a comb-shaped front electrode, 23 is an n+ type crystalline silicon layer, 24 is a p− type silicon crystal substrate, and 25 is a back electrode. The characteristics of the solar cell were measured using AM1.5, with an open circuit voltage of 0.56V and a short circuit photocurrent of 32m on a single crystal substrate.
The 28 mA/cm2 conversion efficiency on the A/cm2 polycrystalline substrate was 14% and 12.5%, respectively.

[0021]

According to the present invention, a solar cell having a high carrier concentration, a shallow pn junction, and excellent film quality can be obtained using a low temperature process.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a CVD deposition apparatus for an amorphous silicon layer.

FIG. 2 is a schematic cross-sectional view showing the formation of a pn junction in an example.

FIG. 3 is a schematic diagram of a solar cell of an example.

[Explanation of symbols]

1... Substrate 2... Substrate holder and RF electrode 3... Heater 4... Gas nozzle 5... RF electrode 6... Gas introduction tube 7... Plasma generation region 8... Vacuum chamber 11... P- type silicon crystal substrate 12... N+ type amorphous silicon layer

21... Transparent electrode 22... Comb-shaped front electrode 23... N+ type crystalline silicon layer 24... P- type silicon crystal substrate 25... Back electrode

Claims (1)

[Claims] 1. An amorphous silicon layer of a second conductivity type, which is a conductivity type opposite to the first conductivity type, is deposited on a substrate having at least a surface of a first conductivity type silicon crystal layer, 1. A method of manufacturing a solar cell, comprising heat-treating a silicon layer to convert it into a crystalline silicon layer of a second conductivity type, thereby forming a pn junction.