JPH04259869A - Test evaluation equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a test and evaluation device.
In particular, the present invention relates to a test evaluation apparatus that tests whether the output of a semiconductor integrated circuit such as a logic circuit is output within a predetermined allowable timing range to determine the operation of the circuit under test. 2. Description of the Related Art In recent years, semiconductor integrated circuits (for example, logic circuits) have become multi-functional and more complex, and as a result, the timing of output from semiconductor integrated circuits has become different for each semiconductor integrated circuit. Therefore, even if the output of the semiconductor integrated circuit is output within the allowable timing range, if the output timing deviates from the determination timing, the determination will be incorrect. Therefore, there is a need for a test and evaluation device that can reliably determine that the output of a semiconductor integrated circuit is good if it is within the allowable timing range.

0002

[Prior Art] Conventionally, even if the output of the circuit under test is within the allowable timing range, if the output timing deviates from the judgment timing, it will be determined as defective. When the data output timing varies within a given time range, the judgment results are not reproducible with a single edge strobe.

[0003] Therefore, if the data output timing from the circuit under test varies within the allowable range, in order to judge the product as non-defective using the edge strobe, measurements are performed multiple times while shifting the judgment points, and as a result, even one part is found to be non-defective. A method is used in which if there are points, the product is judged to be of good quality as an overall judgment. FIG. 8 is a block diagram showing an example of a conventional test evaluation device. As shown in the figure, the conventional test evaluation device includes a comparator 102, a logic comparator 103, a timing generator 104, a pattern generator 105, and a comparison voltage generation circuit 10.
It is equipped with 7.

The comparator 102 receives the output signal of the circuit under test 101, comparison voltages (H, L) from the comparison voltage generation circuit 107, and strobe signals a~ from the timing generator 104, which are timing signals for judgment extraction. c is supplied. Also, the output of the comparator 102 is the output of the logic comparator 103.
and the judgment result (PASS/FAIL judgment)
is now output. That is, in the logic comparator 103, the pattern generator 1
The output of the comparator 102 is compared with the expected value data from 05 and the strobe signals a to c from the timing generator 104.
It is designed to determine whether it is good or bad. Here, although the output timing of the circuit under test 101 is slightly different for each circuit,
1 is output within the allowable timing range, the circuit under test 101 is determined to be good. In other words, the output of the circuit under test 101 can be output at any position (timing) within the allowable timing range.
But that's fine.

[0005]

FIG. 9 is a diagram for explaining the operation of the test and evaluation apparatus shown in FIG. 8. As shown in the figure, in order to confirm that the output of the circuit under test 101 is output at any position within the permissible timing range, strobe signals a to c are applied to multiple positions within the permissible timing range. need to occur.

Specifically, in the case of FIG. 9, the output of the circuit under test 101 becomes output ((
(high level), strobe signals a and c
At the position, the output of the circuit under test 101 is determined to be low level and defective, and only at the position of the strobe signal b, the high level output of the circuit under test 101 is determined to be high level and good. In this way, in the conventional test evaluation device, even if the output of the circuit under test 101 is output at any position within the permissible timing range, it is necessary to detect it and determine that it is acceptable. Strobe signals had to be generated at multiple locations within the device.

[0007]Also, it is possible to judge the circuit under test by taking in the output of a wind strobe during an arbitrary period, but this means that if there is an edge during an arbitrary period, it will be judged as defective. Even if the output of the target circuit is within the allowable timing range, it cannot be reliably determined to be good. In this way, with conventional test and evaluation equipment, the burden of creating software and
The increase in measurement time required to repeat the determination multiple times has been a major obstacle to improving efficiency.

[0008] In view of the above-mentioned problems with the conventional test and evaluation apparatus, an object of the present invention is to reliably judge the circuit as good in a short time when the output of the circuit under test is within the permissible timing range. shall be.

[0009]

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of a test and evaluation apparatus according to the present invention. According to the present invention, the output of the circuit under test 1 is within the allowable timing range (wt
1 to wt2) to determine the operation of the circuit under test 1, the output level of the circuit under test 1 is determined by determining whether the output level of the circuit under test 1 is output within the start position (wt1 to wt2) of the permissible timing range. ), an edge detection holding means 62 for detecting whether the output of the circuit under test 1 has an edge within the permissible timing range and holding the level; The apparatus further comprises an output synthesis means 63 for synthesizing the output of the level capture means 61 and the output of the edge detection holding means 62, and the operation of the circuit under test 1 is determined based on the output level of the output synthesis means 63. A test evaluation device is provided which is characterized by the following.

0010

According to the test and evaluation apparatus of the present invention, the output level capturing means 61 captures the output level of the circuit under test 1 at the starting position of the allowable timing range. Further, the edge detection and holding means 62 detects whether the output of the circuit under test 1 has an edge within the permissible timing range, and detects whether the output of the circuit under test 1 has an edge within the permissible timing range. If so, that level is maintained. Further, the output combining means 63 combines the output of the output level capturing means 61 and the output of the edge detection holding means 62. The operation of the circuit under test 1 is determined based on the output level of the output synthesizing means 63.

As described above, according to the test evaluation device of the present invention, it is not necessary to generate strobe signals at multiple positions within the allowable timing range to make a determination, and the output of the circuit under test is within the allowable timing range. If it is, it can be reliably determined to be good in a short time.

0012

Embodiments Hereinafter, embodiments of the test and evaluation apparatus according to the present invention will be described with reference to the drawings. FIG. 2 is a block circuit diagram showing an embodiment of the test and evaluation apparatus of the present invention. As shown in the figure, the test evaluation device of this embodiment has a comparator 2
, a logic comparator 3, a timing generator 4, a pattern generator 5, and an allowable range determination section 6. Here, comparator 2,
Logic comparator 3, timing generator 4
, and The pattern generator 5 has a configuration similar to that of the conventional test and evaluation device shown in FIG. Furthermore, the comparison voltage generation circuit 107 in FIG.
It is omitted here. The feature of this embodiment is shown in the allowable range determining section 6.

The permissible range determination unit 6 includes a latch circuit 61,
It includes a flip-flop (FF) circuit 62 and an OR gate 63. The comparator 2 is supplied with the output S1 of the circuit under test 1 and the determination reference level signal R, and the output S2 of the comparator 2 is supplied with the latch circuit 61 and the flip-flop circuit 62. Further, the output S3 of the latch circuit 61 and the output S4 of the flip-flop circuit 62 are supplied to an OR gate 63, and the output S5 of the OR gate 63 is supplied to the logic comparator 3, and the determination result (PASS/FAI
(judgment of L) is output. here,
The latch circuit 61 is supplied with an enable signal ES from the timing generator 4, and the flip-flop circuit 62 is supplied with an enable signal ES and a clear signal CS1 from the timing generator 4. Further, the logic comparator 3 is supplied with expected value data from the pattern generator 5 and strobe signal SS from the timing generator 4.

In the above, the enable signal ES is a signal for activating the latch circuit 61 and the flip-flop circuit 62 in the permissible range (permissible timing range) wt1 to wt2, and the clear signal CS1 is a signal for activating the latch circuit 61 and the flip-flop circuit 62 in the permissible range (permissible timing range) wt1 to wt2. Cycle start position (timing t1)
When the flip-flop circuit 62 is in the clear state (
This is a signal for setting the initial state. Furthermore, the strobe signal SS is a signal output at the end position wt2 of the allowable timing range.

The latch circuit 61 is configured to take in the level of the output S2 of the comparator 2 (output S1 of the circuit under test 1) at the starting position wt1 of the allowable timing range. Further, the flip-flop circuit 62 is
Output S2 of comparator 2 (output S1 of circuit under test 1
) has an edge within the allowable timing range wt1 to wt2, and that level is held. The OR gate 63 connects the output S3 of the latch circuit 61 and the flip-flop circuit 6.
It outputs the logical sum of the outputs S4 of 2. The output S5 of the OR gate 63 is supplied to the logic comparator 3, where it is logically compared at the end position wt2 of the allowable timing range by the strobe signal SS, and the operation of the circuit under test 1 is determined. That is, the operation of the circuit under test 1 is determined by testing whether the output of the circuit under test 1 is output within a predetermined allowable timing range.

FIGS. 3 and 4 are time charts for explaining the operation of the test and evaluation apparatus shown in FIG. 2, in which the output data from the circuit under test (sample) 1 is classified into six patterns A to F. It is something. In FIG. 3, in the case of pattern A, that is, when the output S1 from the sample is output (high level) throughout the allowable range (allowable timing range) wt1 to wt2, the output S2 of the comparator 2 is the output from the sample. S1 and the expected value (for example,
Judgment reference level R that is high in test period t1 to t2
) is matched, a high level is output. Since the latch circuit 61 takes in the output S2 of the comparator 2 at the starting position wt1 of the allowable range, the output S3 of the latch circuit 61 is maintained at a high level. Furthermore, the flip-flop circuit 62 has an allowable range wt1 to wt2.
However, since there is no edge, the output S4 of the flip-flop circuit 62 remains at the initial state (when cleared) at the low level. Further, in the OR gate 63, S3 of the latch circuit 61 and the flip-flop circuit 6
The outputs S4 of 2 are combined (ored). Then, the output S5 of the OR gate 63 is logically compared in the logic comparator 3 at the end position PSS(wt2) of the allowable range based on the strobe signal SS. As a result, the operation of the circuit under test 1 is determined to be OK. Note that the operation of this comparator 2 will be explained as positive logic.

Next, in the case of pattern B, the tolerance range wt
There is a changing point (edge) PB within 1 to wt2, but since this edge PB is a changing point from a high level to a low level, the operation is similar to that of pattern A, and the allowable range of the strobe signal SS in the logic comparator 3 is Based on the logic comparison at the end position PSS, it is determined that the operation of the circuit under test 1 is good.

Furthermore, in the case of pattern C, the latch circuit 61
is designed to take in the output S2 of the comparator 2 at the start position wt1 of the allowable range, so the output S3 of the latch circuit 61 remains at a low level. On the other hand, the flip-flop circuit 62 captures the change point (edge) PC from a low level to a high level within the allowable range and converts the output S of the flip-flop circuit 62 from the edge PC.
4 changes to a high level. Then, the output S5 of the OR gate 63 is sent to the logic comparator 3, at the end position PSS (wt2
) is compared logically, and a good judgment result is output.

Furthermore, in FIG. 4, in the case of pattern D, the flip-flop circuit 6 is
2 captures the transition point PD1 from low level to high level, but does not capture the transition point PD2 from low level to high level, so the output S4 of the flip-flop circuit 62 goes from edge PD1 to high level. As a result, the judgment is good. And for patterns E and F, the tolerance range w
Since there is no expected output between t1 and wt2 (S1 and S2 remain at low level), the output S3 of the latch circuit 61
The output S4 of the flip-flop circuit 62 remains at a low level, and the output S5 of the OR gate 63 also remains at a low level. As a result, the operation of test target circuit 1 is defective (NG).
It is determined that

FIG. 5 is a block circuit diagram showing another embodiment of the test and evaluation apparatus of the present invention. The test and evaluation device shown in FIG. 5 is the test and evaluation device shown in FIG.
It has one pair of latch circuits, one flip-flop circuit, and one pair of OR gates. That is, the test evaluation apparatus shown in FIG. 5 includes a pair of comparators 2a
, 2b, latch circuits 61a, 61b, flip-flop circuits 62a, 62b, and OR gate 63a,
63b. Here, in the test evaluation apparatus of FIG.
In this test evaluation device, the judgment reference level G supplied to the comparator 2a is a signal that becomes high in the test period t1 to t2, and the judgment reference level H supplied to the comparator 2b is a signal that becomes low in the test period t1 to t2. This is the signal that becomes the level. Thereby, the operation of the circuit under test 1 is determined by targeting the positive logic output or the negative logic output of the circuit under test 1 as necessary. That is, when a high level (G) is expected, the logic comparator 30 logically compares the output S5a of the OR gate 63a at the end position PSS of the allowable range of the strobe signal SS, and when a low level (H) is expected. In the logic comparator 30, the output S5b of the OR gate 63b is set to the end position PS of the allowable range of the strobe signal SS.
Logical comparison will be made using S.

Furthermore, in the test and evaluation apparatus shown in FIG. 5, the flip-flop circuits 62a and 62b have a tolerance range (
Allowable timing range) wt1 to wt2 starting position wt
1 and output to flip-flop circuits 62a, 62b.
and an operation start signal OS for starting the operation of the latch circuits 61a and 61b, which is output at the starting position t1 of the test period t1 to t2 and is output to the flip-flop circuits 62a and 62.
A first clear signal CS1 that initializes b is outputted at the end position wt2 of the allowable range, and is outputted to the flip-flop circuits 62a, 62b and the latch circuit 61a.
, 61b to the initial state (stopping the operation).
The latch circuits 61a and 61b are supplied with the operation start signal OS and the second clear signal CS2. Here, the first clear signal CS1 is the same as the clear signal CS1 in the test evaluation apparatus of FIG.
The clear signal CS2 is for performing the same operation as the enable signal ES in the test and evaluation apparatus shown in FIG. That is, the latch circuits 61a, 61b and the flip-flop circuits 62a, 62b are activated by the operation start signal OS and the second clear signal CS2.
A predetermined operation is performed only for a time corresponding to the allowable range wt1 to wt2.

As shown in FIGS. 6 and 7, which correspond to FIGS. 3 and 4 described above, when G is expected, in the case of pattern A', pattern B', pattern C', and pattern D', The operation of the circuit under test 1 is determined to be good (OK), and in the case of pattern E' and pattern F', the operation of the circuit under test 1 is determined to be defective (NG). In addition, if H is expected, pattern B', pattern C
', pattern D', pattern E' and pattern F'
In the case of pattern A', the operation of the circuit under test 1 is determined to be good (OK), and in the case of pattern A', the operation of the circuit under test 1 is determined to be defective (NG).

Therefore, in the test evaluation apparatus shown in FIG.
When expected, the output S5a of the OR gate 63a is logically compared in the logic comparator 30, and
When H is expected, the operation of the circuit under test 1 is determined based on the positive logic output or negative logic output of the circuit under test 1 by logically comparing the output S5b of the OR gate 63b in the logic comparator 30. is now possible.

As described above, according to the above-described embodiment of the test and evaluation apparatus of the present invention, sufficient evaluation is possible even if the output timing varies depending on the circuit to be tested, and a significant increase in efficiency can be achieved. . In addition, by using a large number of criteria with different judgment levels, it is possible to make judgments at a more detailed level, and it is also possible to efficiently test and evaluate the circuit under test in terms of timing accuracy and other test judgments. can.

[0025]

[Effects of the Invention] As detailed above, according to the test evaluation device of the present invention, if the output of the circuit under test is within the allowable timing range, it can be reliably determined to be good in a short time. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of a test evaluation device according to the present invention.

FIG. 2 is a block circuit diagram showing an embodiment of the test evaluation device of the present invention.

FIG. 3 is a time chart for explaining the operation of the test evaluation apparatus shown in FIG. 2;

FIG. 4 is a time chart for explaining the operation of the test evaluation apparatus shown in FIG. 2;

FIG. 5 is a block circuit diagram showing another embodiment of the test and evaluation device of the present invention.

FIG. 6 is a time chart for explaining the operation of the test evaluation apparatus shown in FIG. 5;

7 is a time chart for explaining the operation of the test evaluation apparatus shown in FIG. 5. FIG.

FIG. 8 is a block circuit diagram showing an example of a conventional test evaluation device.

FIG. 9 is a diagram for explaining the operation of the test evaluation device of FIG. 8;

[Explanation of symbols]

1...Circuit under test (sample) 2...Comparator 3...Logic comparator 4...Timing generator 5...Pattern generator 6...Tolerance range determination section 61...Output level capture means (latch circuit) 62...Edge detection holding means (flip-flop) circuit) 63...Output synthesis means (OR gate) CS1...Clear signal (first clear signal) CS2
…Second clear signal ES…Enable signal OS…Operation start signal SS…Strobe signal

Claims (7)

[Claims] 1. A test evaluation device that determines the operation of a circuit under test (1) by testing whether the output of the circuit under test is output within an allowable timing range (wt1 to wt2), comprising: output level capturing means (61) for capturing the output level of the circuit under test at a starting position (wt1) of the permissible timing range; and detecting whether the output of the circuit under test has an edge within the permissible timing range. an edge detection and holding means (62) for detecting and holding the level; and an output synthesis means (63) for synthesizing the output of the output level capturing means and the output of the edge detection and holding means; A test evaluation apparatus characterized in that the operation of the circuit under test is determined based on the output level of the means. 2. The output of the output synthesis means (63) is supplied to a logic comparator (3), and the logic comparator determines the operation of the circuit under test according to the output level of the output synthesis means at the end position of the allowable timing range. 2. The test evaluation device according to claim 1, wherein the test evaluation device is configured to determine. 3. The output level capturing means is composed of a latch circuit (61; 61a, 61b), and the edge detection and holding means is composed of a flip-flop circuit (62; 62a, 6
2b), and wherein the output synthesis means is composed of an OR gate (63; 63a, 63b). 4. The flip-flop circuit (62)
And the latch circuit (61) has a determination reference level (
4. The test evaluation device according to claim 3, wherein the output of the comparator (2) to which R) is supplied is supplied. 5. The flip-flop circuit (62)
A clear signal (CS1) is output at the start position (t1) of the test cycle (t1 to t2) and sets the flip-flop circuit to an initial state, and a clear signal (CS1) is output for the time corresponding to the permissible timing range (wt1 to wt2). A claim characterized in that an enable signal (ES) is supplied that puts the flip-flop circuit and the latch circuit (61) into an operating state, and the latch circuit is supplied with the enable signal (ES). Test and evaluation equipment in Section 4. 6. The flip-flop circuit (62a
, 62b), one pair each of the latch circuits (61a, 61b) and the OR gates (63a, 63b) are provided, and each of the flip-flop circuits and each latch circuit has a complementary judgment circuit. Comparators (2a, 2) supplied with reference levels (G, H)
4. The test evaluation apparatus according to claim 3, wherein the output of (b) is supplied, and the operation of the circuit under test is determined based on a positive logic output or a negative logic output of the circuit under test. 7. The flip-flop circuit (62a
, 62b) indicates the start position (
an operation start signal (OS) which is outputted at wt1) and starts the operation of the flip-flop circuit and the latch circuit (61a, 61b), a test period (t1 to t2);
a first clear signal (CS1) that is output at the start position (t1) of and puts the flip-flop circuit into an initial state;
And, the end position of the allowable timing range (wt2)
a second clear signal (CS2) that is output from and initializes the flip-flop circuit and the latch circuit;
is supplied to the latch circuit, and the operation start signal (OS) and the second clear signal (CS) are supplied to the latch circuit.
2) The test evaluation device according to claim 6, wherein: