JPH04258160A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a decreasee in capacity of a transistor due to an unnecessary additional resistor by disposing two MIS transistors in parallel, narrowing the interval between gate electrodes of a common drain side as compared with a predetermined value, and increasing the interval between the gate electrodes of a source side. CONSTITUTION:A semiconductor device containing a MIS transistor, and particularly that including a MOS transistor of an LDD structure is employed. The two transistors are disposed adjacently with a drain region. i.e., a common region having a low concentration N-type diffused layer 5 and a high concentration N-type diffused layer 6. Gate electrodes 4 has a trapezoidal section, and formed at its side vertically at the side of a source region. That is, the interval between the electrodes 4 of the side of common drain region is narrowed. Accordingly, one side is formed in a forward tapered state at the time of forming the gate electrodes, and a layer 5 can be formed only at the drain region. Thus, a decrease in capacity of the transistor due to the additional resistor of the layer 5 can be prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including an MIS transistor, and more particularly to a semiconductor device including an LDD structure MOS transistor.

0002

[Prior Art] LD as a transistor structure for suppressing deterioration of MOS transistors due to hot carriers
D-structure MOS transistors are common, but conventional LD
The D transistor has a structure having a sidewall oxide film 9 on the side surface of the gate electrode 4, as shown in FIG.

Next, a method of manufacturing a conventional LDD structure MOS transistor will be explained. For example, a field oxide film 2 is formed in an element isolation region on a P-type silicon substrate for element isolation using a known LOCOS technique.

After a gate oxide film 3 is grown by thermally oxidizing the surface of the P-type silicon substrate, a polycrystalline silicon film is deposited by the LPCVD method, and phosphorus is diffused to obtain a desired resistivity. Gate electrode 4 is formed by processing a polycrystalline silicon film into a desired pattern using lithography technology.

Thereafter, phosphorus is ion-implanted at a rate of 10 to the 13th power (hereinafter referred to as 1E13) per square centimeter to form a low concentration N-type diffusion layer 5. After growing a silicon oxide film on the entire surface, etching is performed using anisotropic etching to form a sidewall oxide film 9 on the side surface of the gate electrode, followed by arsenic ion implantation of about 1E15 per square cm to form a high concentration N. By forming the type diffusion layer 9, an LDD structure MOS transistor is manufactured.

[0006]

[Problem to be solved by the invention] The conventional LDD described above
In structural MOS transistors, the manufacturing process such as forming sidewall oxide films and recovering from etching damage is somewhat complicated, and a low concentration N-type diffusion layer is also formed in the source region of the transistor as well as in the drain region. However, there has been a problem in that the additional resistance of this lightly doped N-type diffusion layer unnecessarily lowers the performance of the transistor.

[0007]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
Two semiconductor substrates are arranged adjacent to each other sharing a drain region.
each of the gate electrodes of the two MIS transistors has a trapezoidal cross section in which the interval between the gate electrodes increases in accordance with the distance from the gate insulating film, and the side surface is perpendicular to the source side; The drain region has a low concentration impurity diffusion layer under each of the gate electrodes, and the source region of each of the two MIS transistors has a high concentration impurity diffusion layer.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view of a MOS transistor in one embodiment of the present invention.

Two MOS transistors share a common drain region (having a low concentration N type diffusion layer 5 and a high concentration N type diffusion layer 6) and are arranged adjacent to each other. Gate electrode 4
has a trapezoidal cross section, but the side surfaces are vertical on the source region side. The source region does not have a lightly doped N-type diffusion layer.

Next, the manufacturing method of this embodiment will be explained.

First, as shown in FIG. 3, a field oxide film 2 for device isolation is formed in a device isolation region by thermal oxidation to a thickness of about 600 nm on a P-type silicon substrate 1 using the well-known LOCOS technique. Thereafter, ion implantation is performed to adjust the threshold voltage Vt, and a gate oxide film 3 of about 15 nm is grown in the element region by thermal oxidation.

Next, as shown in FIG.
After growing a polycrystalline silicon film 10 of about 0 nm and performing phosphorus diffusion so that the resistivity becomes about 15 Ω, a silicon oxide film 11 of about 300 nm is deposited by CVD. A photoresist film having a thickness of 1 to 1.5 μm is applied to the entire surface and exposed using a mask to shape the photoresist film into a desired pattern. At this time, a mask is prepared in advance so that the distance between the photoresist films 12 is approximately 1 μm or less in the drain region of the transistor.

Next, as shown in FIG. 5, if plasma etching of the silicon oxide film and plasma etching of the polycrystalline silicon film are continued in this state, the portion that will form the drain region of the transistor (sandwiched between the photoresist films 12) is removed. Because the aspect ratio of the region to be etched is large (1 to 2), the etching rate is slow compared to other regions, and the shape after etching is a forward taper shape only in narrowly spaced regions, and the cross-sectional shape is A shaped gate electrode 4 is formed.

In this state, phosphorus is heated at 30 keV to a square cm
Approximately 1E13 per square cm of arsenic at 30keV
When ions are implanted at about E15, the projected range Rp of ion implantation of phosphorus is about 40 nm, whereas the Rp of arsenic is only about 20 nm. Phosphorus enters into the layer to form a low concentration N-type diffusion layer 5 and a high concentration N-type diffusion layer 6. The source region is only a heavily doped N-type diffusion layer. Next, as shown in FIG. 6, a silicon oxide film 4 of about 400 nm is deposited as an interlayer insulating film on the entire surface, and as shown in FIG. 1, contact holes are formed using photolithography technology to form aluminum electrodes 8. A transistor is manufactured by the following steps.

As shown in FIG. 4, the reason why the silicon oxide film 11 is grown on the polycrystalline silicon film 10 is to make the gap between the gate electrodes sandwiching the drain region as narrow as about 1 μm or less. This is to increase the aspect ratio of the area to slow down the etching rate in this region, and to use the known self-align contact technique.

FIG. 7 is a sectional view showing an example of application of the present invention. When a transistor with a large channel width is required, it is common practice to arrange multiple transistors with small channel widths in parallel, but in this case as well, the gate spacing in the drain region is approximately 1 μm or less, and the gate spacing in the source region is approximately 2 μm. With the above configuration, by forming the gate electrode into a forward tapered shape only on the drain region side, a low concentration impurity diffusion layer can be formed only in the drain region.

The manufacturing method is almost the same as described above. However, a first insulating film 14 is deposited instead of the insulating film 7, a contact hole is formed, the first wiring layer 1 is formed, and a second insulating film 16 is deposited thereon. The difference is that a contact hole is formed and a second wiring layer 17 is formed. This is because two-stage contacts were formed to prevent the electrode wiring from becoming easily disconnected due to the large aspect ratio of the contact hole on the drain region.

In the above embodiment, two types of atoms, arsenic and phosphorus, are implanted to form a low concentration N-type diffusion layer, thereby softening the impurity concentration gradient in the drain region. Even by implanting approximately 1E15 per portion, the amount of arsenic penetrating the forward tapered gate polysilicon in the drain region decreases as it approaches the center of the gate electrode, making it possible to moderate the impurity concentration profile.

[0020]

[Effects of the Invention] As explained above, the present invention provides two MI
By arranging S transistors in parallel and making the spacing between the gate electrodes on the common drain side narrower than a predetermined value and widening the spacing between the gate electrodes on the source side, only the gate electrode on the drain side is etched using the difference in etching speed. The diffusion layer has a trapezoidal cross section with a forward taper, and a simple manufacturing process allows the diffusion layer to have a gentle concentration gradient only on the drain side. Therefore, since there is no low concentration impurity diffusion layer in the source region, it is possible to prevent the performance of the transistor from deteriorating due to unnecessary additional resistance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional LDD structure transistor.

FIG. 3 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 7 is a sectional view showing an application example of the present invention.

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 5 Low concentration N-type diffusion layer 6 Highly concentrated N-type diffusion layer 7 Insulating film 8 Aluminum electrode 9 Sidewall oxide film 10 Polycrystalline silicon film 11 Silicon oxide film 12 Photoresist film 13 Photoresist film

Claims (1)

[Claims] 1. Two MIS transistors disposed adjacent to each other sharing a drain region on a semiconductor substrate, each gate electrode of the two MIS transistors having a spacing between the gate electrodes equal to a distance from a gate insulating film. It has a trapezoidal cross-section that widens accordingly, and has vertical sides on the source side.
A semiconductor device characterized in that the drain region has a low concentration impurity diffusion layer under each of the gate electrodes, and each source region of the two MIS transistors has a high concentration impurity diffusion layer.