JPH0425752B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to general image scanning/storage devices or image scanning/display devices that once scan and decompose an image and then compose the image again, such as in a facsimile transmission device. The present invention relates to an image signal processing method and an image signal processing apparatus.

Conventional configurations and their problems In recent years, the use of facsimile in daily work has been expanding more and more, and along with this, the demand for reproduction of halftones in addition to the conventional black-and-white binary is increasing. Reproduction of halftones is often restricted by both recording devices and transmission methods. For example, devices that record on silver halide photographic paper used in photography and thermal recording devices have good halftone recording characteristics, but electrostatic recording devices and inkjet recording devices are essentially suited for binary recording. I can say that. On the other hand, the transmission method is changing from the conventional analog transmission to digital transmission, and there is a trend toward faster and more efficient transmission by making full use of data compression technology. Therefore, if there is a good method for pseudo-halftone display using a black and white binary recording device, it will be compatible with the future direction of digital data transmission, and it will be possible to construct a more optimal facsimile transmission system.

Now, typical methods of pseudo-halftone display include the halftone method seen in printed images of newspapers and magazines, and the dither method in which the image is binarized according to a matrix table of threshold values. However, these conventional methods have the disadvantage of deteriorating the resolution for binary images such as characters and line drawings, and therefore, for images that contain a mixture of intermediate density and binary images, one or the other must be sacrificed. You won't be able to use it.

The dither method, which is a pseudo-halftone display with relatively little deterioration in the resolution of binary images, will be described below as one of the conventional examples with reference to FIG. In the figure a, 1 is a pattern indicating quantized original image data, 2 is a pattern indicating threshold value data, and 3 is a pattern indicating binarized data. The original image data D _xy is compared in size with the threshold data S _xy at the corresponding position, and if it is larger, it is black (=1), otherwise it is thresholded as white (=0\), and the binarized data is processed.
Converted to P _xy . For example, threshold data 2 is shown in figure b.
Threshold data having a size of 4×4 as shown in the figure is repeatedly developed. When the threshold value window is 4×4, 16 types of threshold values can be set, and therefore, halftone display that pseudo-expresses 17 levels for the original image data is possible. D _nax shown in FIG. 5B represents the maximum value of the original image data.

As mentioned above, in the dither method shown in the example in Figure 1, each pixel of the original image data is thresholded independently and converted to binary data, but the number of blacks corresponding to the level of the original image data appears in each threshold window. This results in an average representation of midtones. The relationship between the size of the threshold window and display image quality is that the smaller the window, the better the image resolution, but fewer halftone levels that can be displayed; the larger the window, the worse the image resolution, but the more halftone levels that can be displayed. There is a relationship of becoming. In any case, for black and white binary original images, this method has the disadvantage that the display quality is worse than that of ordinary binary processing.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an image signal processing method and an apparatus thereof that can perform pseudo-halftone display without deterioration in image quality due to resolution deterioration of the binary image.

Structure of the Invention The present invention provides: (1) storing the image signal level of each pixel obtained by scanning and decomposing the original image in first and second image signal storage means; (2) storing the second image signal; Find the sum S of the image signal levels of all pixels in the second scanning window of M pixels to scan the storage means and the error correction amount _E , and when O≦S≦C×M, S=C. ×N+A When O>S, N=O, A=O When S>C×M, N=M, A=O [However, C is a predetermined image signal level, N is an integer satisfying O≦N≦M, and A Find N and A such that O≦A<C ₀ ], and (3) find the number M of pixels for scanning the position of the first image signal storage means corresponding to the second image signal storage device.
(4) numbering each pixel in the first scanning window in descending or ascending order of pixel signal level; (4) numbering each pixel in the second scanning window corresponding to the first scanning window in descending order; For the 1st to Nth pixels, C is the image signal level, (N+1)
The th pixel is assigned A as the image signal level, the remaining pixels are assigned O as the image signal level, and in ascending order, the 1st to (M-N-1)th pixels are assigned O as the image signal level. , (M-N)
The pixel is replaced with A as the image signal level, and the remaining pixels are assigned C as the image signal level. (5) Each pixel within the second scanning window is scanned again by subsequent scanning window movement. The image signal level P _1ST of the pixel that is no longer included in the window is determined by comparing the image signal level P _1ST with a predetermined binarization level V _where O≦V<C.
When the image signal level P 1ST is large, C is substituted, and when the image signal level P _1ST is not large, O is given as the image signal level P _2ND . (6) The sum of the differences between the image signal levels P _1ST and P _2ND ) into divided error correction amounts, one of the divided error correction amounts is set to the error correction amount E, and the remaining K divided error correction amounts are set to the second divided error correction amount.
For each pixel within the scanning window, set the K pixels that are not included within the scanning window by the next scanning window movement but are again included within the scanning window by the subsequent scanning window movement. (7) The above (2), (3), (4), (5), (6), and (7) are added to the first and second image signal levels.
The first,
Image processing is performed repeatedly while moving the second scanning window by a predetermined number of pixels.

DESCRIPTION OF EMBODIMENTS An embodiment of the image signal processing method of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram explaining the scanning window and data conversion. In the figure a, reference numeral 5 is original image data, and data conversion is performed within the scanning window 6 while the scanning window 6 is main-scanning to the right side of the figure a and sub-scanning to the lower side. Although the size of the scanning window 6 is arbitrary, it is, for example, about 2×2 pixels, 3×3 pixels, or 4×4 pixels. The scanning window 6 is basically scanned pixel by pixel in both the main scanning direction and the sub-scanning direction, but this is not necessarily the case.

Note that this embodiment will be explained by scanning one pixel at a time.

Now, if the scanning window 6 is 2×2 pixels, one pixel of the original image data, for example, the pixel D _n,o within the scanning window 6.
will undergo data conversion four times as the scanning window 6 moves. Data conversion is performed as shown in FIGS. 2b to 2e. Note that FIG. 2B shows the original image data at the position of the scanning window 6, and FIG.

(However, the number ' indicates the number of times that pixel has undergone data conversion in the past.) Figure d shows the state after data conversion has been performed at the current scanning window 6 position. . Here, it is assumed that the converted data is not rewritten to the original image data but is stored separately. The data conversion within the scanning window 6 is performed as shown in the flowchart of FIG. 3. (a) The total sum S of data as shown in FIG. 2c is determined.

S=D _n-1 , _o-1 + D _n-1 ″, _o + D _n ′, _o-1 + D _n,o ...(1) (b) Find N and A in the following equation.

S=C・N+A...(2) However, C is a constant, for example, C=D _nax .
D _nax is the maximum value. Further, N is a positive integer.

(c) Check the order of data size as shown in Figure 2b. If the values are the same, they are determined in a predetermined order.

(d) Convert the data shown in FIG. 2c to C for N parts corresponding to the data shown in FIG. 2b in order of size, convert the next to A, and convert the rest to 0\.
For example, in (b), N=1 is found, and in (c), D _n,o-1 ＞D _n,o ＞ D _n-1,o ＞D _n-1 , _o-1 ...(3) When a certain thing is determined, data conversion as shown in FIG. 2e is performed.

If the above data conversion is performed on all the data of the original image, the data value of the original image data is small.
Where the number of C is large and the data value is large, the number of C is large, and the conversion is done in proportion to the data value of the original image data. Therefore, if normal threshold processing is performed on the data-converted values to create binarized data, pseudo-intermediate display data can be obtained.

According to the data processing described above, since the conversion data is arranged (redistributed) in order of the original image data, not only does decomposition and deterioration of the black and white binary original image not occur, but also the thin lines in the original image are Because of this, even areas that would be dotted lines in normal threshold processing tend to be reproduced as continuous lines. This is because, in the data processing described above, large value data in the original image attracts surrounding small value data and has the effect of becoming even larger.

Now, in Figure 2 d, D _n-1 and _o-1 are the values after the last data conversion. It is fine if this value is O or C, but if it is A, it will be binarized and an error will occur. In other words, since white has a value of O and black has a value of C after binarization, thresholding A and binarizing it means changing it to white or black redundantly, resulting in a pseudo halftone gradation. It worsens the tonal characteristics. Therefore, the value of D _n-1 , _o-1 is set as P _1ST , and the difference between this and the threshold value P _2ND (O or C) is calculated, and this is set as the total error correction amount E _s , and the total error correction amount _Es is Divide it and add one as the error correction amount E when calculating the total sum S in the next scanning window, and the rest as the divided error correction amount.
By adding E _d to the value D _n ″, _o-1 after data conversion in Figure 2 d and replacing it, the error correction amount E is used for the next process in the main scanning direction and corrects the total sum S. However, the divisional error correction amount E _d is used in the next process in the sub-scanning direction to correct the sum S. It is possible to improve the gradation characteristics in both the main-scanning direction and the sub-scanning direction.

Although the error correction amount E _s may be divided at any ratio, the following explanation will be based on an example in which it is divided into 1/2.

The image signal processing method will be explained in more detail below with reference to the flowchart shown in FIG.

[In the flowchart shown in FIG. 4, G ₁ , G ₂ : image data storage device, W ₁ : scanning window for image data of G ₁ , D _n,o , D _n,o-1 , D _{n- 1,o} , D _n-1 , _o-1 : Each data in W ₁ , W ₂ : Scanning window for image data of G ₂ , D _n,o , D _n ′, _o-1 , D _n-1 ″ , _o , D _n-1 , _o-1 : Value of each data in W ₂ before data conversion at the current scanning window position. The number ′ is the number of times data was converted at the past scanning window position, D _n ′, _o , D _n ″, _o-1 , D _n-1 , _o , D _n-1 , _o-1 : W ₂
The value after data conversion at the current scanning window position for each data within. The number ' is the number of times data has been converted in the past including the current scanning window position, E: error correction amount, S _n : total data within scanning window W ₂ S: value of S _n + E, M: scanning window W ₁ , number of pixels in scanning window _W2 , M=4, C: predetermined image signal level, N: integer O≦N≦M, A: O≦A<C, V: binarization level E _s : error correction Total amount E _d : Indicates the division error correction amount E _s =E+E _d , respectively. ] (a) Input image data into storage devices G ₁ and G ₂ (note that it is possible to perform the following processing while inputting image data one pixel or one scanning line at a time, but here we will input all image data ).

(b) A scanning window W ₁ is placed at the start position of the main scanning and sub-scanning of the image data input to the storage device G ₁ , and a scanning window W is placed at the start position of the main scanning and sub-scanning of the image data input to the storage device G ₂ . ₂ is initially set.

(c) Error correction amount E= as initial value at the beginning of main scanning
Set O.

(d) Total sum S _n of data within scanning window W ₂ and error correction amount E
Find the sum S.

(e)・(f) Compare and judge the size of S, and if O>S
In (g), set N=O, A=O, and if S>C×M, set N=M, A=O in (ch), otherwise (li) find N and A such that S=C×N+A. .

(N) Data D _n,o , D _n,o-1 , within scanning window W ₁ ,
The corresponding data positions within the scanning window W ₂ are rewritten as follows in descending order of D _n-1,o , D _{n- 1 , and o-1} .

[Let C be up to the Nth number.

Let A be the N+1st one.

Let the rest be O. ] (ru) Data D _n-1 , _o-1 woP _1ST in scanning window W ₂
shall be.

(wo) Compare P _1ST and binarization level V. P _1ST
If is large, P _2ND is set to C with (W), and if P _1ST is large, P _2ND is set to O with (F). Note that the values of data D _n-1 and _o-1 are finally at the binarization level V
Since it is converted to binary data by , it is the same whether you replace it with the value of P _2ND here or leave it as is.

(Y) P _2ND −P _1ST is determined as the total error correction amount E _s , and the error correction amount E and the divided error correction amount E _d to be corrected at the next scanning window position are each set as E _s /2.

(T) Value after data conversion within scanning window W ₂ D _n ″, _o-1
The division error correction amount E _d is added to and replaced with the values of D _n ″, _o−1 .

(v) Both scanning window W ₁ and scanning window W ₂ are moved by one pixel in the main scanning direction.

(S) Determine whether processing in the main scanning direction has been completed. If it has not finished, return to (d).

(t) If it has finished, press (w) to return both scanning window W ₁ and scanning window W ₂ to the main scanning start position.
Move one pixel in the sub-scanning direction.

(n) Determine whether processing has ended in the sub-scanning direction, and if it has not ended, return to (c).

By using the processing methods (a) to (e) shown in FIG. 4, it is possible to obtain a pseudo halftone display that does not suffer from deterioration in image quality due to deterioration in the resolution of the binary image.

Next, an image signal processing device according to an embodiment of the present invention will be described with reference to FIG.

FIG. 5 shows block connections of an image signal processing apparatus in an embodiment of the present invention.

In FIG. 5, reference numeral 15 denotes a timing signal generation circuit that supplies timing signals to each block function to be described later, and timing signal supply lines to each block function are omitted. 17 is an A/D converter that converts an analog image signal inputted through the terminal 16 into a digital image signal; 19 and 21 store digital image signals according to addresses instructed through gate circuits 18 and 20, respectively; or an image data storage device to be read; 22 is a gate circuit 18;
20 to send the address information to the gate circuit 18,
23 is a binary conversion circuit that binarizes the data for which all data conversion processing for redistribution has been completed and records it in an image recording device or the like via a terminal 24; The scanning window read out from the image data storage device 21 by
_{28 is a scanning window W 1 read} out from the image data storage device 19 via the gate circuit 18; A ranking circuit for ranking data in descending order of size, 2
Reference numeral 9 denotes a redistribution circuit that creates converted data from the sum S sent out from the data addition circuit 25 and the divided error correction amount _Ed sent out from the error correction calculation circuit 26, and performs reallocation.

The operation of the above configuration will be explained below.

First, an analog image signal obtained by scanning an original image is converted into a digital image signal by an A/D converter 17 via an input terminal 16, and is stored in an image data storage device 19 via a gate circuit 18, and is also stored in a gate circuit. Image data storage device 21 via 20
It will also be remembered. At that time, the gate circuit 18 and the gate circuit 20 are controlled by an address control circuit 22, and the memory device 19 and the memory device 21, respectively.
Indicates the data write/read address. In the process to be described later, the data stored in the storage device 19 is used as data for ranking, and the data in the storage device 21 is finally rewritten by data conversion by redistribution.

Further, the data for which all data conversion processing for redistribution has been completed is read out from the storage device 21 via the gate circuit 20, and output as an output image signal via the binarization circuit 23 to be recorded by an image recording device (not shown) or the like. It is output to terminal 24. Now, data addition circuit 2
5 calculates the sum S of the data within the scanning window obtained from the storage device 21 via the gate circuit 20 and the error correction data E obtained from the error correction amount calculation circuit 26. The ranking circuit 28 determines all the data addresses at the corresponding scanning window positions in the storage device 21 in descending order of each data in the scanning window obtained from the storage device 19 through the gate circuit 18, and sends the data to the address control circuit 22 and the error correction calculation circuit 26. to notify. Also, at the timing of this notification, the error correction amount calculation circuit 26 and the redistribution circuit 29
will also be notified. Therefore, the redistribution circuit 29 creates converted data from the total sum S obtained from the data conversion circuit 25 and the divided error correction amount E _d sent from the error correction calculation circuit 26, and transfers the converted data to the storage device 21 specified by the address control circuit 22. Gate circuit 20 at address
Conversion data is sequentially written through the . The error correction calculation circuit 26 also uses the address and timing information from the ranking circuit 28 to output P _1ST , which is the last data-converted value (D _n-1 , _o-1 in FIG. 2 d) within the scanning window. , and compares the P _1ST with the binarization level V obtained from the binarization circuit 23 to obtain the value P _2ND of O or C.
1/2 of the value of P _1ST −P _2ND is given as the error correction amount E and the divided error correction amount E _d in the next scanning window.

By repeating the above steps, image signals can be processed.

The detailed configurations of the ranking circuit 28, redistribution circuit 29, and error correction calculation circuit 26 shown in FIG. 5 will be described below with reference to FIGS. 6 to 8.

First, details of the ranking circuit 28 will be explained.

FIG. 6 shows a block configuration of the ranking circuit 28 shown in FIG. 2 read out from the image data storage device 19 via the gate circuit 18
The four pieces of data within the ×2 scanning window _W1 are input from the data input terminal 44, and are sent to the four data registers 47 corresponding to the positions within the scanning window via the gate circuit 46.
is stored in a predetermined location. At this time, the memorized position is designated by setting the address of the output of the counter 48 that counts the timing pulse T ₂ inputted from the input terminal 43 in the register 47 via the gate circuit 49 . Further, the timing pulse _T2 inputted from the input terminal 43 passes through the gate circuit 50 and becomes a data write clock for the register 47, and at the same time, the timing control circuit 51
is also sent to signal line 52 to output a gate switching signal. The gate switching signal on the signal line 52 drives the gate circuit 46, the gate circuit 49, and the gate circuit 50 to create an input mode state in which the register 47 receives four pieces of data input from the input terminal 44. On the other hand, the maximum value detection circuit 53 detects the maximum value for the four data in the register 47,
Output the data address of the maximum value. At this time, the timing control circuit 51 uses the gate switching signal of the signal line 52 to control the gate circuit 46, gate circuit 49,
The gate circuit 50 is driven to create a state in which the contents of the register 47 are rewritten. In this state, the data address of the maximum value is set in the register 47 via the gate circuit 49, the negative constant value of the register 54 is set in the register 47 via the gate circuit 46, and the negative constant value of the register 54 is set in the register 47 via the gate circuit 46. The numerical value is sent to the register 47 via the gate circuit 46.
is set to Then, the internal clock signal output from the timing control circuit 51 via the signal line 55 becomes the data write clock for the register 47 via the gate circuit 50.
The maximum value data of 7 is rewritten to negative data.
In this state, the internal clock signal 4 is connected to the signal line 55.
When the data is outputted, the contents of the register 47 will all change to negative values. In the order in which this internal clock is output, the data addresses corresponding to the data first fetched into the register 47 are outputted to the output of the maximum value detection circuit 53 in descending order. This address becomes the write data of the four address storage registers 56 and is stored sequentially, but at this time, the internal clock of the signal line 55 is
At the same time as the write clock of
is input. The output of the counter 57 is sent via a gate circuit 58 to the address storage register 56 to designate the location where the address data is to be stored. At this time, the signal line 5 output from the timing control circuit 51
The output signal of 9 drives the gate circuit 58 to enter the data write state, that is, the output of the counter 57 is applied to the address storage register 56. After four pieces of address data are written in the address storage register 56, the output signal of the signal line 59 drives the gate circuit 58 to put the address storage register 56 in a data read state. After that, when a read clock is output to the signal line 60 of the timing control circuit 51, the counter 61 counts this clock and provides the output to the address storage register 56 via the gate circuit 58 to specify the read position of the address data. . In this way, the address data from the ranking circuit 28 is output to the output terminal 62. Further, the readout clock on the signal line 60 is outputted to an output terminal 63 and becomes a timing signal for other circuit blocks. Note that the counters 48, 57, and 61 are all 2
This is a bit counter, which is not shown, but is reset by a sub-scanning synchronization pulse. Further, the details of signal timing adjustment, such as delay time compensation in hardware production, are self-evident and will not be explained here.

What should be noted here is that there are four types of address data output to the output terminal 62: 00, 01, 10, and 11, and the addresses in the image data storage devices 19 and 21 in FIG. It will be made in Therefore, 00, 01, 10, 11 are addresses within the scanning window, and if we consider them in correspondence with the scanning window 9 in FIG. 2d, 00 is D _n-1 , _o-1 , 01
should be defined as D _n-1 , _o , 10 as D _n ″, _o-1 , 11 as D _n ′, _o .

Therefore, the data input from the input terminal 44 must also appear in the order corresponding to the addresses within this scanning window. The address constant in the error correction calculation circuit 26 in FIG. 8, which will be described later, also means an address within the scanning window.

Next, the redistribution circuit 29 will be explained.

FIG. 7 shows detailed block connections of the redistribution circuit 29 of FIG. 5. The sum S of data within the scanning window is set in a register 66 from an input terminal 64 via a gate circuit 65. A timing signal input from input terminal 67 drives gate circuit 65 and register 66, and when setting the sum S in register 66, the signal from input terminal 64 is passed through and written to register 66. Otherwise, gate circuit 65
passes the output signal of the subtraction circuit 68. A subtraction circuit 68 subtracts a constant C set in a register 69 from the contents of the register 66 and outputs the result. The timing signal input from the input terminal 63 is sent to the register 6.
6, and the output signal of the subtraction circuit 68, which enters through the gate circuit 65, is taken into the register 66.
Therefore, the output of the register 66 will be such that the constant C is sequentially subtracted from the initial sum S every time a timing signal is input from the input terminal 63. The comparison circuit 70 compares the contents of the register 66 and the contents C of the register 69, and if the contents of the register 66 are greater or the same, it drives the gate circuit 71 to make the contents C of the register 69 the output of the gate circuit 71, When the content of is small, the gate circuit 71 is driven and the register 6 is
6 is the output of the gate circuit 71. The positive/negative determination circuit 72 drives the gate circuit 73 and registers 6
When the content of register 66 is positive, the output of gate circuit 71 is used as the output of gate circuit 73, and when the content of register 66 is negative, the constant 0, which is the content of register 74, is used as the output of gate circuit 73. A timing signal input from the terminal 63 allows the divided error correction amount E _d input from the input terminal 87 to pass through.

The output of the gate circuit 88 is applied to an adder circuit 89, where it is added to the output of the gate circuit 73, and the redistributed data to the output terminal 75 is output. By the way, since the gate circuit 88 is controlled to open when D _n ″, _o-1 in the scanning window of FIG. 2d,
The division error correction amount E _d is added to D _n ″, _o-1 , and the other data is redistributed as is.

Next, the error correction calculation circuit 26 will be explained.

FIG. 8 shows detailed block connections of the error correction arithmetic circuit 26 shown in FIG. Comparison circuit 76
compares the address constant of the register 77 and the address data input from the input terminal 62, and if they match, drives the gate circuit 78 to allow the timing signal input from the input terminal 63 to pass. The address constant of register 77 is the value of the last data converted within the scanning window.
D _n-1 , address within the scanning window of _o-1, 00 in the above example
The value is . The comparison circuit 79 compares the binarized level V input from the input terminal 80 with the redistributed data input from the input terminal 75, and if the redistributed data is larger, drives the gate circuit 81 and registers 8.
2 is set as the output of the gate circuit 81, and if the redistributed data is large, the gate circuit 81 is driven and the constant O of the register 83 is set as the output of the gate circuit 81.
Let the output be The subtraction circuit 84 subtracts the output of the gate circuit 81 from the redistribution data at the input terminal 75. The register 85 takes in and holds the result of the subtraction circuit 84 using the output signal of the gate circuit 78. A divider circuit 90 halves the output of the register 85 and sends it to an output terminal 86 as an error correction amount E, and outputs it to an output terminal 91.
is given as the division error correction amount E _d .

Effects of the Invention As described above, the present invention can obtain pseudo halftones without deteriorating image quality, and the image processing according to the present invention only needs to be performed in the image reading example. Therefore, for example, existing facsimile systems can be implemented by simply adding some circuits to the transmitting side. Conventionally, when an image was a mixture of a binary image such as a character line drawing and a halftone image, it was impossible to avoid deterioration in the image quality of one of them, but the present invention has made it possible to display and record images of high quality for both. Furthermore, in the conventional dither method, the number of pseudo halftone levels that can be expressed is limited by the matrix size, and if the scanning window size is increased to increase the number of levels, the resolution will deteriorate. Therefore, when processing color images, the number of reproduced colors is so small that it is not practical. However, since the levels that can be expressed in the present invention are essentially continuous, it can be said to be an optimal method for color image processing. In addition, in color image processing, it is easily possible to reduce the overlap of each color by staggering the level distribution of the additional data for each of the yellow Y, cyan C, magenta M, and black B signals. That is clear. Furthermore, the regularity of the additional data also improves the band compression efficiency of various currently announced predictive coding methods, and the present invention has a very large effect.

[Brief explanation of drawings]

Figures 1a and b are schematic diagrams illustrating the dither method, which is one of the conventional pseudo halftone displays, and Figures 2a to 2e are scanning windows and data conversion of an image signal processing method in an embodiment of the present invention. 3 is a flowchart showing a part of the processing procedure of the method, FIG. 4 is a flowchart showing the processing procedure of an image signal processing method in an embodiment of the present invention, and FIG. 5 is a flowchart showing the processing procedure of a part of the method. A block wiring diagram of an image signal processing apparatus according to an embodiment of the present invention, FIG. 6 is a block wiring diagram of a ranking circuit in the same apparatus, FIG. 7 is a block wiring diagram of a redistribution circuit in the same apparatus, and FIG. FIG. 2 is a block diagram of an error correction calculation circuit in the same device. 19, 21... image data storage device, 25...
Data addition circuit, 26...Error correction calculation circuit, 2
8... Ranking circuit, 29... Redistribution circuit.

Claims (1)

[Claims] 1. The image signal level of each pixel obtained by scanning and decomposing the original image is stored in first and second image signal storage means, and the number of pixels to be scanned in the second image signal storage means. Find the sum S of the pixel signal levels of all pixels in the second scanning window of M and the sum S of the error correction amount _E , and when O≦S≦C×M, S=C×N+A, and when O>S. N=O, A=O When S>C×M, N=M, A=O [However, C is a predetermined image signal level, N is an integer such that O≦N≦M, and A is O≦A<C] Find N and A, and scan each pixel in a first scanning window of M pixels to scan the position of the first image signal storage means corresponding to the second image signal storage means in descending order of image signal level. or numbered in ascending order, the first
For each pixel in the second scanning window corresponding to the scanning window, in descending order, the first to Nth pixels have a pixel signal level of C, and the (N+1)th pixel has a pixel signal level of A. , the remaining pixels are replaced with O as the image signal level, and in ascending order, 1 is assigned.
The pixel from the (M-N-1)th pixel is assigned O as the pixel signal level, the (M-N)th pixel is assigned A as the pixel signal level, and the remaining pixels are assigned C as the pixel signal level. , for each pixel within the second scanning window, the pixel signal level P _1ST of the pixel that is no longer included within the scanning window due to subsequent scanning window movement,
The image signal level P _1ST is predetermined as O≦V<
By comparison with the binarization level V, which is C, if the image signal level P _1ST is large, C is determined, and if the image signal level P _1ST is not large, O is determined as the image signal level P _2ND.
Then, the image signal level P _1ST is given as
The sum of the differences between P _2ND and For each pixel in the second scan window, the K pixels that are not included within the scan window by the next scan window movement but are again included within the scan window by the subsequent scan window movement. adding each to the set image signal level, and moving the first scanning window and the second scanning window by a predetermined pixel amount over the entire area of the first and second image signal storage means through the above procedure. An image signal processing method characterized by repeating the process. 2. First and second image signal storage means that store the image signal level of each pixel obtained by scanning and decomposing the original image, and a second image signal storage means of the number M of pixels that scans the second image signal storage means. Find the sum S _n of the image signal levels of all pixels within the scanning window and the sum S of the error correction amount E, and when O≦S≦C×M, S=C×N+A, and when O>S, N=O, A=O When S>C×M, N=M, A=O [However, C is a predetermined image signal level, N is an integer satisfying O≦N≦M, and A is O≦A<C]. and calculating means for calculating each pixel within a first scanning window of M pixels, which scans the position of the first image signal storage means corresponding to the second image signal storage means, in descending order of image signal level or a ranking means for numbering in ascending order; and 1 for each pixel in the second scanning window corresponding to the first scanning window in descending order;
The pixel from the th to the Nth has an image signal level of C.
, the (N+1)th pixel is assigned A as the image signal level, the remaining pixels are assigned O as the image signal level, and in ascending order, from the 1st to (M-N
-1)th pixel has O as the image signal level,
The (M−N)th pixel has A as the image signal level,
Assignment means assigns C as an image signal level to the remaining pixels, and for each pixel within the second scanning window, the image signal level P _1ST of the pixel that is no longer included within the scanning window due to subsequent scanning window movement is provided. , the image signal level
By comparing P _1ST with a predetermined binary level V such that O≦V<C, if the image signal level P _1ST is large, C is determined, and if the image signal level P _1ST is not large, O is the image signal. means for performing replacement to give a level P _2ND , and dividing the sum of the difference between the image signal levels P _1ST and P _2ND into (K+1) divided error correction amounts, one of the divided error correction amounts being an error correction amount. E, and the remaining K divisional error correction amounts are for each pixel within the second scanning window, and may not be included within the scanning window depending on the next scanning window movement, but will be included in the subsequent scanning window. means for respectively adding the set image signal levels of the K pixels included in the scanning window by the movement; An image signal processing device comprising a scanning window and means for moving the second scanning window by a predetermined pixel.