JPH04257120A - Semiconductor device - Google Patents

Abstract

PURPOSE:To easily and efficiently check the switching voltage of an A/D converter by checking the switching voltage of the A/D converter by one terminal. CONSTITUTION:The input terminal of a test circuit 11 is connected to output terminals of comparators 12a1, 12a2, and 12a3 of an A/D converter 12, and outputs of comparators 12a1, 12a2, 12a3 of the A/D converter 12 are directly taken in to encode a signal. That is, the test circuit 11 is so constituted that respective conversion outputs of the A/D converter 12 are inputted to output the output, whose output logic is inverted in accordance with output inversion of comparators, from one terminal. The output terminal of the test circuit 11 is connected to an output terminal 13 through one terminal of an output mode changeover switch 4, and the output from the text circuit 11 can be directly observed from the output terminal 13 by the output mode changeover switch 4.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a built-in analog
The present invention relates to a semiconductor device capable of testing switching voltage of a digital (hereinafter referred to as A/D) converter.

0002

2. Description of the Related Art In recent years, semiconductor devices have become increasingly highly integrated, and the number of A/D mixed type semiconductor devices has also increased. Furthermore, although devices incorporating an A/D converter into one chip have appeared, on the other hand, testing of semiconductor devices has also become complicated and time-consuming. Conventionally, a test method has been to divide a semiconductor device into several internal blocks and directly extract the output from each block for testing. Therefore, a method and test circuit for testing an A/D converter built into a semiconductor device will be described below.

FIG. 6 is a block diagram showing the circuit configuration of a conventional semiconductor device, and shows a case where an analog input voltage is divided into n parts. In FIG. 6, the analog input terminal 1 to which an analog signal is input is connected to the comparators 2a1, . . . 2an-2, 2an-1 of the A/D converter 2, respectively.・2an
The output terminals of -2 and 2an-1 are respectively connected to the input terminals of the internal logic circuit 3, and are also connected to one terminal of each output mode changeover switch 4. Each of the output mode changeover switches 4 switches between one terminal to which each output terminal of the A/D converter 2 is connected, and the other terminal to which each output terminal of the internal logic circuit 3 is connected, respectively. They are output to output terminals 5, respectively.

The operation of the semiconductor device configured as described above will be explained below. First, A/D converter 2
Each comparator 2a1,...2an-2, 2an-1
The switching voltages of VL <V1 <V2 <V3 <...<Vn-1
<VH, and the input voltage range A of analog input terminal 1 is set as VL<A<VH. n is the number of voltage divisions of the A/D converter 2. Further, the output mode changeover switch 4 is set so that the output of each comparator 2a1, . . . 2an-2, 2an-1 appears directly at each output terminal 5.

In this state, when the voltage at the analog input terminal 1 is changed from VL to VH, first the output of the comparator 2a1 of the switching voltage V1 changes, and then the output of the comparator 2a2 (not shown) of the switching voltage V2 changes. )
The output of the comparator 2an-1 changes, and finally the output of the comparator 2an-1 of the switching voltage Vn-1 changes. At this time, each comparator 2a1, . . . 2an- is directly connected to each output terminal 5.
2 and 2an-1 appear, and by observing these outputs, each comparator 2 of the A/D converter 2
The switching voltages of a1, . . . 2an-2, 2an-1 can be checked.

[0006]

However, in the above conventional configuration, each of the comparators 2a1, . . . 2an-2,
In order to directly observe the output of each 2an-1, a large number of terminals are required, which poses a problem in that it cannot be easily inspected in a short period of time.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device that can easily test the switching voltage of an A/D converter in a short time.

[0008]

Means for Solving the Problems In order to solve the above problems, a semiconductor device of the present invention includes an A/D conversion means having a plurality of comparators and converting an analog input voltage into a digital voltage; The test circuit is provided with a test circuit which receives the conversion output from each comparator of the conversion means as an input, and outputs from one terminal an output whose output logic is inverted as the output of the comparator is inverted.

[0009]

[Operation] With the above configuration, the A/D conversion output from each comparator of the A/D conversion means can be observed with one terminal, so that the switching voltage, which is the A/D conversion output of the A/D conversion means, It becomes possible to inspect easily and efficiently.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the same reference numerals are given to those having the same functions and effects as those of the conventional example, and the explanation thereof will be omitted.

FIG. 1 is a block diagram showing the circuit configuration of a semiconductor device according to an embodiment of the present invention.
This shows the case of division. In FIG. 1, the input terminal of the test circuit 11 is connected to each comparator 12 of the A/D converter 12.
each comparator 12a1, 12a of the A/D converter 12 is connected to the output terminal of a1, 12a2, 12a3, respectively.
The outputs of 2 and 12a3 are directly taken in, respectively, and the signals are encoded. That is, the test circuit 11 operates on each comparator 12a1, 12a2, 12a of the A/D converter 12.
The conversion outputs from 3 are respectively input, and outputs whose output logics are inverted as the outputs of the comparators are inverted are outputted from one terminal. The output terminal of this test circuit 11 is connected to the output terminal 13 via one terminal of the output mode changeover switch 4, and the inverted output from the test circuit 11 is configured to be directly observable from the output terminal 13 by the output mode changeover switch 4. ing.

FIG. 2 is a specific circuit diagram of the A/D converter 12 and test circuit 11 in FIG. 1. In FIG. 2, analog input terminal 1 is connected to comparators 12a1, 12a2, and 12a3 of A/D converter 12, respectively,
The output terminal of the comparator 12a1 is the NAND gate 14,
15, and is also connected to the input terminal of comparator 12a2.
The output terminal of is connected to NAND gate 1 via inverter 16.
4 and is connected to the input terminal of NAND gate 15.
Further, the output terminal of the comparator 12a3 is connected to the input terminal of the NAND gate 14 via the inverter 17, and is also connected to the NAND gate 15. The output terminals of NAND gates 14 and 15 are NAND
The input terminals of the NAND gates 18 are connected to each other, and the output terminal of the NAND gate 18 is connected to an output terminal 19. Above, NAND gates 14, 15, 18 and inverter 1
6 and 17 constitute a test circuit 11. Here, the switching voltages of the comparators 12a1, 12a2, and 12a3 are respectively V1, V2, and V3.
It is assumed that V1 <V2 <V3.

The operation of the above configuration will be explained below. First, when the analog input voltage input to analog input terminal 1 switches and the voltage is less than V1, the outputs of each comparator 12a1, 12a2, and 12a3 are all L.
level and therefore NAND gates 14, 15
Since none of the input voltages become H level, the output voltages of NAND gates 14 and 15 both become H level. Therefore, when all the input voltages of the NAND gate 18 are at H level, the output voltage becomes an L level test circuit output and is output from the output terminal 19, as shown at a1 in FIG. Next, when the analog input voltage switches and reaches V1, the output of the comparator 12a1 becomes H level, and the outputs of comparators 12a2 and 12a3 are both L level. As a result, NAND gate 1
Since all the input voltages of NAND gates 4 and 4 are at H level, the output voltage of NAND gate 14 is at L level. In addition, since the input voltages of the NAND gate 15 do not all become H level, the NAND gate 15
The output voltage of D gate 15 becomes H level. Therefore, since the input voltages of the NAND gate 18 do not all become H level, the output voltage is as shown in a2 of FIG.
The test circuit output becomes an H level and is output from the output terminal 19. Similarly, each time the analog input voltage reaches from voltage V1 to voltage V2 and further from voltage V2 to voltage V3, the comparator 12a2 and then the comparator 1
2a3 is also inverted and output from the output terminal 19 as a test circuit output of the L level shown at a3 in FIG. 3 and the H level shown at a4 of FIG.

Therefore, as described above, the test circuit 1 has one terminal with an output whose output logic is inverted before and after the inversion of the output of each of the comparators 12a1, 12a2, and 12a3.
1, each switching voltage of the A/D converter 12 can be easily and efficiently inspected by observing the output state of one of the output terminals 19, and each comparator 12a1, 12a2, The characteristics of 12a3, failure state, etc. can be easily and quickly inspected.

In this embodiment, the analog input voltage is divided into four parts, but the same effect can be obtained when the analog input voltage is divided into n parts. That is, as shown in FIG. 4, the switching voltages of each of the comparators 22a1 to 22an-1 of the A/D converter 22 are set to VL <V1 <V2 <V3 <...
<Vn-1 <VH, and the output mode changeover switch 4 is set so that the output of the test circuit 21 appears directly at the output terminal 23. In this state, if a test circuit 21 is provided in which an output signal 24 as shown in FIG. 5 appears at its output terminal 23 when the analog voltage at the analog input terminal 1 is changed from voltage VL to voltage VH, the output terminal 23, when the analog input voltage becomes voltage V1, it is inverted, and then,
When the voltage reaches the voltage V2, it is further inverted, and this is repeated until finally, when the analog input voltage is the voltage Vn-1, the output is inverted for the (n-1)th time.

[0016]

As described above, according to the present invention, by providing a test circuit which outputs from one terminal an output whose output logic is inverted as the output of each comparator of the A/D conversion means is inverted, the The switching voltage which is the conversion output of the D conversion means can be easily and efficiently inspected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of a semiconductor device according to an embodiment of the present invention, and shows a case where an analog input voltage is divided into four.

FIG. 2 is a specific circuit diagram of the A/D converter 12 and test circuit 11 in FIG. 1.

FIG. 3 is an operational diagram of the test circuit 11 in FIG. 2;

FIG. 4 is a block diagram showing the circuit configuration of a semiconductor device according to another embodiment of the present invention, and shows a case where an analog input voltage is divided into n.

5 is an operational diagram of the test circuit 21 in FIG. 4. FIG.

FIG. 6 is a block diagram showing the circuit configuration of a conventional semiconductor device, and shows a case where an analog input voltage is divided into n.

[Explanation of symbols]

11, 21 Test circuits 12, 22 A/D conversion circuits 13, 19, 23 Output terminals 12a1, 12a2, 12a3, 22a1, . . . 22a
n-2, 22an-1 Comparators 14, 15, 18 NAND gates 16, 17
inverter

Claims (1)

[Claims] 1. An analog-to-digital conversion means having a plurality of comparators and converting an analog input voltage into a digital voltage, each inputting a conversion output from each comparator of the analog-to-digital conversion means, and an output from the comparator. A semiconductor device comprising a test circuit that outputs an output from one terminal whose output logic is inverted as the output logic is inverted.