JPH04252469A - Recording medium and reproducing device for the same - Google Patents

Abstract

PURPOSE:To obtain an accurate synchronizing signal for sector even when an error exists on a recording plane by taking OR by matching the timing of the detection output of a synchronous pattern of sector unit and that of the synchronous pattern of auxiliary information. CONSTITUTION:An EFM input signal is inputted to a decoder 10, and decoded main data and the detection output of a subcode synchronous pattern can be obtained. The main data is sent to a synchronous detection circuit 80, and the detection output BP of a block synchronous pattern can be obtained, and the detection output of the subcode synchronous pattern is sent to a delay circuit 40, and the timing with the output BP is matched, and it goes to the detection output SCP, and is supplied to an OR gate 50 with the output BP, and they are OR-ed, then, it is outputted as the synchronizing signal for sector. In such a way, it is possible to obtain the accurate synchronizing signal for sector even when a large flaw, dust, or PLL step-out exists on the recording plane of a medium.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording medium for recording error-correction encoded data and a reproducing apparatus for the recording medium.

0002

2. Description of the Related Art Conventionally, so-called CIRC (cross-interleaved Reed-Solomon code) has been used as a format for recording PCM data on a recording medium such as an optical disk by subjecting it to error correction coding and adding auxiliary information. ), there is a so-called compact disc (CD) signal format in which PCM digital audio data is subjected to error correction encoding processing and a subcode is added as the above-mentioned auxiliary information.

FIG. 7 shows the signal format of the above-mentioned CD. That is, in the signal format of FIG. 7,
One frame is made up of a frame synchronization pattern, a subcode, digital audio data, and a parity bit used for error correction in order from the beginning. The one frame includes 24 channel bits in a frame synchronization pattern,
1 byte for subcode (1 byte is 14 channel bits by EFM (8-14 modulation)) and 32 bytes for each digital audio data and parity bit.
There are 3 channel bits for connection between each byte after the above frame synchronization pattern, resulting in a total of 588 bits.
The channel is a bit.

Furthermore, as shown in FIG. 8, 98 subcodes constitute one block (that is, 98 frames).
is configured. The first 2 of this block
Two synchronization patterns, S0 and S1, are arranged in each subcode, and each subcode for the remaining 96 frames has a so-called P channel (P1) of 1 bit each.
~P96), Q channel (Q1 ~Q96), and other information are arranged. Note that the frequency of one subcode frame is 7.35kHz÷98=7
The frequency is 5 Hz, and the period is 13.3 msec.

[0005] On the other hand, as an extended format in which the signal format of the above-mentioned CD is expanded, and instead of the above-mentioned digital audio data, data with a synchronization pattern attached in a fixed sector unit based on a predetermined data format is recorded. For example, there is a so-called CD-ROM format.

In the signal format of this CD-ROM, as shown in FIG. 9, one block of the subcode, that is, 98 frames of the CD, is treated as one sector. In addition, the recording area for one frame of digital audio data on the above-mentioned CD includes 24
Since the byte of data is stored, the above-mentioned one sector in the CD-ROM has a total of 2352 (24 x 98 = 23
52 bytes). Furthermore, the first 12 bytes of each sector are used as a synchronization pattern for the data file, that is, a block synchronization (sync) pattern, and the next 4 bytes are used as a header.

The header is composed of address information for minutes (1 byte), seconds (1 byte), blocks (1 byte), and mode (1 byte). Mode 0 is defined as an area indicating non-use. Further, in the mode 1, the area other than the block synchronization pattern and header is a 2048-byte user data area and 288 bytes of auxiliary data. The above auxiliary data is 4
It has a byte EDC area (error detection area), an 8-byte zero area (space), a 276-byte error correction area, a 172-byte P parity area, and a 104-byte Q parity area. The area other than the block synchronization pattern and header in mode 2 is a 2336-byte user data area.

[0008]

[Problem to be solved by the invention] Here, the above-mentioned CD-R
When playing back data recorded on an OM optical disc using a playback device, even if there are some scratches or dust on the disc recording surface, there will be no problem because the error will be corrected during decoding of the error correction code mentioned above. Detection of data or synchronization patterns is performed. However, depending on the size of the scratches, dust, etc., errors that exceed the error correction capability (errors that cannot be corrected) may occur. For example, Figure 10
As shown in , if there is an unreadable portion BER on the disk that is large enough to cause an uncorrectable error, the error ER caused by the unreadable portion BER is reduced to about the interleaving length ( For example, the error may spread over a period of approximately 15 msec.

In this way, when an error ER of about 15 msec, which is about the interleave length, occurs, the detection output of the block synchronization pattern, that is, the sector synchronization signal SCP, which should be obtained every 13.3 msec of the period of the subcode frame, becomes , at least one becomes unreadable. In the example of FIG. 10, the sector synchronization signal SCP
a will no longer be obtained.

Furthermore, the large unreadable portion BER
If there is a PLL based on the reproduced binary signal from the disk
(Phase Lock Loop) P to obtain the clock
The loop of LL may come off, and in this case, the above P
EFM demodulation, etc. performed in response to the LL clock becomes impossible, and the sector synchronization signal SCP described above also becomes impossible to detect.

In the CD-ROM format, the sector synchronization signal SCP cannot be read until the sector data is deinterleaved, so it takes time to obtain the sector synchronization signal SCP. This time requires approximately 15 msec for 108 EFM frames.

[0012] The present invention is proposed in view of the above-mentioned circumstances. For example, in a CD-ROM,
To provide a recording medium in which a signal is recorded in a format capable of obtaining a synchronizing signal for a sector even when an error exceeding the capability of an error correction code or a PLL error occurs, and a reproducing device for the recording medium. The purpose is to

[0013]

[Means for Solving the Problems] The recording medium of the present invention has been proposed to achieve the above-mentioned object, and is
M data is subjected to error correction encoding processing and the format is extended to add auxiliary information including a synchronization pattern, and instead of the above PCM data, a synchronization pattern is added in a fixed sector unit based on a predetermined data format. In the recording medium on which recording is performed in an extended format using the auxiliary information, the sector-by-sector synchronization pattern is recorded while maintaining a predetermined positional relationship with the synchronization pattern of the auxiliary information. Also,
The recording medium playback device of the present invention expands the format of PCM data to be subjected to error correction encoding processing and adds auxiliary information including a synchronization pattern, and instead of the PCM data, a certain sector is encoded based on a predetermined data format. A reproducing device for a recording medium that uses data to which a synchronization pattern is attached in units and records the synchronization pattern in sector units while maintaining a predetermined positional relationship with respect to the synchronization pattern of the auxiliary information, The timing of the detection output of the synchronization pattern and the detection output of the synchronization pattern of the auxiliary information are logically summed, and the output thereof is used as the synchronization signal for the sector.

[0014]

[Operation] According to the recording medium and the reproducing apparatus for the recording medium of the present invention, the synchronization pattern of each sector and the synchronization pattern of the auxiliary information are recorded on the recording medium while maintaining a predetermined positional relationship, and the reproducing apparatus records the synchronization pattern of each sector and the synchronization pattern of the auxiliary information. The detection output of the synchronization pattern for each sector and the detection output of the synchronization pattern of the auxiliary information are logically summed and used as a synchronization signal for the sector. If either one of them can be read, a synchronization signal for the sector can be obtained.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a recording medium and a reproducing apparatus for a recording medium according to the present invention will be described with reference to the drawings. FIG. 1 shows a signal format recorded on a recording medium according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a recording medium reproducing apparatus according to an embodiment of the present invention.

[0016] The recording medium of this embodiment is one in which recording is performed in an extended format in which PCM data is subjected to error correction coding (CIRC) processing and a subcode is added as auxiliary information. Recording is performed according to the CD-ROM format, which is an extension of the CD format. Therefore, an optical disk is used as the recording medium of this embodiment. Here, in the CD-ROM format, instead of the PCM data in the CD format, as shown in FIG.
M format), data (
(hereinafter referred to as main data) is used for recording. Further, the subcode includes the S0 and S1 synchronization patterns (subcode synchronization patterns) as shown in FIG. 8 described above. Under such conditions, the recording medium of this embodiment converts the block synchronization pattern into the subcode synchronization pattern (S0, S1) as shown in FIG.
(either one or both) is recorded in a signal format that maintains a predetermined positional relationship. The physical configuration of the above optical disc is that of a normal CD-RO.
Since it is similar to the M disk, illustration of the disk configuration itself is omitted.

Here, the signal format shown in FIG. 1 is as follows:
It consists of the EFM (8-14 modulation) frame synchronization pattern shown in FIG. This is synchronized with the subcode synchronization pattern of, for example, S1 of the above subcodes. Specifically, for example, synchronization is achieved by placing the block synchronization pattern in the L6n, A byte position following subcode synchronization pattern S1 in the CD format as shown in FIG. . In other words, the fixed “00F” block synchronization pattern of the above-mentioned normal CD-ROM format
FFFFFFFFFFFFFFFFFFFF00'' pattern, when this fixed pattern is interleaved with the above data + parity, its placement position before encoding is not determined, so the above subcode synchronization pattern and this fixed pattern must be synchronized. In contrast, in this embodiment, as described above, the fixed pattern (block synchronization pattern) is arranged at the byte position of L6n, A, which always follows the subcode in the CD format. Figure 1 shows the format before error correction encoding (or after error correction decoding), and Figure 3 shows the format after error correction encoding. Furthermore, the above block synchronization pattern can be placed following S0 (or both S0 and S1) of the subcode, or it can be placed at the byte position of L6n,B. can.

The recording medium reproducing apparatus according to the embodiment of the present invention is a disc reproducing apparatus on which data is recorded in the format shown in FIG. 1, and as shown in FIG. The timing of the detection output and the detection output of the subcode synchronization pattern is matched, a logical sum (OR) is performed, and the output is used as a synchronization signal for the sector.

That is, in FIG. 2, input terminal 1
In this example, a signal (EFM
signal) is supplied. This input EFM signal is subjected to the above error correction encoding in a decoder 10 (details will be described later). In this decoder 10, the detection output of the subcode synchronization pattern is obtained together with the main data decoded by the error correction. The main data is taken out from the terminal 6, and the detection output of the subcode synchronization pattern is taken out from the terminal 3. The main data is sent to a block synchronization detection circuit 80, and by detecting the fixed pattern in this circuit 80, a block synchronization pattern detection output BP is obtained. The detection output BP of this block synchronization pattern is, as shown in FIG. 4, a signal indicating the timing according to the detection of the fixed pattern. Furthermore, the detection output of the subcode synchronization pattern is output from a delay (DL) circuit 4.
0. The delay circuit 40 delays the detection output of the subcode synchronization pattern in order to align the timing with the detection output BP of the block synchronization pattern from the block synchronization detection circuit 80. Therefore, the subcode synchronization pattern detection output SCP from this delay circuit 40 and the block synchronization detection circuit 80
The detection output BP of the block synchronization pattern is timed as shown in FIG. Both the subcode synchronization pattern detection output SCP and the block synchronization pattern detection output BP, whose timings have been aligned in this manner, are supplied to a two-input OR gate 50. therefore,
This OR gate 50 takes the logical sum of the two supplied signals, and outputs the output from the output terminal 60. That is, the output from this output terminal 60 is used as a sector synchronization signal in the reproduction apparatus of this embodiment. Note that the data + parity in the main data is output from the output terminal 70.

Furthermore, if the detection of the subcode synchronization pattern performed by the encoder 10 of the playback apparatus of this embodiment is performed by ORing the subcodes S0 and S1 as has been done in the past, erroneous detection may occur. There is a risk that this may occur. Therefore, in the encoder 10 of this embodiment, S
The output of AND (logical product) of 0 and S1 or S
The detection output of only 1 (or only S0) is used as the detection output of the subcode synchronization pattern. This results in a disc-shaped extremely pinpoint S.
As long as no scratches or the like occur in the 0 or S1 portion, a subcode synchronization pattern detection output can be obtained.

From the above, in this embodiment, if the scratches on the optical disk are microscopic, the block synchronization pattern can be detected by interleaving. From the output BP it is possible to form a synchronization signal for the sector. Furthermore, in this embodiment, even if the block synchronization pattern cannot be detected due to large scratches or PLL misalignment, if the subcode synchronization pattern can be detected, the detection output SCP for the sector can be detected. synchronization signals can be formed. Therefore, even if there is a large scratch or a microscopic scratch, an accurate and reliable sector synchronization signal can be obtained.

The details of the decoder 10 will now be explained. This decoder 10 is capable of obtaining a detection output of a subcode synchronization pattern synchronized with the main data, and is preferably configured as shown in FIG. That is, in this FIG. 5, the input EF
The M signal is supplied to the latch circuit 11. Here, the clock input terminal of the latch circuit 11 is connected to a recovered clock (for example, an output VC from a voltage controlled oscillator (VCO)).
A phase detection circuit (PDO) 30 that detects the phase of the input EFM signal based on the OI) and a PLL circuit 3 as an external circuit.
A PLL system clock (EFM bit clock) formed by a loop consisting of 1 and 1 is supplied. The output of this latch circuit 11 is sent to an edge detection circuit 12, and edge information from the edge detection circuit 12 is sent to a 23-bit shift register. This shift register 13
has an output for each stage, and detects a frame synchronization pattern (ie, EFM synchronization signal) using all 23 bits. This allows the decoder to be synchronized. Note that the PLL circuit 31 is connected to the decoder 1.
It is also possible to have a configuration including the value within 0.

The 23-bit shift register 13 outputs 14 bits of data and sends it to the EFM demodulation circuit 14. The EFM demodulation circuit 14 has a terminal 9.
A crystal timing generation circuit 19 operates based on an external clock supplied from a crystal oscillator in an external circuit via
A crystal clock is supplied from therefore,
The EFM demodulation circuit 14 performs a process of converting (demodulating) the 14-bit data into normal 8-bit data based on this crystal clock. This 8-bit data is sent to RAM15. Note that the crystal oscillator described above may also be included in the decoder 10.

The write/read address data in the RAM 15 is generated based on the PLL system clock. That is, this write/read address data is R
It is generated by the AM address generation circuit 24, and the RAM address generation circuit 24 operates based on the timing clock from the PLL system timing generation circuit 23, which is supplied with the PLL system clock. . Therefore, the RAM address generation circuit 24 generates write/read address data for the RAM 15 based on the PLL system clock. Further, the read address data is the above-mentioned 8
This address data is used to decode bit data (decode error correction coding, that is, remove interleaving). Furthermore, this RAM 15 has the above 108EF
It is possible to store data for M frames, and therefore, the interleaved data can be obtained from the RAM 15 every 108 EFM frames.

Thereafter, the interleaved data is sent to the error detection/correction circuit 16. The error detection/correction circuit 16 performs a two-stage Reed-Solomon code (C1) in the CIRC in the CD format.
, C2) error detection and correction is performed. This error detection/correction circuit 16 also operates based on the crystal clock. When an error is detected in the error detection/correction circuit 16, the interpolation circuit 17 performs average value calculation or pre-hold processing on the data, and then the data is transferred to the parallel or serial data via the buffer 18. is output as This buffer 18 operates based on the crystal clock, and therefore, the output of the buffer 18 is based on the crystal clock.

[0026] Furthermore, the data of the subcode is the EFM
After being extracted by the demodulation circuit 14, it is sent to the subcode demodulation circuit 21. The subcode demodulation circuit 21 performs subcode demodulation, and then the signal is sent to a CRC check (cyclic code error detection) circuit 22 . After error detection is performed by the CRC check circuit 22, the data is sent to the buffer 18.

In this buffer 18, in addition to the synchronization explained in the above-described embodiment, the main data is further synchronized with the subcode data. To do something like this,
In this specific example, the following things are done.

That is, in this specific example, 1 is placed on the upper side of each of the specific 2 bytes of the main data following S0 or S1 (S1 in this specific example) of the subcode.
The bit is added and this bit is set to "1", and the subcode is synchronized based on these two bytes of "1" and the crystal clock. As the specific 2 bytes, as shown in FIG. I set the above “1” to the part-time job.

To accomplish this, the 14-bit output from the shift register 13 is also sent to the subcode sync detection circuit 20. The subcode sync detection circuit 20 detects S1 of the subcode. The detection output from this subcode sync detection circuit 20 is such that only the two bytes following S1 are "H". In other words, these two bytes correspond to L6n,A and L6n,B of the main data. Therefore, by sending the detection output of this subcode sync detection circuit 20 to the RAM 15, the RAM 15
1 bit is added to the upper side of the 8 bits of L6n, A and L6n, B which are supplied simultaneously with the detection output.
The most significant bit of these 9 bits is set to "1". Therefore, this RAM 15 is
A RAM with at least a 9-bit processing unit is used.

Furthermore, the subcode sync detection circuit 20
Also includes a circuit for taking countermeasures when, for example, the detection error in S1 occurs. That is, the subcode sync detection circuit 20 also detects the above S0, and if a detection error of the above S1 occurs at this time, the next subcode byte after the previously detected S0 is detected. (i.e., the subcode byte having S1 above), the subcode sync detection circuit 2 described above
It is designed to output "H" which corresponds to the detection output from 0. Furthermore, when both S0 and S1 are in error, the interpolated output (from the circuit 20 described above) is generated 13.3 ms (one frame) after the timing based on the output before the occurrence of this error, that is, S0 or S1 detected in the previous frame. It is designed to output "H" corresponding to the detection output of .

Here, in the case of the above L6n that comes once every 13.3 ms, the data supplied to the 9-bit RAM 15 will have "1" at the top, but in this specific example, In the RAM 15, CIRC decoding processing similar to the conventional one is performed in this unit. That is, the interleaving is restored in units of 9 bits. The output of this RAM 15 is sent to the buffer 18 via the error detection/correction circuit 16 and the interpolation circuit 17.

Furthermore, in the buffer 18 of this specific example,
A sync bit detection circuit 18a is arranged. This sync bit detection circuit 18a detects L6n, A and L6n of 2 bytes of the main data if "1" is set in the most significant bit (sync bit) of the output of the RAM 15.
, B, that is, logic that outputs "H" over one period of the clock LRCK for switching the L and R channels shown in FIG. Therefore, the output of the sync bit detection circuit 18a is used as the subcode synchronization signal output (SBSY in FIG. 6). Note that this subcode synchronization signal output SBSY becomes the detection output SCP of the subcode synchronization pattern via the delay circuit 40.

Therefore, in the buffer 18, the main data is read based on the crystal clock, and the shift clock is raised in response to the synchronization signal output SBSY of the subcode shown in FIG. , by reading the data of the subcode from the CRC check circuit 22, the Q data (SUBQ) of the subcode and the SUBQ can be read out from the CRC check circuit 22.
It becomes possible to read the data (CRCF) etc. The subcode synchronization signal output SBSY is output from the terminal 3, the subcode Q data SUBQ is output from the terminal 4, and the main data is output from the terminal 6.

Furthermore, the crystal timing generation circuit 19 outputs the clock LRCK for switching the L and R channels via the terminal 7, and the system clock SCK is output via the terminal 8. There is.

Note that FIG. 6 shows the decoder 10 of this specific example.
It shows the signal waveform of each part of LR.
Main data is output in synchronization with CK and SCK. Further, the subcode synchronization signal output SBSY is output in synchronization with, for example, the above LRCK, and is output from a certain EF of the above S1.
When the data of L6n at the beginning of M frame is output, L
It is output over one period of the above LRCK of 6n and R6n. Further, the above SUBQ and CRCF are read by an external clock SQCK supplied from the terminal 5.

As described above, in the present example decoder 10, one bit is added to the most significant part of each of the two bytes of specific main data following S1 or S0 of the subcode, and "1" is set in this bit. , convert this into 9-bit R
After writing/reading to/from AM15 and deinterleaving,
Since this most significant "1" is detected and the subcode synchronization signal output SBSY is obtained based on this,
Main data and subcode can be synchronized. Furthermore, since the buffer 18 operates based on a crystal clock, the main data and subcode are synchronized with this crystal clock. For this reason, when the main data is divided at the timing of the subcode, even if jitter exists, the main data will not overlap or be corrupted. That is, even if the main data is divided at the timing of this subcode, reproducible division points can be obtained. Furthermore, in a system that compensates for the case where data cannot be obtained due to a reading error or defocus of the pickup, etc., the data recorded in the RAM 15 is read out in bursts at double speed, the main data There is no such thing as missing or overlapping. Furthermore, reading of the main data and auxiliary information can be done in the same manner as in the past. For this reason, even if vibrations are applied to the playback device during playback, for example, skipping of the sound will not occur, making it possible to obtain a playback device with high earthquake resistance.

In this specific example, as described above, a detection output of a subcode synchronization pattern is obtained when the first sample value L6n of an EFM frame in which a subcode S1 exists as auxiliary information is output. However, S1 of this subcode and L6n of the first sample value may be other values as long as they are reproducible.

Further, in the above-described specific example, the most significant bit (L6n) of the main data is used as a flag for outputting the subcode synchronization signal, but in addition, for example, when controlling the readout of the RAM 15, the above-mentioned It is also conceivable to use the byte of the interpolation pointer during interpolation in the interpolation circuit 17. That is, in this interpolation circuit 17, there is an interpolation pointer indicating that the sample value is an interpolation value, and normally only one bit out of eight bits is used. For this reason, this unused 7
One of the bits can be used as a flag for outputting the subcode synchronization signal.

Furthermore, it is also possible to configure the subcode and the subcode synchronization pattern detection output to be switchable between a mode in which the subcode and the subcode synchronization pattern detection output are output at the same timing as before, and a mode in which they are output at the timing as in this specific example. It is.

[0040]

As described above, in the recording medium of the present invention, the sector-by-sector synchronization pattern is recorded while maintaining a predetermined positional relationship with respect to the synchronization pattern of the auxiliary information. In a media playback device, the synchronization pattern detection output for each sector and the detection output of the auxiliary information synchronization pattern are synchronized and logically summed, and the output is used as the sector synchronization signal. Even if there is a large scratch or dust on the recording surface of the recording medium that exceeds the error correction capability during error correction decoding, or the PLL is out of alignment, it is possible to obtain an accurate sector synchronization signal, and even if there is a small scratch etc., it is possible to obtain a sector synchronization signal. Therefore, even if an error exceeding the capability of the error correction code occurs in a recording medium such as a CD-ROM, a sector synchronization signal can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a signal format recorded on a recording medium according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a playback device according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining CIRC.

FIG. 4 is a diagram showing a detection output of a subcode synchronization pattern, a detection output of a block synchronization pattern, and a fixed pattern.

FIG. 5 is a block diagram showing details of a decoder.

FIG. 6 is a waveform diagram showing signal waveforms of each part of the decoder.

FIG. 7 is a diagram showing a CD format.

FIG. 8 is a diagram showing a subcode frame.

FIG. 9 is a diagram showing a CD-ROM frame.

FIG. 10 is a diagram showing detection outputs of uncorrectable errors and block synchronization patterns.

[Explanation of symbols]

10...Decoder 40...Delay circuit 50...2 input OR gate

Claims (2)

[Claims] Claim 1: A format in which PCM data is subjected to error correction encoding processing and auxiliary information including a synchronization pattern is added, and instead of the PCM data, a synchronization pattern is generated in fixed sector units based on a predetermined data format. In a recording medium on which recording is performed in an extended format using data attached to the auxiliary information, the sector-by-sector synchronization pattern is recorded while maintaining a predetermined positional relationship with respect to the synchronization pattern of the auxiliary information. recording medium. [Claim 2] A format in which PCM data is subjected to error correction encoding processing and auxiliary information including a synchronization pattern is added is extended, and instead of the PCM data, a synchronization pattern is generated in fixed sector units based on a predetermined data format. A reproducing device for a recording medium that records a sector-based synchronization pattern while maintaining a predetermined positional relationship with respect to the auxiliary information synchronization pattern using the attached data, wherein the sector-based synchronization pattern is detected. A reproducing device for a recording medium, characterized in that the output and the detection output of the synchronization pattern of the auxiliary information are logically summed at the same timing, and the output is used as a synchronization signal for the sector.