JPH0425245A - Base band signal switching device - Google Patents
Base band signal switching deviceInfo
- Publication number
- JPH0425245A JPH0425245A JP12980890A JP12980890A JPH0425245A JP H0425245 A JPH0425245 A JP H0425245A JP 12980890 A JP12980890 A JP 12980890A JP 12980890 A JP12980890 A JP 12980890A JP H0425245 A JPH0425245 A JP H0425245A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- signal
- digital
- delay circuit
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 claims abstract description 16
- 238000012937 correction Methods 0.000 claims description 6
- 238000001514 detection method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はベースバンド信号切替器に関し、特に現用およ
び予備回線用無線通信受信機において、ディジタル処理
されたバイポーラ出力信号をビットの欠落なしに現用側
から予備側に切替えるベースパント信号切替器に関する
。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a baseband signal switching device, and particularly to a wireless communication receiver for working and protection lines, in which a digitally processed bipolar output signal can be used for working without missing bits. The present invention relates to a base punt signal switch that switches from the side to the standby side.
従来のベースバンド信号切替器は第2図のブロック図に
示すように、現用および予備のディジタル信号処理部I
A、2Aは、遅延量粗調整信号18.19の制御操作に
より、入力信号の遅延量1/2ビットづつ変化させるデ
ィジタル遅延回路6A、7Aと、遅延量微調整信号20
.21の制御操作により、さらに、入力信号の1/2ビ
ット以内の遅延量の微調整を行う微調整用アナログ遅延
回路8A、9Aと、微調整用アナログ遅延回路8A、9
Aの出力信号をユニポーラからバイポーラに変換するコ
ンパレータであるU/BCONV10.11を有する。As shown in the block diagram of FIG. 2, a conventional baseband signal switch has a working and standby digital signal processing unit
A and 2A are digital delay circuits 6A and 7A that change the delay amount of the input signal by 1/2 bit by control operation of the delay amount coarse adjustment signals 18 and 19, and a delay amount fine adjustment signal 20.
.. 21, further fine adjustment analog delay circuits 8A, 9A, which perform fine adjustment of the delay amount within 1/2 bit of the input signal, and fine adjustment analog delay circuits 8A, 9.
It has U/BCONV10.11 which is a comparator that converts the output signal of A from unipolar to bipolar.
切換部5は、現用および予備の各ディジタル信号処理部
IA、2Aの出力に接続され、現用および予備のバイポ
ーラ信号の位相差を検出し、モニタ電圧を出力する位相
比較器13と、バイポーラ信号の位相差が、あるしきい
値(例えば1/4ビット)より少ない場合には、切M
!17 W器4の切替信号により、ビットの欠落なしに
現用および予備の切替えを行う高速スイッチ12とを有
している。The switching unit 5 is connected to the outputs of the working and standby digital signal processing units IA and 2A, and includes a phase comparator 13 that detects the phase difference between the working and standby bipolar signals and outputs a monitor voltage, and a phase comparator 13 that detects the phase difference between the working and standby bipolar signals and outputs a monitor voltage. If the phase difference is less than a certain threshold (for example, 1/4 bit), the M
! It has a high-speed switch 12 that performs switching between the current and standby modes without missing any bits in response to the switching signal from the 17W unit 4.
今、高速スイッチ12が現用側を選択している場合に、
現用と予備とのバイポーラ出力信号の位相差が1/4ビ
ット以上である場合には、待機中の予備側回線のディジ
タル信号処理部2Aの位相差を補正するために、遅延量
粗調整信号19及び遅延量微調整信号21を位相比較器
13の出力に取り付けられた調整用測定器17のモニタ
電圧を計測しながら、1/4ビット以下の位相差となら
るように調整する。その後に高速スイッチ12を予備側
に切替えてビットは欠落のない切替えを行う、高速スイ
ッチ12が予備側を選択している場合には、前述と同様
の趣旨でディジタル信号処理部IAの方を調整すること
により、予備側から現用側に切替えてもビットは欠落の
ない切替えを行うことができる。バイポーラ信号の位相
差が1/4ビット以下の時、ビットの欠落なしで切替え
可能としたが、実際にはデータとタロツクのタイミング
の条件により調整条件が設定される。If the high-speed switch 12 is currently selecting the active side,
When the phase difference between the bipolar output signals between the working and protection lines is 1/4 bit or more, the delay amount coarse adjustment signal 19 is sent to correct the phase difference of the digital signal processing unit 2A of the standby protection side line. The delay amount fine adjustment signal 21 is adjusted so that the phase difference is 1/4 bit or less while measuring the monitor voltage of the adjustment measuring device 17 attached to the output of the phase comparator 13. After that, switch the high-speed switch 12 to the standby side to perform switching without missing bits. If the high-speed switch 12 selects the standby side, adjust the digital signal processing unit IA in the same way as described above. By doing so, it is possible to perform switching without missing bits even when switching from the backup side to the working side. When the phase difference of the bipolar signal is 1/4 bit or less, switching is possible without missing bits, but in reality, adjustment conditions are set depending on the timing conditions of data and tarok.
上述した従来のベースバンド信号切替器では、ディジタ
ル信号処理部の出力信号の位相差がある値以下となるよ
うに、操作者が位相比較器のモニタ電圧を調整用測定器
17により計測しながら予備側あるいは現用側のディジ
タル信号処理部を調整しなければならないので、調整に
時間かがかり、又、パネル交換などのメンテナンスのた
びに再調整しなければならないという欠点がある。In the above-mentioned conventional baseband signal switching device, the operator measures the monitor voltage of the phase comparator with the adjusting measuring device 17 and performs a preliminary check so that the phase difference between the output signals of the digital signal processing section is below a certain value. Since it is necessary to adjust the digital signal processing section on the side or the current side, the adjustment takes time, and there are also disadvantages in that readjustment must be performed every time maintenance such as panel replacement is performed.
本発明のベースバンド信号切替器は、ディジタル入力信
号をビット単位で遅延補正を行うディジタル遅延回路と
、前記ディジタル遅延回路の信号を受けてさらに1ビッ
ト単位以内の1/N(Nは4以上の整数)ビットごとに
遅延補正を行う微調整用遅延回路と、前記微調整用遅延
回路出力のユニポーラ信号をバイポーラ信号に変換する
U/’Bコンバータとを有するディジタル信号処理部を
現用および予備回線側にそれぞれ備え、前記現用および
予備回線側のディジタル信号処理部のいずれかを切替制
御器の制御により切り替える高速スイッチを有する。The baseband signal switching device of the present invention includes a digital delay circuit that performs delay correction on a digital input signal bit by bit, and a digital delay circuit that receives a signal from the digital delay circuit and further converts the signal to 1/N (N is 4 or more) within 1 bit unit. (Integer) A digital signal processing unit having a fine adjustment delay circuit that performs delay correction for each bit and a U/'B converter that converts the unipolar signal output from the fine adjustment delay circuit into a bipolar signal is installed on the working and protection line sides. and a high-speed switch for switching between the digital signal processing units on the working and protection line sides under the control of a switching controller.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のブロック図である。現用お
よび予備のディジタル信号処理部1゜2は現用回線、予
備回線の入力端子14.15の入力信号を後述する遅延
量制御部3からの遅延量粗調整信号18A、19Aによ
り、ディジタル遅延回路6または7の遅延量を172ビ
ットステツプで変化させ、同じく遅延量制御部3からの
遅延量微調整信号2OA、21Aにより微調整用アナロ
グ遅延回路8または9によりさらに1/2ビット以内の
遅延量の微調整を行う。U/BCONV10.11は従
来例と同様にユニポーラ信号をバイポーラ信号に変換す
る。切替部5の位相比較器13はアナログ掛算器で、現
用、予備の各ディジタル信号処理部1,2のバイポーラ
出力信号の位相差を検出し、その検出信号を遅延量制御
部3に出力する。又、高速スイッチ12は半導体スイッ
チであり、現用、予備の各バイポーラ出力信号の位相差
があるしきい値(例えば1/4ビット)以下の場合にビ
ットの欠落なしに出力を切替えることが可能なスイッチ
である。FIG. 1 is a block diagram of one embodiment of the present invention. The working and backup digital signal processing units 1-2 convert the input signals of the input terminals 14 and 15 of the working line and the protection line into the digital delay circuit 6 using delay amount rough adjustment signals 18A and 19A from the delay amount control unit 3, which will be described later. Alternatively, the delay amount of 7 is changed in 172-bit steps, and the delay amount is further adjusted within 1/2 bit by the fine adjustment analog delay circuit 8 or 9 using the delay amount fine adjustment signals 2OA and 21A from the delay amount control section 3. Make fine adjustments. U/BCONV10.11 converts unipolar signals into bipolar signals as in the conventional example. The phase comparator 13 of the switching section 5 is an analog multiplier that detects the phase difference between the bipolar output signals of the active and standby digital signal processing sections 1 and 2, and outputs the detected signal to the delay amount control section 3. Furthermore, the high-speed switch 12 is a semiconductor switch, and can switch the output without missing bits when the phase difference between the active and standby bipolar output signals is less than a certain threshold (for example, 1/4 bit). It's a switch.
ここで、遅延量制御部3は、切替制御器4の制御信号と
、位相比較器13の検出結果とにより待機中の回線側の
ディジタル信号処理部の遅延量を遅延量粗調整信号18
A、19A及び遅延量微調整化、号2OA、21Aの出
力を制御する。Here, the delay amount control section 3 adjusts the delay amount of the digital signal processing section on the line side in standby based on the control signal of the switching controller 4 and the detection result of the phase comparator 13 using a delay amount rough adjustment signal 18.
A, 19A and delay amount fine adjustment, outputs of Nos. 2OA and 21A are controlled.
例えば、高速スイッチ12が、現用側を選択していて、
現用、予備のバイポーラ出力信号の位相差が1/4ビッ
トを超えている場合には、遅延量制御部3は、遅延量微
調整信号により、微調整用アナログ遅延回路9を制御し
て、位相差が最小となるようにする。この時の位相差が
1/4ビット以内であれば、その遅延量を保持し、そう
でなければ、遅延量粗調整信号によりディジタル遅延回
路7を制御し、遅延量を1/2ビットシフトしたのち、
さらに遅延量微調整信号により微調整用アナログ遅延回
路9を制御して、位相差を最小となるようにし、この時
の位相差が1/4ビット以内であれば、その遅延量を保
持し、そうでなければ、上記の如く、ディジタル遅延回
路7及び微調整用アナログ遅延回路9の制御を繰り返し
て位相差を1/4ビット以内に合わせ、その遅延量を保
持する6位相調整を行った後の状態の時には、高速スイ
ッチ12を現用側から予備側に切替えてもビットは欠落
しない。同様に高速スイッチ12が予備側を選択してい
ても同じ手順で位相調整を行うことにより、予備側から
現用側へ切替えてもビットが欠落しないことは明白であ
る。For example, if the high-speed switch 12 selects the active side,
When the phase difference between the current and standby bipolar output signals exceeds 1/4 bit, the delay amount control section 3 controls the fine adjustment analog delay circuit 9 using the delay amount fine adjustment signal to adjust the phase. The phase difference should be minimized. If the phase difference at this time was within 1/4 bit, the delay amount was held; otherwise, the digital delay circuit 7 was controlled by the delay amount rough adjustment signal, and the delay amount was shifted by 1/2 bit. after,
Furthermore, the analog delay circuit 9 for fine adjustment is controlled by the delay amount fine adjustment signal to minimize the phase difference, and if the phase difference at this time is within 1/4 bit, the delay amount is maintained, If not, as described above, after repeating the control of the digital delay circuit 7 and the fine adjustment analog delay circuit 9 to adjust the phase difference to within 1/4 bit, and performing 6 phase adjustments to maintain the delay amount. In this state, no bits are lost even if the high-speed switch 12 is switched from the working side to the standby side. Similarly, even if the high-speed switch 12 selects the protection side, by performing phase adjustment in the same procedure, it is clear that no bits will be lost even when switching from the protection side to the working side.
以上説明したように本発明は、現用側回線及び予備側回
線のバイポーラ出力信号の位相差を検出し、現用側回線
あるいは予備側回線の遅延量の差を自動的に調整するこ
とにより、人手による操作が不要となり、かつ、操作者
が確認するための調整用測定器も不要となる効果がある
。したがって操作基のメンテナンスの時間も短縮できる
効果がある。As explained above, the present invention detects the phase difference between the bipolar output signals of the working line and the protection line, and automatically adjusts the difference in the amount of delay between the working line and the protection line. This has the effect that no operation is required, and there is no need for an adjustment measuring device for the operator to confirm. Therefore, there is an effect that the maintenance time for the operating panel can also be shortened.
第1図は本発明の一実施例のブロック図、第2図は従来
のベースバンド信号切替器のブロック図である。
1.2.LA、2A・・・ディジタル信号処理部、3・
・・遅延量制御部、4・・・切替制御器、5・・・切替
部、6,7.6A、7A・・・ディジタル遅延回路、8
.9.8A、9A・・・微調整用アナログ遅延回路、1
0.11・・・U/BCONV、12・・・高速スイッ
チ、13・・・位相比較器、14・・・現用側入力端子
、15・・・予備側入力端子、16・・・出力端子。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional baseband signal switch. 1.2. LA, 2A...Digital signal processing section, 3.
...Delay amount control unit, 4...Switching controller, 5...Switching unit, 6, 7.6A, 7A...Digital delay circuit, 8
.. 9.8A, 9A...Analog delay circuit for fine adjustment, 1
0.11... U/BCONV, 12... High speed switch, 13... Phase comparator, 14... Working side input terminal, 15... Standby side input terminal, 16... Output terminal.
Claims (1)
ディジタル遅延回路と、前記ディジタル遅延回路の信号
を受けてさらに1ビット単位以内の1/N(Nは4以上
の整数)ビットごとに遅延補正を行う微調整用遅延回路
と、前記微調整用遅延回路出力のユニポーラ信号をバイ
ポーラ信号に変換するU/Bコンバータとを有するディ
ジタル信号処理部を現用および予備回線側にそれぞれ備
え、前記現用および予備回線側のディジタル信号処理部
のいずれかを切替制御器の制御により切り替える高速ス
イッチを有するベースバンド信号切替器において、 前記現用および予備回線側のディジタル信号処理部の相
互の出力信号の遅延位相差を検出する位相比較器と、前
記遅延位相差の情報と前記切替制御器から入力される現
在待機中の回線の情報とを入力し、待機中回線のディジ
タル信号処理部に遅延量粗調整信号および遅延量微調整
信号の制御信号を送出する遅延量制御部とを有すること
を特徴とするベースバンド信号切替器。 2、前記ディジタル遅延回路が前記遅延量粗調整信号を
受けて1ビット単位の遅延補正を自動的に行い、引き続
き前記微調整用遅延回路が前記遅延量微調整信号を受け
て前記高速スイッチがビット欠落のない切替えを行うし
きい値である1/Nビットごとの遅延補正を自動的に行
うことを特徴とする請求項1記載のベースバンド信号切
替器。[Claims] 1. A digital delay circuit that performs delay correction on a digital input signal in units of bits, and 1/N (N is an integer of 4 or more) within 1 bit unit after receiving the signal of the digital delay circuit. A digital signal processing unit having a fine adjustment delay circuit that performs delay correction for each bit and a U/B converter that converts a unipolar signal output from the fine adjustment delay circuit into a bipolar signal is provided on the working and protection line sides respectively. , a baseband signal switching device having a high-speed switch that switches between the digital signal processing units on the working and protection line sides under the control of a switching controller, wherein mutual output signals of the digital signal processing units on the working and protection line sides are switched. A phase comparator detects the delay phase difference of A baseband signal switching device comprising: a delay amount control section that sends out control signals of a coarse adjustment signal and a delay amount fine adjustment signal. 2. The digital delay circuit receives the delay coarse adjustment signal and automatically performs delay correction in 1-bit units, and then the fine adjustment delay circuit receives the delay amount fine adjustment signal and the high-speed switch corrects the bit. 2. The baseband signal switching device according to claim 1, wherein delay correction is automatically performed for every 1/N bit, which is a threshold value for switching without loss.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12980890A JPH0425245A (en) | 1990-05-18 | 1990-05-18 | Base band signal switching device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12980890A JPH0425245A (en) | 1990-05-18 | 1990-05-18 | Base band signal switching device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0425245A true JPH0425245A (en) | 1992-01-29 |
Family
ID=15018737
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12980890A Pending JPH0425245A (en) | 1990-05-18 | 1990-05-18 | Base band signal switching device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0425245A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2427086A (en) * | 2005-06-08 | 2006-12-13 | Intel Corp | Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner |
-
1990
- 1990-05-18 JP JP12980890A patent/JPH0425245A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2427086A (en) * | 2005-06-08 | 2006-12-13 | Intel Corp | Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner |
GB2427085A (en) * | 2005-06-08 | 2006-12-13 | Zarlink Semiconductor Ltd | Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner |
GB2427086B (en) * | 2005-06-08 | 2007-04-25 | Intel Corp | Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner |
US7606332B2 (en) | 2005-06-08 | 2009-10-20 | Intel Corporation | Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner |
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