JPH04249372A - Mos type field effect transistor and fabrication thereof - Google Patents

Abstract

PURPOSE:To prevent soft errors of 0 1 to be caused when a punch through and alpha-rays penetrate through a source-drain by a method wherein an insulating layer separating a source diffusing layer from a drain diffusing layer is formed in a narrower band form than a channel length at a place which is deeper than an invert layer in which a channel of a semiconductor substrate is formed. CONSTITUTION:After a V-form small groove 2 is opened in a P type silicon substrate 1, a SiO23 grows on the entire surface by a CVD method. Next, by etching the SiO23, the small groove 2 is filled with the SiO23. Next, after a polysilicon 4 grows on the entire surface and is heat-treated by a laser-anneal or the like, whereby the polysilicon 4 is made a single crystal. Then, after impurities for controlling a threshold value voltage is ion-implanted, a gate oxidizing film 5 and a polysilicon gate electrode 6 is formed, arsenic is ion- implanted, and a source 7a and a drain 7b are formed to form an element part.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor, and more particularly to the structure of a substrate between source and drain electrodes.

0002

[Prior Art] A MOS field effect transistor (hereinafter referred to as MOSFET) according to the prior art is first shown in FIG.
) as shown in FIG. 4B, secondly as shown in FIG. 4B, as shown in FIG. As shown in FIG.
IMOX (Separation by Implan)
There are three types of ted Oxygen) structures.

[0003] As described above, the conventional MOSFET has a structure in which an insulating layer exists over the entire surface or no insulating layer exists under the source 7a, drain 7b, and channel.

0004

As MOSFETs have been miniaturized and their gate lengths have reached the submicron order, the following two problems have arisen.

The first problem is the short channel effect due to the shorter gate length. Punch-through current has been prevented by increasing the impurity concentration of the substrate, but this has led to problems such as increased capacitance and deterioration of circuit operating characteristics.

The second problem is that, as shown in FIG. 5, when α particles are incident on the source 7a and the drain 7b, an inversion error from "0" to "1" occurs in the MOSFET. . As the gate length becomes shorter, this source-drain penetration becomes more noticeable.

When α rays penetrate from the source 7a side to the drain 7b side, funneling occurs.
) phenomenon, electrons are emitted from the source immediately after incidence (approximately 1 picosecond) and are collected at the drain. A current proportional to the logarithm of the drain voltage flows along the trajectory.

[0008] The potential disturbed by the α rays gradually recovers in 1 to 10 picoseconds after the incidence of the α rays. The current that continues to flow is considered to be due to lateral NPN operation.

[0009] Further, after 10 picoseconds, the electric field due to funneling disappears, and the electrons injected into the substrate move by diffusion, and are collected at the source and drain.

[0010] If the charge entering and leaving the source (assuming the charge to be collected is positive) is Qs, then Qs = -Q1 -Q2 +
If Qs < 0 at Q3, charge is released from the source. Here, Q1 is electron emission within 1 picosecond after α-ray incidence, Q
2 is electron emission in 1-10 ps, Q3 is approximately 1
The charge due to electron collection of the source for 0 ps is shown.

[0011] While the conventional soft error is a "1" → "0" reversal, this soft error is a "0" → "1" reversal that becomes more noticeable as the effective channel length of the MOSFET becomes shorter.
This is a reversal error.

In actual devices, α rays are generated from trace amounts of U (uranium) and Th (thorium) contained in mold resin, Al wiring, high melting point metal wiring, and the like. The angle at which α rays enter the device surface is random, and the finer the pattern, the more the α rays enter the device surface.
” Soft errors become a problem. This defect occurs not only in the MOSFET connected to the memory cell node but also in the MOSFET forming the peripheral circuit.

[0013]

Means for Solving the Problems The MOS field effect transistor of the present invention has an insulating layer formed deeper than the channel inversion layer to isolate the source and drain.

[0014]

[Embodiment] As the first embodiment of the present invention, an N-type MOSFE
T will be explained with reference to FIGS. 1(a) to (e).

First, as shown in FIG. 1(a), a surface opening width of 0.2 to 0.3 μm and a depth of 0 is formed in a P-type silicon substrate 1.
．． A small V-shaped groove 2 of 2 to 0.3 μm is made.

Next, as shown in FIG. 1(b), C is applied to the entire surface.
SiO2 3 is grown using a VD method or the like.

Next, as shown in FIG. 1(c), SiO2
SiO2 is formed in the small groove 2 by etching back 3.
3 is satisfied.

Next, as shown in FIG. 1D, after growing polysilicon 4 to a thickness of 0.1 μm over the entire surface, polysilicon 4 is made into a single crystal by heat treatment such as laser annealing.

Next, as shown in FIG. 1E, impurities for controlling the threshold voltage are ion-implanted, a gate oxide film 5 and a polysilicon gate electrode 6 are formed, and arsenic is ion-implanted to form the source. 7a and a drain 7b are formed to complete the element section.

[0020] Width 0.2 μm and depth 0.2 μm in Fig. 1(a)
The first method for forming the small grooves 2 of m is the EB direct writing method, but there are also easier methods as follows.

First, as shown in FIG. 2A, SiO2 3 is etched using the photoresist 14 as a mask to form an opening with a width of 0.5 μm.

Next, as shown in FIG. 2(b), after removing the photoresist 14, new SiO2 3a is grown by CVD to a thickness of just 0.15 μm on the sidewall of the opening of the SiO2 3. let

Next, as shown in FIG. 2(c), the SiO2 3a is etched back by anisotropic dry etching.

Small grooves can be formed in the P-type silicon substrate 1 by anisotropic dry etching using the SiO2 3, 3a as a mask.

When the opening width of the small groove 2 is wide, there is also a method of digging the groove a little deeper, removing the oxide films 3 and 3a after thermal oxidation, and flattening the surface before growing the polysilicon 4. .

By sandwiching the insulating film made of SiO 2 3 between the source 7a and the drain 7b, the electric field near the drain 7b is relaxed, especially when the drain voltage is high, and the shape of the depletion layer is different, making it different from the conventional MOSFET. short channel effects are less likely to occur compared to Alpha rays are source 7
Even if it penetrates into the drain 7b from the source 7a, the insulating layer 3 causes less disturbance in the potential that occurs after the α rays are incident, and the charge emitted from the source 7a is similar to that of a normal MOSFET.
It has the advantage of being substantially less than ET. In this way, it has been found that this method is effective against soft errors caused by source-drain penetration and punch-through, which is one of the short channel effects.

The shape of the insulating film sandwiched between the source and drain is not limited to the wedge shape of this embodiment, but various shapes can be considered.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3(a) to 3(d).

First, as shown in FIG. 3(a), after forming SiO2 8 with a thickness of 25 nm on a P-type silicon substrate 1, tungsten 9 with a thickness of 500 to 600 nm is deposited, and then an opening is formed by lithography. .

Next, as shown in FIG. 3(b), the P-type silicon substrate 1 is maintained at 500° C. and oxygen is accelerated with an energy of 1.
00-150keV, implantation amount (dose) approximately 2×1018
After cm-2 hot ion implantation, tungsten 9 is removed. Next, annealing at 1100 to 1200℃ is performed.
Form iO2 10. Next, apply polysilicon 4 to the entire surface.
grow.

Next, as shown in FIG. 3(c), the polysilicon 4 is made into a single crystal by laser annealing, and then impurities for controlling the threshold voltage are ion-implanted to form the gate oxide film 5 and the polysilicon gate electrode. form 6.

Next, as shown in FIG. 3(d), arsenic ions are implanted to form a source 7a and a drain 7b, thereby completing the element section.

By performing rotational ion implantation when ion-implanting oxygen, a trapezoidal shape of SiO that spreads in the depth direction is formed.
2 can be formed.

[0034]

Effects of the Invention: Since an insulating layer is provided to isolate the source and drain of the MOSFET, punch-through (short channel effect) is prevented, and the change from "0" to "1" that occurs when α rays penetrate the source and drain is prevented. ” is effective in preventing soft errors.

The shape (size, shape, depth) of the insulating layer is MO
It can be optimized for each SFET.

Since a new silicon layer is formed to serve as the channel layer, there is an advantage that it is not affected by surface damage that occurs in the step of forming an insulating layer. Furthermore, by using an MBE apparatus or the like, even an extremely thin silicon layer can be formed on the insulating layer with high precision.

[Brief explanation of the drawing]

FIG. 1 is a perspective view and a sectional view showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method of forming small grooves according to the present invention.

FIG. 3 is a sectional view showing a second embodiment of the invention.

FIG. 4 is a cross-sectional view of a MOSFET according to the prior art.

FIG. 5 is a cross-sectional view showing a "0" → "1" soft error due to source-drain penetration.

[Explanation of symbols]

1 P-type silicon substrate 2 Small groove 3,3a　　　SiO2 4 Polysilicon 5 Gate oxide film 6 Gate polysilicon 7a Source 7b Drain 8 SiO2 9 Tungsten 10　　　SiO2 11 Insulating substrate 12 Field oxide film 13 Buried oxide film 14 Photoresist

Claims (6)

[Claims] 1. A MOS type field effect transistor in which an insulating layer is formed in a strip shape narrower than the channel length to isolate a source diffusion layer and a drain diffusion layer in a region deeper than an inversion layer in which a channel is formed in a semiconductor substrate. 2. The MOS field effect transistor according to claim 1, wherein the upper end of the insulating layer is shallower than the lower end of the source-drain diffusion layer. 3. The MOS field effect transistor according to claim 1, wherein the lower end of the insulating layer is deeper than the lower end of the source-drain diffusion layer. 4. The MOS field effect transistor according to claim 1, wherein the insulating layer is made of one or more of silicon oxide, silicon nitride, tantalum oxide, and an organic insulator. 5. The method according to claim 1, comprising the steps of forming an insulating layer in a predetermined shape on the semiconductor substrate, and depositing polysilicon with a thickness of 0.2 μm or less over the entire surface and then converting it into a single crystal. A method for manufacturing a MOS field effect transistor. 6. A step of forming an insulating layer inside the semiconductor substrate by implanting oxygen ions into a predetermined region of the surface of the semiconductor substrate, and depositing polysilicon with a thickness of 0.2 μm or less over the entire surface, and then simply The MO according to claim 1, comprising the step of crystallizing.
A method for manufacturing an S-type field effect transistor.