JPH0424657Y2 - - Google Patents

Description

[Detailed description of the invention] (1) Technical field of the invention This invention relates to a multi-input logic circuit using series-connected MOS transistors, and specifically aims to prevent differences in output response time depending on input conditions. That is.

(2) Background of the technology Address buffer sections, decoder sections, bit line control sections, etc. are installed around memory circuits, and the operating speeds of these sections all depend on the response time of the logic circuits used.

(3) Prior Art and Problems Figures 1 and 2 show a two-input NAND gate and a NOR gate using CMOS as simple examples of conventional logic circuits. The circuit of Fig. 1a has CMOS transistors T ₁ and T ₃ driven by one input IN ₁ and the other input IN ₂ .
Among CMOS transistors T ₂ and T ₄ , p-channel MOS transistors T ₁ and T ₂ serving as loads are connected in parallel,
And n-channel MOS transistor on the drive side
This is T ₃ and T ₄ connected in series. In this case, the problem is the response time for the output OUT to change from H (high) to L (low). In other words, the figure b
Input IN ₂ when input IN ₁ is H as shown in
When changes from L to H, the output OUT changes from H to L, but before this IN ₂ level change, IN ₁ = H,
When IN ₂ = L, transistors T ₂ and T ₃ are on, T ₂ and T ₄
is off, the connection point N _A between transistors T ₃ and T ₄ is charged to V _cc -V _th3 (V _th3 is the threshold level of T ₃ ). For this input IN ₂
switches from L to H to turn off transistor _T2 ,
Even if T ₄ is turned on, the output OUT will not become L (=V _ss ) until the charge at node N _A is discharged.
A time delay t ₁ occurs here.

On the other hand, when the input IN ₁ switches from L to H while the input IN ₂ is in the H state as shown in FIG. However, in the state where IN ₁ =L and IN ₂ =H, transistors T ₁ and T ₄ are on and T ₂ and T ₃ are off, so the node N _A is L (=V _ss ). For this reason
When IN ₁ switches from L to H, turning off transistor T ₁ and turning on T ₃ , the output OUT switches from H to L with only a slight time delay t ₂ without discharging the charge at node N _A .

The problem is not the presence or absence of response time itself, but the difference in response times t ₁ and t ₂ due to input conditions (in this case t ₁ > t ₂ )
This is what happens. This problem is a transistor
This is inherent in the configuration in which T ₃ and T ₄ are connected in series.
As shown in Figure 2a, T ₃ and T ₄ are p-channel MOS
The same applies to the case of using a transistor. However, in this case, it is a CMOS 2-input NOR gate, and the 2-input
The output OUT becomes H only when both IN ₁ and IN ₂ become L. The response time becomes a problem under the input condition where the output OUT changes from L to H, as shown in b.
When IN ₁ = L and IN ₂ switches from H to L, the node drops to V _th2 (threshold level of T ₂ )
A delay time t ₃ occurs at the output OUT in order to charge N _A to V _cc . This time t ₃ is like c IN ₂
When IN ₁ is switched from H to L with =L, this response time
Longer than _t4 .

The circuits shown in FIGS. 3a to 3d are conceivable as circuits that solve this problem of response time difference. FIG. 3a shows a two-input NAND gate. The two-input NAND gate in this example has two n-channels in the circuit shown in Figure 1a.
A series circuit consisting of MOS transistors T ₄₂ and T ₃₂ is added. This series circuit is n channel
MOS transistors T ₃₁ and T ₄₁ (these are shown in Fig. 1)
(equivalent to T ₃ and T ₄ ) in parallel. Transistors T ₃₁ and T ₃₂ are input IN ₁ , and transistors T ₄₁ and T ₄₂ are input IN _2.
are driven at the same time. Therefore, as shown in Figure 1b
When IN ₁ = H and IN ₂ = L, the transistor T ₂ ,
Since T ₃₁ is on and T ₁ and T ₄₁ are off, the potential at the connection point N _B between transistors T ₃₁ and T ₄₁ is (V _cc −
V _th31 ) is high, but since transistor T ₃₂ is on and T ₄₂ is off at the same time, their connection point N _C is
It has dropped to _Vss . For this reason, IN ₂ is changed from L to H.
When switched to , transistor T ₂ is turned off, transistor T ₄₂ is turned on, and the output OUT is quickly switched from H to L due to the influence of the node _NC on the low potential side. Conversely, when IN ₂ = H and IN ₁ is switched from L to H as shown in Figure 1c, node N _B is used as the low potential side, so
The response time in this case also remains unchanged. That is, under any input condition, the response time is unified to the shorter one corresponding to _t2 in FIG. 1c. FIG. 3b shows an example applied to a two-input NOR gate. Since the relationship between this example and FIG. 1A corresponds to the relationship between FIGS. 1A and 1B, the same parts are given the same reference numerals and detailed explanations will be omitted.
In this case, the transistors T ₃₁ , T ₃₂ , T ₄₁ ,
All T ₄₂ are p-channels.

FIG. 3c shows an example applied to a three-input NAND gate. A normal three-input NAND gate consists of three p-channel MOS transistors T ₁ , T ₂ ,
It is composed of three n-channel MOS transistors (for example, T ₃₁ , T ₆₁ , T ₄₁ ) connected in series with T ₅ , but in this example, three more n-channel MOS transistors T ₄₂ , T ₃₂ , T ₆₂ are connected in series. A series circuit consisting of 3
n-channel MOS transistors T ₆₃ , T ₄₃ ,
Add a series circuit consisting of T ₃₃ and connect T ₃₁ to _{T 33} to IN ₁
So, again, T ₄₁ ~ T ₄₃ with IN ₂ , and then T ₆₁ ~ _{T 63}
It is designed to be driven by IN ₃ . The operation in this case will be briefly explained. For example, IN ₁ = H, IN ₂
Assume a state where =H and IN ₃ =L. At this time, transistors T ₅ , T ₃₁ to T ₃₃ , and T ₄₁ to _{T 43} are on,
Since the others are off, the source side potentials of T ₃₁ and T ₄₂ (through T ₃₂ ) among the top transistors in each series circuit are high, and only the source side potential of T ₆₃ is low. That is, in a series circuit containing transistor T ₆₃
This is because T ₆₃ is off and both T ₄₃ and T ₃₃ are on. Therefore, when input IN ₃ switches from L to H, transistor T ₅ turns off and T ₆₃ turns on, the output
OUT quickly becomes L.

However, if the circuit concept of FIGS. 3a to 3c is extended directly to a multi-input logic circuit, a large number of transistors will be required.

FIG. 3d is an example of a four-input NAND gate using CMOS. In this case, the parallel transistor T ₁ ,
T ₂ and T ₅ are p-channel MOS driven by input IN ₄
T ₇ is added, further increasing the number of series circuits to 4, and each series circuit has an n-channel driven by IN ₄ .
MOS transistors T ₈₁ to T ₈₄ are inserted. still,
T ₃₄ , T ₄₄ , and T ₆₄ are transistors added to each series circuit due to the increase in the number of series circuits.
Driven by IN ₁ to _{IN 3} .

As is clear from the above examples, in CMOS, the number of parallel transistors (T ₁ , T _2, etc.) equal to the number of inputs n
, each requires a plurality (ideally n) of series circuits each consisting of transistors, the number of which is equal to the number of inputs n. For example, if there are n inputs, n+n ² transistors are required.

(4) Purpose of the invention The invention aims to eliminate the above-mentioned difference in response time due to input conditions by using a smaller number of transistors (both are on the high-speed side).

(5) Structure of the invention The above purpose is to provide a first series circuit consisting of n MOS transistors connected in series to receive each input signal in a logic circuit where the number of input signals n is 3 or more; A second series circuit formed by connecting n MOS transistors in series, and a parallel circuit formed by connecting n MOS transistors in parallel for receiving each input signal, between the first power supply line and the output terminal. The parallel circuit is connected to the first series circuit, and only the first series circuit and the second series circuit are connected in parallel between the second power supply line and the output end, and the first series circuit is closest to the output end.
An input signal of the MOS transistor is input to the MOS transistor closest to the second power supply line in the second series circuit, and the input signal of the MOS transistor is input to the MOS transistor closest to the output terminal in the second series circuit.
The problem is solved by a logic circuit characterized in that an input signal of a MOS transistor is input to a MOS transistor closest to the second power supply line in the first series circuit.

(6) Embodiment of the invention FIG. 4 is a circuit diagram showing an embodiment of the invention. This example outputs important ones among n inputs.
We focused on the fact that if the input is applied to the transistor closer to OUT, the same effect can be expected even with fewer series circuits. FIG. 4 shows an example of a 4-input NAND gate. In this example, input IN ₁ ,
This assumes that IN ₂ is important for response,
In this case, only two sets of series circuits are required. That is, the input
Both IN ₃ and IN ₄ are H, for example, IN ₁ = H, IN ₂ = L
If so, the transistors T ₃₁ , T ₆₁ , T ₈₁ ,
Since T ₈₂ , T ₆₂ , T ₃₂ , and T ₂ are on, in the series circuit on the left, the source potential of T ₃₁ is high through T ₆₁ and T ₈₁ , but in the series circuit on the right, the source of T ₄₂ is at a low potential. be. Therefore, when IN ₂ is switched from L to H, transistor T ₂ is turned off and T ₄₂ is turned on, so the output
OUT quickly becomes L.

The circuit shown in Figure 4 is a NAND gate circuit, but when applying the present invention to a NOR circuit, the vertical relationship is reversed around the line connected to the output OUT on the diagram.
All you have to do is swap the channel and n channel. Furthermore, the configuration of this invention using multiple sets of series circuits is CMOS.
Not limited to E/D type MOS or normal MOS
It can also be applied to logic circuits. The logic circuit of the present invention can be used for various purposes such as a predecoder in an address buffer section, or a logic gate in the first and second stages of a bit line control circuit.

(7) Effects of the invention As described above, according to the invention, the output response time of a logic circuit using a small number of transistors connected in series with MOS transistors driven by different inputs can be made uniform regardless of the input conditions. There are advantages that can be achieved.

[Brief explanation of the drawing]

1, 2, and 3 a to 3 d are explanatory diagrams of conventional logic circuits, and FIG. 4 is a circuit diagram showing an embodiment of the present invention. In the figure, _T31 to _T34 , _T41 to _T44 ... are MOS transistors connected in series, and _T1 , _T2 ... are load transistors.

Claims (1)

[Claim for Utility Model Registration] In a logic circuit in which the number n of input signals is 3 or more, a first series circuit formed by connecting n MOS transistors in series that receive each input signal; A second series circuit formed by connecting MOS transistors in series, and a parallel circuit formed by connecting n MOS transistors in parallel for receiving each input signal, and the parallel circuit is provided between the first power supply line and the output terminal. circuits are connected, only the first series circuit and the second series circuit are connected in parallel between the second power supply line and the output end, and the first series circuit is closest to the output end.
An input signal of the MOS transistor is input to the MOS transistor closest to the second power supply line in the second series circuit, and the input signal of the MOS transistor is input to the MOS transistor closest to the output terminal in the second series circuit.
A logic circuit characterized in that an input signal of a MOS transistor is input to a MOS transistor closest to the second power supply line in the first series circuit.