JPH04245439A - bipolar transistor - Google Patents

Abstract

PURPOSE:To provide a bipolar transistor whose collector breakdown strength is high, whose current gain is high and which is provided with a high-speed property regarding the bipolar transistor and especially regarding a heterobipolar transistor (HBT). CONSTITUTION:The title transistor is constituted in the following manner. A semiconductor layer (e.g. InGaAs) having a narrow forbidden band width on the side of a base is situated to be close to a semiconductor layer (e.g. InP) having a wide forbidden band width on the side of a collector. The semiconductor layer having the wide forbidden band width is composed of the following: a layer which comes into contact with the semiconductor layer having the narrow forbidden band width and which contains n-type impurities; a layer which is continued to it and which does not contain any impurities; and a layer which is continued to the layer and which contains the n-type impurities. The semiconductor layer having the narrow forbidden band width is composed of the following: a layer which comes into contact with the semiconductor layer having the wide forbidden band width and which contains P-type impurities; a layer which is continued to it and which does not contain any impurities; and a layer which is continued to it and which contains the p-type impurities.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to bipolar transistors, and more particularly to heterojunction bipolar transistors (HBTs) with improved collector structures.

0002

2. Description of the Related Art Heterojunction bipolar transistors (HBTs) using compound semiconductors are examples of active elements that have characteristics superior to conventional silicon-based bipolar transistors in terms of high speed and the like. The typical HBT is AlGaAs/GaAs, but from the viewpoint of improving high speed and reducing power consumption, In
I of AlAs/InGaAs, InP/InGaAs system
HBTs based on nGaAs are attracting attention.

FIG. 5 shows a conventional InAlAs/InGaA
FIG. 2 is an energy band diagram of an s-based HBT. In this figure, 21 is an emitter layer, 22 is a base layer, and 23 is a collector layer. In this HBT, as shown in this figure, InAlAs is used for the emitter layer 21, and InGaAs is used for the base layer 22 and collector layer 23. In this case, since the forbidden band width of InGaAs forming the collector layer is small and the ionization rate is high, there is a drawback that the collector breakdown voltage is low.

FIG. 6 also shows a conventional InP/InGaA
FIG. 2 is an energy band diagram of an s-based HBT. The symbols in this figure correspond to the symbols in FIG. This HBT
As shown in this figure, InP is used in the emitter layer.
The base layer is made of InGaAs, and the collector layer is made of InP. In this case, since the forbidden band width of InP is large and the ionization rate is small, the collector breakdown voltage is sufficiently high, but a barrier is created for electrons traveling from the base layer to the collector layer, resulting in a decrease in current gain and a reduction in high speed. There was a drawback that a decline occurred.

[0005] Conventionally, in view of the above drawbacks, FIG.
Proposals have been made to improve the HBT as shown in FIG. Before explaining a proposal for improving the HBT, for convenience of explanation below, the collector structure of the HBT is divided into regions and symbols are assigned to each region.

FIG. 7 is a schematic energy band diagram for explaining the structure of the HBT collector. In this figure, in order to label each part, only the magnitude relationship of the forbidden band width is shown, and the shape of the potential is not expressed. In the figure, I indicates the original base layer, VI indicates the original collector contact layer,
Areas II to V are inserted between them. The regions I, II, and III are made of a semiconductor with a small bandgap, such as InGaAs, and the regions IV, V, and VI are made of a semiconductor with a large bandgap, such as InP. Further, as will be explained later with examples, region I exhibits p-type conductivity, regions II and III exhibit i-type, n-type, and p-type conductivity, and region IV exhibits n-type conductivity. , region V indicates either n-type or i-type,
Region VI indicates n-type.

FIG. 8 shows a conventional improved InP/InG
FIG. 2 is an energy band diagram of an aAs-based HBT. This H
In BT, as shown in Figure 8, p-In
Between the GaAs base layer (I) and the n-InP collector contact layer (VI), the i-InGaAs layers (II, II
It has a structure sandwiching a layer I), an n-InP layer (IV), and an i-InP layer (V). In this conventional example, since InP with a low ionization rate is used for the collector layer, the collector breakdown voltage is high, and the n-InP layer (IV) at the heterojunction
As a result, the base of the conduction band of this layer is curved to reduce the thickness of the barrier, making it easier for electrons to pass through the barrier, allowing high current gain and high speed to be maintained.

[0008]

However, the conventional HBT shown in FIG. 8 is still not sufficient in terms of current gain and high speed. Therefore, an object of the present invention is to provide an HBT with high collector breakdown voltage, higher current gain, and higher speed than conventional techniques.

[0009]

[Means for Solving the Problems] In the bipolar transistor according to the present invention, a semiconductor layer with a narrow forbidden band width on the base side and a semiconductor layer with a wide forbidden band width on the collector side are adjacent to each other, and a semiconductor layer with a wide forbidden band width on the collector side is adjacent to each other. The semiconductor layer is composed of a layer containing an n-type impurity in contact with the semiconductor layer having a narrow forbidden band width, a layer containing no impurity following this, and a layer containing an n-type impurity following this, and the semiconductor layer has a narrow forbidden band width. Adopts a structure in which the wide semiconductor layer is composed of a p-type impurity-containing layer in contact with a wide band gap semiconductor layer, a subsequent layer containing no impurities, and a subsequent p-type impurity-containing layer. did.

0010

[Operation] As mentioned above, the collector is made of InGaAs/In.
Using a P heterojunction, making the InP side n-type, and InGaAs
By making the side i-, n-, or p-type, the electron barrier on the InP side can be reduced, and collector breakdown voltage and current gain can be improved, and high speed performance can be maintained.

[0011]

Embodiment (First Embodiment) FIG. 1 is an energy band diagram of a first embodiment of the present invention.

In this embodiment, as shown in this figure,
An i-InGaAs layer (I) is placed between the p-InGaAs base layer (I) and the n-InP collector contact layer (VI).
I), p-InGaAs layer (III), n-InP layer (
IV), it has a structure with an i-InP layer (V) sandwiched therebetween. This embodiment is based on the i-In in the conventional example shown in FIG.
GaAs layers (II, III), i-InGaAs layers (
II) and a p-InGaAs layer (III) divided into two.

In this example, since InP with a low ionization rate is used for the collector layer, the collector breakdown voltage is high, and the p-InGaAs layer (III) at the heterojunction
By curving the base of the conduction band of this layer downward, the barrier for electrons seen from the base layer side is lowered, making it easier for electrons to cross the barrier and maintain high current gain and high speed.

(Second Embodiment) FIG. 2 is an energy band diagram of a second embodiment of the present invention. As shown in this figure, in this embodiment, n(
or p)-InGaAs layer (II), p-InGaA
It has a structure sandwiching an s layer (III), an n-InP layer (IV), and an i-InP layer (V). This example is shown in Figure 1.
The i-InGaAs layer (II
) is changed to an n (or p)-InGaAs layer (II).

In this example, since InP with a low ionization rate is used for the collector layer, the collector breakdown voltage is high, and the n (or p)-InGaAs layer (I
By I), the base of the conduction band of this layer is curved downward to lower the electron barrier seen from the base layer side, making it easier for electrons to pass over the barrier, resulting in a high current gain and
High speed can be maintained.

In the above structure, if the InGaAs layer (II) at the heterojunction is i-type, when a large amount of electrons are injected, the width of the depletion layer at the base-collector junction is narrowed, and the apparent base This causes the so-called Kirk effect, in which the width increases and the cutoff frequency decreases, but as in this example, the InGaAs layer (II
) is n-type, even if a large number of electrons are injected, they are neutralized by the positive residual charges in the n-layer, and the depletion layer width is less likely to be narrowed, making it possible to effectively suppress the Kirk effect. .

(Third Embodiment) FIG. 3 is an energy band diagram of an HBT according to a third embodiment of the present invention. This figure shows the case where the collector structure of the present invention is applied to an HBT. In this figure, 3 is an n+ -InP layer, 4 is an i-
InP layer, 5 is n-InP layer, 6 is p-InGaAs layer, 7 is n-InGaAs layer, 8 is p+ -InGaAs
9 is an n-InP layer, and 10 is an n+-InP layer.

The above n+ -InP layer 3 is a collector contact layer, an i-InP layer 4, an n-InP layer 5,
The p-InGaAs layer 6 and the n-InGaAs 7 are layers constituting a collector structure, the p+-InGaAs layer 8 is a base layer, the n-InP layer 9 is an emitter layer, and the n+-InP layer 10 is an emitter contact layer. This embodiment employs the collector structure of the second embodiment.

FIG. 4 is a sectional view of an HBT according to a third embodiment of the present invention. In this figure, 1 is semi-insulating In
P substrate, 2 is i-InP buffer layer, 11 is AuGe/
The symbols correspond to those explained in FIG. 3, except that 12 is an Au collector electrode, 12 is a Ti/Pt/Au base electrode, and 13 is an AuGe/Au emitter electrode.

[0020] This HBT is manufactured, for example, as follows. 1. On a semi-insulating InP substrate 1, an i-InP buffer layer 2 (3000 Å) and an n+ −
InP collector contact layer 3 (concentration of n-type impurities such as Si and Se, 5 x 1018 cm-3, thickness 5000 Å),
i-InP layer 4 (2000 Å), n-InP layer 5 (1×
1018 cm-3, 300 Å), p-InGaAs layer 6
(P-type impurity concentration such as Zn, Be, etc. 5 x 1017 cm-3
, 500 Å), n-InGaAs layer 7 (5×1016c
m-3, 1000 Å), p+-InGaAs base layer 8 (1×1019 cm-3, 1000 Å), n-InP
Emitter layer 9 (5 x 1017 cm-3, 2000 Å),
n+ -InP layer emitter contact layer 10 (5×10
18 cm-3, 1000 Å).

2. After the growth of these layers, the emitter region is patterned by photolithography, and emitter mesa etching is performed until the base layer 8 is exposed. 3. Similarly, base mesa etching is performed until the collector contact layer is exposed. 4. The emitter layer 8 and collector layer 10 are made of AuG.
Ti/Pt/Au are deposited on the e/Au and base layers 8 to form electrodes, thereby completing the HBT. Note that although the above HBT has an emitter-up structure, a collector-up structure can also have the same effect. Further, in the above embodiment, InP is used as the emitter, but InAlAs can also be used in almost the same way.

[0022]

[Effects of the Invention] As explained above, according to the present invention,
HBT with high collector voltage resistance, high current gain, and excellent high speed performance
This technology is capable of providing a wide variety of technologies, making a significant contribution to this technical field.

[Brief explanation of the drawing]

FIG. 1 is an energy band diagram of a first embodiment of the present invention.

FIG. 2 is an energy band diagram of a second embodiment of the present invention.

FIG. 3 is an energy band diagram of an HBT according to a third embodiment of the present invention.

FIG. 4 is a sectional view of an HBT according to a third embodiment of the present invention.

[Fig. 5] Conventional InAlAs/InGaAs-based HBT
FIG.

FIG. 6 is an energy band diagram of a conventional InP/InGaAs-based HBT.

FIG. 7 is a schematic energy band diagram for explaining the structure of an HBT collector.

[Fig. 8] Conventional improved InP/InGaAs system H
It is an energy band diagram of BT.

[Explanation of symbols]

1 Semi-insulating InP substrate 2 i-InP layer 3 n+-InP layer 4 i-InP layer 5 n-InP layer 6 p-InGaAs layer 7 n-InGaAs layer 8 p+-InGaAs layer 9 n-InP layer 10 n+ -InP layer 11 AuGe/Au collector electrode 12 Ti/Pt/Au base electrode 13　AuGe/Au emitter electrode

Claims (4)

[Claims] Claim 1: A semiconductor layer with a narrow band gap on the base side and a semiconductor layer with a wide band gap on the collector side are adjacent to each other, and the semiconductor layer with the wide band gap is in contact with the semiconductor layer with a narrow band gap. It consists of a layer containing an n-type impurity, a subsequent layer containing no impurity, and a subsequent layer containing an n-type impurity, and the narrow bandgap semiconductor layer is formed into a wide bandgap semiconductor layer. 1. A bipolar transistor comprising a layer containing a p-type impurity in contact with a p-type impurity, a layer containing no impurity following this, and a layer containing a p-type impurity following this. 2. A semiconductor layer with a narrow band gap on the base side and a semiconductor layer with a wide band gap on the collector side are adjacent to each other, and the semiconductor layer with the wide band gap is in contact with the semiconductor layer with a narrow band gap. It consists of a layer containing an n-type impurity, a subsequent layer containing no impurity, and a subsequent layer containing an n-type impurity, and the narrow bandgap semiconductor layer is formed into a wide bandgap semiconductor layer. 1. A bipolar transistor comprising a layer containing a p-type impurity in contact with a p-type impurity, a layer containing an n-type or p-type impurity following this, and a layer containing a p-type impurity following this. [Claim 3] The narrow bandgap semiconductor is InGa.
3. The bipolar transistor according to claim 1, wherein the bipolar transistor is made of As. 4. The bipolar transistor according to claim 1, wherein the semiconductor having a wide forbidden band width is InP.