JPH04241468A - Electrically erasable non-volatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To embody further reduction and higher integration by reducing an erase gate occupancy area of an electrically erasable non-volatile semiconductor memory device (EEPROM) which is provided with a floating gate, a control gate, and an erase gate on an MOS type transistor device. CONSTITUTION:The sides of a floating gate FG are coated with an erasable insulation film 13, thereby forming a control gate CG and further forming an erase gate 15 on the side of the FG in a self-matching manner by way of the erasable insulation film 13. Since the erase gate is formed on the side of the floating gate, it is possible to reduce an occupancy area.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable nonvolatile semiconductor memory device (hereinafter referred to as an EEPROM) and a method of manufacturing the same. More specifically, the present invention relates to an EEPROM suitable for high integration and a manufacturing method thereof.

0002

2. Description of the Related Art Recently, among non-volatile semiconductor memory devices, EEPROM (Electrica ROM), which can be electrically erased, has been
lly Erasable Programmable
ROM) is attracting attention.

[0003] Among these EEPROMs, MOS
A structure in which a floating gate is formed on the channel region of a type transistor element via a gate oxide film having a tunnel oxide film, and a control gate and an erase gate are arranged in parallel on this floating gate via an insulating film. A device consisting of the following is known as a highly integrated EEPROM.

0004

Each gate in the EEPROM is individually formed using photolithography technology. In particular, the control gate and erase gate, which are arranged in parallel on the floating gate, are formed by simultaneous patterning using photolithography at regular intervals and then etching.

Therefore, in order to achieve high integration and miniaturization of EEPROM, it is necessary to reduce the area of these gates as much as possible, and in particular, it is considered to reduce the area of the erase gate from the viewpoint of its function. .

However, because there is a limit to the miniaturization of patterns using current photolithography, it is difficult to obtain erase gates that are significantly reduced in size. This was one obstacle to achieving this goal.

The present invention was made under such circumstances, and is an EEPROM that enables high integration and miniaturization.
This is what we are trying to provide.

[0008]

[Means for Solving the Problems] According to the present invention, a floating gate, a control gate, and an erase gate are provided on a MOS transistor element, and the erase gate covers a side wall portion of an insulating film surrounding the floating gate. An electrically erasable nonvolatile semiconductor memory device is provided which is formed and disposed on the side of the floating gate via the floating gate. Furthermore, according to the present invention, a nonvolatile semiconductor memory device is manufactured which includes a floating gate, a control gate, and an erase gate on a MOS transistor element, and after forming the floating gate and its surface insulating film, a metal A method of manufacturing an electrically erasable nonvolatile semiconductor memory device is provided, which comprises performing deposition and etching to form a remaining metal layer on the side surface of the floating gate.

[0009]

According to the EEPROM of the present invention, since the erase gate is formed and arranged on the side of the floating gate, the area occupied on the surface of the MOS transistor element is significantly reduced. Since such an erase gate can be formed in a self-aligned manner on the side part,
Does not require complicated manufacturing processes.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing example of an EEPROM according to the present invention will be described below with reference to the drawings. First, as shown in FIG. 1, field oxide films 2 are formed at regular intervals on a semiconductor substrate 1 by the Locos oxidation method, and then a gate oxide film 3 is formed on the surface between them by thermal oxidation. A polysilicon pattern 4 doped with impurities (phosphorus or arsenic) for gate formation is formed.

Next, as shown in FIG. 2, HTO (
High Temperature Oxide) film 6
formation (LPCV at 850 °C with SiH4 and N2O
After forming the SOG film 5 (formed by method D) and the SOG film 5, an HTO layer 6 is buried between the polysilicon patterns 4 by etching back.

Next, as shown in FIG. 3, in order to determine the gate length of the floating gate, unnecessary polysilicon 4 and HTO film 6 are etched away by photolithography using photoresist 7 for forming a floating gate. A floating gate (FG) (FIG. 4) made of polysilicon is constructed.

Next, as shown in FIG. 4, after implanting arsenic ions to form the source 8 and drain 9, the interlayer insulating film 10 for isolating the floating gate (FG) and the control gate is thermally oxidized or CVD method (ONO film)
Formed by

Next, as shown in FIG. 5, a photoresist pattern 11 for forming an erase gate and an erase window is formed. This pattern consists of a pattern that completely covers the floating gate as shown in FIG.
Floating gate (FG) as shown in b)
expose a portion of the side and top surface of the

Next, as shown in FIG. 6, the exposed side surfaces of the floating gate (FG) are covered with an erasing insulating film 13 by forming a thermal oxide film or an HTO film. Here, the thickness of the erasing insulating film 13 is made thinner than other interlayer insulating films and oxide films so as to cause tunneling.
Usually, the thickness is preferably 350 to 400 Å.

Next, a polysilicon layer 12 for forming a control gate is formed on the entire surface, and impurity diffusion (phosphorus or arsenic) is performed. A photoresist pattern 14 for a control gate is formed on this, and a polysilicon layer 12 is formed.
At the same time, a control gate (CG) is patterned by subjecting it to anisotropic etching using a dry etching method, and at the same time, as shown in FIG. The erase gate 15 is formed in a self-aligned manner. Through these steps, the floating gate, control gate, and erase gate of the EEPROM of the present invention are basically constructed.

After this, as shown in FIG.
After depositing an insulating film 16 made of PSG, a contact hole 18 was formed, and then a metal wiring 17 was formed, thereby obtaining an EEPROM of the present invention.

[0018] The EEP of the present invention thus obtained
In ROM, the erase gate is formed in a significantly reduced size on the side of the floating gate in a self-aligned manner, so that high integration is possible and manufacturing is simpler. More specifically, it has been found that the area occupied by one EEPROM element can be reduced by about 70 to 85%.

[0019]

[Effects of the Invention] According to the present invention, the area of the erase gate can be reduced, and as a result, the EEPROM can be highly integrated.
High reduction in size can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the manufacturing process of an EEPROM of the present invention, (a) is a plan view, (b) is an AA' cross-sectional view, and (c) is a BB' cross-sectional view. .

FIG. 2 is a BB' cross-sectional explanatory diagram showing each manufacturing process following FIG. 1;

FIG. 3 is an explanatory diagram showing the manufacturing process following FIG. 2, in which (a) is a plan view, (b) is an AA' cross-sectional view, and (c) is B-
It is a B' cross-sectional explanatory diagram.

4 is a manufacturing process explanatory diagram following FIG. 3. FIG.

FIG. 5 is a manufacturing process explanatory diagram following FIG. 4;

6 is a manufacturing process explanatory diagram following FIG. 5. FIG.

7 is a manufacturing process explanatory diagram following FIG. 6. FIG.

8 is a manufacturing process explanatory diagram following FIG. 7. FIG.

[Explanation of symbols]

1 Semiconductor substrate 2 Field oxide film 3 Gate oxide film 4 Polysilicon pattern 5 SOG film 6 HTO film 7 Floating gate forming photoresist 8 Source 9 Drain 10 Interlayer insulation film 11 Photoresist pattern 12 Polysilicon layer 13 Erasing insulation film 14 Photoresist pattern 15 Erase gate 16 Insulating film 17 Metal wiring 18 Contact hole FG Floating gate CG Control gate

Claims (2)

[Claims] 1. A MOS transistor element is provided with a floating gate, a control gate, and an erase gate, and the erase gate is formed on the side of the floating gate through a side wall of an insulating film surrounding the floating gate. An electrically erasable nonvolatile semiconductor memory device. 2. A nonvolatile semiconductor memory device comprising a floating gate, a control gate, and an erase gate on a MOS transistor element is manufactured, and after forming the floating gate and its surface insulating film, metal deposition and 2. The method of manufacturing an electrically erasable nonvolatile semiconductor memory device according to claim 1, further comprising etching to form a remaining metal layer on the side surface of the floating gate.