JPH04237347A - Memory control device - Google Patents

Abstract

PURPOSE:To reduce bank busy queue and to improve memory access performance. CONSTITUTION:Respective memory requests from an arithmetic processor 3 and an I/O processor 4 to a main storage device 1 are divided in each bank number by bank selecting parts 220 to 223 and stored in bank fuffers 210 to 213. Then respective memory access requests are checked by bank busy checking circuits 200 to 203 and a request to an idle bank is inputted to a priority circuit 22. Since the newest passed bank number is registered in a bank number register 24, the bank number with a value obtained by adding '+1' to the registered bank number by a '+1' adder is set up to the highest priority to successively check the bank numbers. The request with the highest priority order is passed and stored in a memory access register 21 and the main storage device 1 is accessed by the request.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a memory control device.
In particular, the present invention relates to a memory control device that controls a main memory device having a plurality of banks.

0002

2. Description of the Related Art Conventionally, this type of memory control device prioritizes devices requesting memory access to the main memory when a bank is vacant, and the request of the device with the highest priority is granted. In order to pass the bus, the configuration was such that a bank number unrelated to the previously passed bank number was passed.

0003

[Problems to be Solved by the Invention] The above-mentioned conventional memory control device is configured to pass a bank number unrelated to the previously passed bank number, so that a device requesting memory access to the main storage device is When issuing access requests in the order of bank numbers, there is a drawback that the number of bank busy waits increases.

0004

[Means for Solving the Problems] A memory control device of the present invention is a memory control device for controlling a main storage device including a plurality of banks having consecutive integer bank numbers and which can be accessed simultaneously. a holding means for holding a memory access request to the main storage device for each bank number; a checking means for checking whether a bank corresponding to the memory access request held by the holding means is free; and an access means for accessing the main storage device by giving priority to a memory access request corresponding to a bank in order from the bank number next to the bank number passed before the memory access request.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an application example of an embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation of this application example.

In FIG. 1, this application example includes a memory control device 2 according to an embodiment of the present invention, a main storage device 1 controlled by the memory control device 2, an arithmetic processing device 3 that accesses the main storage device 2, and an input device. The output processing device 4 is configured to include an output processing device 4.

The main memory device 1 has banks 100 to 103,
The common control unit 104 controls the banks 100 to 103.

The memory control device 2 sends memory access requests from the arithmetic processing device 3 and the input/output processing device 4 to the bank 10.
Bank selection section 2 for selecting each bank number from 0 to 103
20 to 223, bank buffers 210 to 213 that buffer each bank number, bank busy check circuits 200 to 203 that check whether the bank is busy for each bank number, and a bank number register 24 that holds the latest passed bank number. , a +1 adder 23, a priority circuit 22 that prioritizes in the order of the bank number next to the latest bank number that has been bussed among vacant banks, and a priority circuit 22 that handles the memory access request with the highest priority. It is configured to include a memory access register 21 that is held in order to send data to the storage device 1.

Next, the operation of this application example is shown in FIGS. 1 and 2.
This will be explained using the following.

Assume that a memory access request from the arithmetic processing unit 3 accesses the memory control unit 2 in the order of banks 100, 101, 102, and 103. For ease of understanding, each access request is referred to as E0, E1, E2, and E3.

Assume that memory access requests from the input/output processing device 4 are made for banks 103, 100, 101, and 102 in this order. Each access request is I3, I0, I
1, I2.

Each memory access request is sent to the bank selector 22.
The data is divided by bank number from 0 to 223 and stored in bank buffers 210 to 213. Each bank buffer 21
0 to 213 each have two buffers (0 and 1)
. Buffers are retrieved FIFO. If they are simultaneous, the input/output processing device 4 enters first. Each memory access request is then checked by bank busy checks 200-203,
A request for an empty bank enters the priority circuit 22. Since the latest passed bank number is stored in the bank number register 24, the bank number of the value added by +1 by the +1 adder 23 is sequentially checked with top priority. The request with the highest priority passes and the memory access register 21
, and accesses the main storage device 1.

By operating the memory control device 2 in this manner, memory access requests from the arithmetic processing device 3 and the input/output processing device 4 are processed in bank number order (the initial value does not have to be 0). For example, as shown in the time chart of FIG. 2, bank busy waiting can be extremely reduced. In addition, as shown in the time chart of FIG.
Since the access order and the reply order are different, it is necessary to align each memory access request within the devices (arithmetic processing unit 3 and input/output processing unit 4).

[0015]

As explained above, the present invention provides a holding means that holds requests for access to the main storage device from a plurality of devices for each bank number, and a memory access request held by this holding means. A check means for checking whether a bank to be accessed is free or not, and a check method that prioritizes memory access requests corresponding to free banks in order from the bank number next to the bank number that passed before this memory access request. By having an access means for accessing the storage device, priority is given to the bank number next to the bank number passed before the current memory access request, so it is possible to reduce bank busy waiting and improve memory access performance. There are effects that can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of application of an embodiment of the present invention.

FIG. 2 is a time chart showing an example of the operation of this application example.

[Explanation of symbols]

1 Main storage device 2 Memory control device 3 Arithmetic processing device 4 Input/output processing device 100 to 103 Bank 104 Common control section 21 Memory access register 22 Priority circuit 23 +1 adder 24 Bank number register 200 to 203 Bank busy check circuit 21
0~213 Bank buffer 220~223
Bank selection section

Claims (1)

[Claims] 1. A memory control device that controls a main storage device that includes a plurality of banks that have consecutive integer bank numbers and that can be accessed simultaneously, a bank that requests memory access requests from a plurality of devices to the main storage device. holding means for holding each number; checking means for checking whether a bank corresponding to the memory access request held by the holding means is free; 1. A memory control device comprising access means for accessing the main storage device in order of priority starting from the bank number next to the bank number passed before the access request.